charles macneill
/
VL53L1CB
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vl53l1_ll_def.h
00001 00002 /******************************************************************************* 00003 * Copyright (c) 2020, STMicroelectronics - All Rights Reserved 00004 00005 This file is part of VL53L1 Core and is dual licensed, 00006 either 'STMicroelectronics 00007 Proprietary license' 00008 or 'BSD 3-clause "New" or "Revised" License' , at your option. 00009 00010 ******************************************************************************** 00011 00012 'STMicroelectronics Proprietary license' 00013 00014 ******************************************************************************** 00015 00016 License terms: STMicroelectronics Proprietary in accordance with licensing 00017 terms at www.st.com/sla0081 00018 00019 STMicroelectronics confidential 00020 Reproduction and Communication of this document is strictly prohibited unless 00021 specifically authorized in writing by STMicroelectronics. 00022 00023 00024 ******************************************************************************** 00025 00026 Alternatively, VL53L1 Core may be distributed under the terms of 00027 'BSD 3-clause "New" or "Revised" License', in which case the following 00028 provisions apply instead of the ones 00029 mentioned above : 00030 00031 ******************************************************************************** 00032 00033 License terms: BSD 3-clause "New" or "Revised" License. 00034 00035 Redistribution and use in source and binary forms, with or without 00036 modification, are permitted provided that the following conditions are met: 00037 00038 1. Redistributions of source code must retain the above copyright notice, this 00039 list of conditions and the following disclaimer. 00040 00041 2. Redistributions in binary form must reproduce the above copyright notice, 00042 this list of conditions and the following disclaimer in the documentation 00043 and/or other materials provided with the distribution. 00044 00045 3. Neither the name of the copyright holder nor the names of its contributors 00046 may be used to endorse or promote products derived from this software 00047 without specific prior written permission. 00048 00049 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00050 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00051 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00052 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00053 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00054 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00055 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00056 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00057 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00058 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00059 00060 00061 ******************************************************************************** 00062 00063 */ 00064 00065 00066 00067 00068 00069 #ifndef _VL53L1_LL_DEF_H_ 00070 #define _VL53L1_LL_DEF_H_ 00071 00072 #include "vl53l1_error_codes.h" 00073 #include "vl53l1_register_structs.h" 00074 #include "vl53l1_platform_user_config.h" 00075 #include "vl53l1_platform_user_defines.h" 00076 #include "vl53l1_hist_structs.h" 00077 #include "vl53l1_dmax_structs.h" 00078 #include "vl53l1_error_exceptions.h" 00079 00080 #ifdef __cplusplus 00081 extern "C" { 00082 #endif 00083 00084 00085 00086 00087 #define VL53L1_LL_API_IMPLEMENTATION_VER_MAJOR 1 00088 00089 #define VL53L1_LL_API_IMPLEMENTATION_VER_MINOR 1 00090 00091 #define VL53L1_LL_API_IMPLEMENTATION_VER_SUB 48 00092 00093 #define VL53L1_LL_API_IMPLEMENTATION_VER_REVISION 12224 00094 00095 #define VL53L1_LL_API_IMPLEMENTATION_VER_STRING "1.1.48.12224" 00096 00097 00098 #define VL53L1_FIRMWARE_VER_MINIMUM 398 00099 #define VL53L1_FIRMWARE_VER_MAXIMUM 400 00100 00101 00102 00103 00104 #define VL53L1_LL_CALIBRATION_DATA_STRUCT_VERSION 0xECAB0102 00105 00106 00107 00108 00109 #define VL53L1_LL_ZONE_CALIBRATION_DATA_STRUCT_VERSION 0xECAE0101 00110 00111 00112 00113 00114 00115 #define VL53L1_BIN_REC_SIZE 6 00116 00117 #define VL53L1_TIMING_CONF_A_B_SIZE 2 00118 00119 #define VL53L1_FRAME_WAIT_EVENT 6 00120 00121 00122 00123 #define VL53L1_MAX_XTALK_RANGE_RESULTS 5 00124 00125 00126 #define VL53L1_MAX_OFFSET_RANGE_RESULTS 3 00127 00128 00129 #define VL53L1_NVM_MAX_FMT_RANGE_DATA 4 00130 00131 00132 #define VL53L1_NVM_PEAK_RATE_MAP_SAMPLES 25 00133 00134 #define VL53L1_NVM_PEAK_RATE_MAP_WIDTH 5 00135 00136 #define VL53L1_NVM_PEAK_RATE_MAP_HEIGHT 5 00137 00138 00139 00140 00141 #define VL53L1_ERROR_DEVICE_FIRMWARE_TOO_OLD ((VL53L1_Error) - 80) 00142 00143 #define VL53L1_ERROR_DEVICE_FIRMWARE_TOO_NEW ((VL53L1_Error) - 85) 00144 00145 #define VL53L1_ERROR_UNIT_TEST_FAIL ((VL53L1_Error) - 90) 00146 00147 #define VL53L1_ERROR_FILE_READ_FAIL ((VL53L1_Error) - 95) 00148 00149 #define VL53L1_ERROR_FILE_WRITE_FAIL ((VL53L1_Error) - 96) 00150 00151 00152 00153 00154 00155 00156 typedef struct { 00157 uint32_t ll_revision; 00158 uint8_t ll_major; 00159 uint8_t ll_minor; 00160 uint8_t ll_build; 00161 } VL53L1_ll_version_t; 00162 00163 00164 00165 00166 typedef struct { 00167 00168 uint8_t device_test_mode; 00169 uint8_t VL53L1_p_009; 00170 uint32_t timeout_us; 00171 uint16_t target_count_rate_mcps; 00172 00173 uint16_t min_count_rate_limit_mcps; 00174 00175 uint16_t max_count_rate_limit_mcps; 00176 00177 00178 } VL53L1_refspadchar_config_t; 00179 00180 00181 00182 00183 typedef struct { 00184 00185 uint16_t dss_config__target_total_rate_mcps; 00186 00187 uint32_t phasecal_config_timeout_us; 00188 00189 uint32_t mm_config_timeout_us; 00190 00191 uint32_t range_config_timeout_us; 00192 00193 uint8_t num_of_samples; 00194 00195 int16_t algo__crosstalk_extract_min_valid_range_mm; 00196 00197 int16_t algo__crosstalk_extract_max_valid_range_mm; 00198 00199 uint16_t algo__crosstalk_extract_max_valid_rate_kcps; 00200 00201 uint16_t algo__crosstalk_extract_max_sigma_mm; 00202 00203 00204 } VL53L1_xtalkextract_config_t; 00205 00206 00207 00208 00209 typedef struct { 00210 00211 uint16_t dss_config__target_total_rate_mcps; 00212 00213 uint32_t phasecal_config_timeout_us; 00214 00215 uint32_t range_config_timeout_us; 00216 00217 uint32_t mm_config_timeout_us; 00218 00219 uint8_t pre_num_of_samples; 00220 00221 uint8_t mm1_num_of_samples; 00222 00223 uint8_t mm2_num_of_samples; 00224 00225 00226 } VL53L1_offsetcal_config_t; 00227 00228 00229 00230 00231 typedef struct { 00232 00233 uint16_t dss_config__target_total_rate_mcps; 00234 00235 uint32_t phasecal_config_timeout_us; 00236 00237 uint32_t mm_config_timeout_us; 00238 00239 uint32_t range_config_timeout_us; 00240 00241 uint16_t phasecal_num_of_samples; 00242 00243 uint16_t zone_num_of_samples; 00244 00245 00246 } VL53L1_zonecal_config_t; 00247 00248 00249 00250 00251 00252 typedef struct { 00253 00254 VL53L1_DeviceSscArray array_select; 00255 00256 uint8_t VL53L1_p_009; 00257 00258 uint8_t vcsel_start; 00259 00260 uint8_t vcsel_width; 00261 00262 uint32_t timeout_us; 00263 00264 uint16_t rate_limit_mcps; 00265 00266 00267 } VL53L1_ssc_config_t; 00268 00269 00270 00271 00272 typedef struct { 00273 00274 00275 uint32_t algo__crosstalk_compensation_plane_offset_kcps; 00276 00277 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 00278 00279 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 00280 00281 uint32_t nvm_default__crosstalk_compensation_plane_offset_kcps; 00282 00283 int16_t nvm_default__crosstalk_compensation_x_plane_gradient_kcps; 00284 00285 int16_t nvm_default__crosstalk_compensation_y_plane_gradient_kcps; 00286 00287 uint8_t global_crosstalk_compensation_enable; 00288 00289 int16_t histogram_mode_crosstalk_margin_kcps; 00290 00291 int16_t lite_mode_crosstalk_margin_kcps; 00292 00293 uint8_t crosstalk_range_ignore_threshold_mult; 00294 00295 uint16_t crosstalk_range_ignore_threshold_rate_mcps; 00296 00297 int16_t algo__crosstalk_detect_min_valid_range_mm; 00298 00299 int16_t algo__crosstalk_detect_max_valid_range_mm; 00300 00301 uint16_t algo__crosstalk_detect_max_valid_rate_kcps; 00302 00303 uint16_t algo__crosstalk_detect_max_sigma_mm; 00304 00305 00306 00307 } VL53L1_xtalk_config_t; 00308 00309 00310 00311 00312 typedef struct { 00313 00314 00315 uint16_t tp_tuning_parm_version; 00316 00317 uint16_t tp_tuning_parm_key_table_version; 00318 00319 uint16_t tp_tuning_parm_lld_version; 00320 00321 uint8_t tp_init_phase_rtn_lite_long; 00322 00323 uint8_t tp_init_phase_rtn_lite_med; 00324 00325 uint8_t tp_init_phase_rtn_lite_short; 00326 00327 uint8_t tp_init_phase_ref_lite_long; 00328 00329 uint8_t tp_init_phase_ref_lite_med; 00330 00331 uint8_t tp_init_phase_ref_lite_short; 00332 00333 00334 uint8_t tp_init_phase_rtn_hist_long; 00335 00336 uint8_t tp_init_phase_rtn_hist_med; 00337 00338 uint8_t tp_init_phase_rtn_hist_short; 00339 00340 uint8_t tp_init_phase_ref_hist_long; 00341 00342 uint8_t tp_init_phase_ref_hist_med; 00343 00344 uint8_t tp_init_phase_ref_hist_short; 00345 00346 00347 uint8_t tp_consistency_lite_phase_tolerance; 00348 00349 uint8_t tp_phasecal_target; 00350 00351 uint16_t tp_cal_repeat_rate; 00352 00353 uint8_t tp_lite_min_clip; 00354 00355 00356 uint16_t tp_lite_long_sigma_thresh_mm; 00357 00358 uint16_t tp_lite_med_sigma_thresh_mm; 00359 00360 uint16_t tp_lite_short_sigma_thresh_mm; 00361 00362 00363 uint16_t tp_lite_long_min_count_rate_rtn_mcps; 00364 00365 uint16_t tp_lite_med_min_count_rate_rtn_mcps; 00366 00367 uint16_t tp_lite_short_min_count_rate_rtn_mcps; 00368 00369 00370 uint8_t tp_lite_sigma_est_pulse_width_ns; 00371 00372 uint8_t tp_lite_sigma_est_amb_width_ns; 00373 00374 uint8_t tp_lite_sigma_ref_mm; 00375 00376 uint8_t tp_lite_seed_cfg; 00377 00378 uint8_t tp_timed_seed_cfg; 00379 00380 00381 uint8_t tp_lite_quantifier; 00382 00383 uint8_t tp_lite_first_order_select; 00384 00385 00386 uint16_t tp_dss_target_lite_mcps; 00387 00388 uint16_t tp_dss_target_histo_mcps; 00389 00390 uint16_t tp_dss_target_histo_mz_mcps; 00391 00392 uint16_t tp_dss_target_timed_mcps; 00393 00394 uint16_t tp_dss_target_very_short_mcps; 00395 00396 00397 uint32_t tp_phasecal_timeout_lite_us; 00398 00399 uint32_t tp_phasecal_timeout_hist_long_us; 00400 00401 uint32_t tp_phasecal_timeout_hist_med_us; 00402 00403 uint32_t tp_phasecal_timeout_hist_short_us; 00404 00405 00406 uint32_t tp_phasecal_timeout_mz_long_us; 00407 00408 uint32_t tp_phasecal_timeout_mz_med_us; 00409 00410 uint32_t tp_phasecal_timeout_mz_short_us; 00411 00412 uint32_t tp_phasecal_timeout_timed_us; 00413 00414 00415 uint32_t tp_mm_timeout_lite_us; 00416 00417 uint32_t tp_mm_timeout_histo_us; 00418 00419 uint32_t tp_mm_timeout_mz_us; 00420 00421 uint32_t tp_mm_timeout_timed_us; 00422 00423 uint32_t tp_mm_timeout_lpa_us; 00424 00425 00426 uint32_t tp_range_timeout_lite_us; 00427 00428 uint32_t tp_range_timeout_histo_us; 00429 00430 uint32_t tp_range_timeout_mz_us; 00431 00432 uint32_t tp_range_timeout_timed_us; 00433 00434 uint32_t tp_range_timeout_lpa_us; 00435 00436 uint32_t tp_phasecal_patch_power; 00437 00438 uint8_t tp_hist_merge; 00439 00440 uint32_t tp_reset_merge_threshold; 00441 00442 uint8_t tp_hist_merge_max_size; 00443 00444 uint8_t tp_uwr_enable; 00445 int16_t tp_uwr_med_z_1_min; 00446 int16_t tp_uwr_med_z_1_max; 00447 int16_t tp_uwr_med_z_2_min; 00448 int16_t tp_uwr_med_z_2_max; 00449 int16_t tp_uwr_med_z_3_min; 00450 int16_t tp_uwr_med_z_3_max; 00451 int16_t tp_uwr_med_z_4_min; 00452 int16_t tp_uwr_med_z_4_max; 00453 int16_t tp_uwr_med_z_5_min; 00454 int16_t tp_uwr_med_z_5_max; 00455 int16_t tp_uwr_med_z_6_min; 00456 int16_t tp_uwr_med_z_6_max; 00457 int16_t tp_uwr_med_corr_z_1_rangea; 00458 int16_t tp_uwr_med_corr_z_1_rangeb; 00459 int16_t tp_uwr_med_corr_z_2_rangea; 00460 int16_t tp_uwr_med_corr_z_2_rangeb; 00461 int16_t tp_uwr_med_corr_z_3_rangea; 00462 int16_t tp_uwr_med_corr_z_3_rangeb; 00463 int16_t tp_uwr_med_corr_z_4_rangea; 00464 int16_t tp_uwr_med_corr_z_4_rangeb; 00465 int16_t tp_uwr_med_corr_z_5_rangea; 00466 int16_t tp_uwr_med_corr_z_5_rangeb; 00467 int16_t tp_uwr_med_corr_z_6_rangea; 00468 int16_t tp_uwr_med_corr_z_6_rangeb; 00469 int16_t tp_uwr_lng_z_1_min; 00470 int16_t tp_uwr_lng_z_1_max; 00471 int16_t tp_uwr_lng_z_2_min; 00472 int16_t tp_uwr_lng_z_2_max; 00473 int16_t tp_uwr_lng_z_3_min; 00474 int16_t tp_uwr_lng_z_3_max; 00475 int16_t tp_uwr_lng_z_4_min; 00476 int16_t tp_uwr_lng_z_4_max; 00477 int16_t tp_uwr_lng_z_5_min; 00478 int16_t tp_uwr_lng_z_5_max; 00479 int16_t tp_uwr_lng_corr_z_1_rangea; 00480 int16_t tp_uwr_lng_corr_z_1_rangeb; 00481 int16_t tp_uwr_lng_corr_z_2_rangea; 00482 int16_t tp_uwr_lng_corr_z_2_rangeb; 00483 int16_t tp_uwr_lng_corr_z_3_rangea; 00484 int16_t tp_uwr_lng_corr_z_3_rangeb; 00485 int16_t tp_uwr_lng_corr_z_4_rangea; 00486 int16_t tp_uwr_lng_corr_z_4_rangeb; 00487 int16_t tp_uwr_lng_corr_z_5_rangea; 00488 int16_t tp_uwr_lng_corr_z_5_rangeb; 00489 00490 } VL53L1_tuning_parm_storage_t; 00491 00492 00493 00494 00495 00496 typedef struct { 00497 00498 uint8_t x_centre; 00499 uint8_t y_centre; 00500 00501 } VL53L1_optical_centre_t; 00502 00503 00504 00505 00506 typedef struct { 00507 00508 uint8_t x_centre; 00509 uint8_t y_centre; 00510 uint8_t width; 00511 uint8_t height; 00512 00513 } VL53L1_user_zone_t; 00514 00515 00516 00517 00518 typedef struct { 00519 00520 uint8_t max_zones; 00521 uint8_t active_zones; 00522 00523 00524 00525 VL53L1_histogram_config_t multizone_hist_cfg; 00526 00527 VL53L1_user_zone_t user_zones[VL53L1_MAX_USER_ZONES]; 00528 00529 00530 uint8_t bin_config[VL53L1_MAX_USER_ZONES]; 00531 00532 00533 } VL53L1_zone_config_t; 00534 00535 00536 00537 typedef struct { 00538 00539 00540 VL53L1_GPIO_Interrupt_Mode intr_mode_distance; 00541 00542 00543 VL53L1_GPIO_Interrupt_Mode intr_mode_rate; 00544 00545 00546 uint8_t intr_new_measure_ready; 00547 00548 00549 uint8_t intr_no_target; 00550 00551 00552 uint8_t intr_combined_mode; 00553 00554 00555 00556 00557 00558 uint16_t threshold_distance_high; 00559 00560 00561 uint16_t threshold_distance_low; 00562 00563 00564 uint16_t threshold_rate_high; 00565 00566 00567 uint16_t threshold_rate_low; 00568 00569 } VL53L1_GPIO_interrupt_config_t; 00570 00571 00572 00573 00574 typedef struct { 00575 00576 00577 uint8_t vhv_loop_bound; 00578 00579 00580 uint8_t is_low_power_auto_mode; 00581 00582 00583 uint8_t low_power_auto_range_count; 00584 00585 00586 uint8_t saved_interrupt_config; 00587 00588 00589 uint8_t saved_vhv_init; 00590 00591 00592 uint8_t saved_vhv_timeout; 00593 00594 00595 uint8_t first_run_phasecal_result; 00596 00597 00598 uint32_t dss__total_rate_per_spad_mcps; 00599 00600 00601 uint16_t dss__required_spads; 00602 00603 } VL53L1_low_power_auto_data_t; 00604 00605 00606 00607 00608 00609 00610 00611 typedef struct { 00612 00613 00614 uint8_t smudge_corr_enabled; 00615 00616 00617 uint8_t smudge_corr_apply_enabled; 00618 00619 00620 uint8_t smudge_corr_single_apply; 00621 00622 00623 00624 00625 uint16_t smudge_margin; 00626 00627 00628 uint32_t noise_margin; 00629 00630 00631 uint32_t user_xtalk_offset_limit; 00632 00633 00634 uint8_t user_xtalk_offset_limit_hi; 00635 00636 00637 uint32_t sample_limit; 00638 00639 00640 uint32_t single_xtalk_delta; 00641 00642 00643 uint32_t averaged_xtalk_delta; 00644 00645 00646 uint32_t smudge_corr_clip_limit; 00647 00648 00649 uint32_t smudge_corr_ambient_threshold; 00650 00651 00652 uint8_t scaler_calc_method; 00653 00654 00655 int16_t x_gradient_scaler; 00656 00657 00658 int16_t y_gradient_scaler; 00659 00660 00661 uint8_t user_scaler_set; 00662 00663 00664 uint32_t nodetect_ambient_threshold; 00665 00666 00667 uint32_t nodetect_sample_limit; 00668 00669 00670 uint32_t nodetect_xtalk_offset; 00671 00672 00673 uint16_t nodetect_min_range_mm; 00674 00675 00676 uint32_t max_smudge_factor; 00677 00678 } VL53L1_smudge_corrector_config_t; 00679 00680 00681 00682 typedef struct { 00683 00684 00685 uint32_t current_samples; 00686 00687 00688 uint32_t required_samples; 00689 00690 00691 uint64_t accumulator; 00692 00693 00694 uint32_t nodetect_counter; 00695 00696 } VL53L1_smudge_corrector_internals_t; 00697 00698 00699 00700 typedef struct { 00701 00702 00703 uint8_t smudge_corr_valid; 00704 00705 00706 uint8_t smudge_corr_clipped; 00707 00708 00709 uint8_t single_xtalk_delta_flag; 00710 00711 00712 uint8_t averaged_xtalk_delta_flag; 00713 00714 00715 uint8_t sample_limit_exceeded_flag; 00716 00717 00718 uint8_t gradient_zero_flag; 00719 00720 00721 uint8_t new_xtalk_applied_flag; 00722 00723 00724 uint32_t algo__crosstalk_compensation_plane_offset_kcps; 00725 00726 00727 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 00728 00729 00730 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 00731 00732 00733 } VL53L1_smudge_corrector_data_t; 00734 00735 00736 00737 00738 00739 typedef struct { 00740 00741 00742 00743 uint8_t range_id; 00744 00745 uint32_t time_stamp; 00746 00747 uint8_t VL53L1_p_015; 00748 00749 uint8_t VL53L1_p_022; 00750 00751 uint8_t VL53L1_p_025; 00752 00753 uint8_t VL53L1_p_026; 00754 00755 uint8_t VL53L1_p_016; 00756 00757 uint8_t VL53L1_p_027; 00758 00759 00760 uint16_t width; 00761 00762 uint8_t VL53L1_p_030; 00763 00764 00765 uint16_t fast_osc_frequency; 00766 00767 uint16_t zero_distance_phase; 00768 00769 uint16_t VL53L1_p_006; 00770 00771 00772 uint32_t total_periods_elapsed; 00773 00774 00775 uint32_t peak_duration_us; 00776 00777 00778 uint32_t woi_duration_us; 00779 00780 00781 00782 00783 00784 uint32_t VL53L1_p_020; 00785 00786 uint32_t VL53L1_p_021; 00787 00788 int32_t VL53L1_p_013; 00789 00790 00791 00792 00793 uint16_t peak_signal_count_rate_mcps; 00794 00795 uint16_t avg_signal_count_rate_mcps; 00796 00797 uint16_t ambient_count_rate_mcps; 00798 00799 uint16_t total_rate_per_spad_mcps; 00800 00801 uint32_t VL53L1_p_012; 00802 00803 00804 00805 00806 uint16_t VL53L1_p_005; 00807 00808 00809 00810 00811 uint16_t VL53L1_p_028; 00812 00813 uint16_t VL53L1_p_014; 00814 00815 uint16_t VL53L1_p_029; 00816 00817 00818 00819 00820 int16_t min_range_mm; 00821 00822 int16_t median_range_mm; 00823 00824 int16_t max_range_mm; 00825 00826 00827 00828 00829 uint8_t range_status; 00830 00831 } VL53L1_range_data_t; 00832 00833 00834 00835 00836 typedef struct { 00837 00838 VL53L1_DeviceState cfg_device_state; 00839 00840 VL53L1_DeviceState rd_device_state; 00841 00842 uint8_t zone_id; 00843 00844 uint8_t stream_count; 00845 00846 00847 int16_t VL53L1_p_007[VL53L1_MAX_AMBIENT_DMAX_VALUES]; 00848 00849 int16_t wrap_dmax_mm; 00850 00851 00852 uint8_t device_status; 00853 00854 00855 uint8_t max_results; 00856 00857 uint8_t active_results; 00858 00859 VL53L1_range_data_t VL53L1_p_002[VL53L1_MAX_RANGE_RESULTS]; 00860 00861 VL53L1_range_data_t xmonitor; 00862 00863 VL53L1_smudge_corrector_data_t smudge_corrector_data; 00864 00865 00866 00867 } VL53L1_range_results_t; 00868 00869 00870 00871 00872 typedef struct { 00873 00874 uint8_t no_of_samples; 00875 00876 uint32_t rate_per_spad_kcps_sum; 00877 00878 uint32_t rate_per_spad_kcps_avg; 00879 00880 int32_t signal_total_events_sum; 00881 00882 int32_t signal_total_events_avg; 00883 00884 uint32_t sigma_mm_sum; 00885 00886 uint32_t sigma_mm_avg; 00887 00888 uint32_t median_phase_sum; 00889 00890 uint32_t median_phase_avg; 00891 00892 00893 } VL53L1_xtalk_range_data_t; 00894 00895 00896 00897 00898 typedef struct { 00899 00900 VL53L1_Error cal_status; 00901 00902 uint8_t num_of_samples_status; 00903 00904 uint8_t zero_samples_status; 00905 00906 uint8_t max_sigma_status; 00907 00908 uint8_t max_results; 00909 00910 uint8_t active_results; 00911 00912 00913 VL53L1_xtalk_range_data_t 00914 VL53L1_p_002[VL53L1_MAX_XTALK_RANGE_RESULTS]; 00915 00916 VL53L1_histogram_bin_data_t central_histogram_sum; 00917 00918 VL53L1_histogram_bin_data_t central_histogram_avg; 00919 00920 uint8_t central_histogram__window_start; 00921 00922 uint8_t central_histogram__window_end; 00923 00924 VL53L1_histogram_bin_data_t 00925 histogram_avg_1[VL53L1_MAX_XTALK_RANGE_RESULTS]; 00926 00927 VL53L1_histogram_bin_data_t 00928 histogram_avg_2[VL53L1_MAX_XTALK_RANGE_RESULTS]; 00929 00930 VL53L1_histogram_bin_data_t 00931 xtalk_avg[VL53L1_MAX_XTALK_RANGE_RESULTS]; 00932 00933 00934 } VL53L1_xtalk_range_results_t; 00935 00936 00937 00938 00939 typedef struct { 00940 00941 uint8_t preset_mode; 00942 00943 uint8_t dss_config__roi_mode_control; 00944 00945 uint16_t dss_config__manual_effective_spads_select; 00946 00947 uint8_t no_of_samples; 00948 00949 uint32_t effective_spads; 00950 00951 uint32_t peak_rate_mcps; 00952 00953 uint32_t VL53L1_p_005; 00954 00955 int32_t median_range_mm; 00956 00957 int32_t range_mm_offset; 00958 00959 00960 } VL53L1_offset_range_data_t; 00961 00962 00963 00964 00965 typedef struct { 00966 00967 int16_t cal_distance_mm; 00968 00969 uint16_t cal_reflectance_pc; 00970 00971 VL53L1_Error cal_status; 00972 00973 uint8_t cal_report; 00974 00975 uint8_t max_results; 00976 00977 uint8_t active_results; 00978 00979 VL53L1_offset_range_data_t 00980 VL53L1_p_002[VL53L1_MAX_OFFSET_RANGE_RESULTS]; 00981 00982 00983 } VL53L1_offset_range_results_t; 00984 00985 00986 00987 00988 typedef struct { 00989 00990 uint16_t result__mm_inner_actual_effective_spads; 00991 00992 uint16_t result__mm_outer_actual_effective_spads; 00993 00994 uint16_t result__mm_inner_peak_signal_count_rtn_mcps; 00995 00996 uint16_t result__mm_outer_peak_signal_count_rtn_mcps; 00997 00998 00999 } VL53L1_additional_offset_cal_data_t; 01000 01001 01002 01003 typedef struct { 01004 int16_t short_a_offset_mm; 01005 int16_t short_b_offset_mm; 01006 int16_t medium_a_offset_mm; 01007 int16_t medium_b_offset_mm; 01008 int16_t long_a_offset_mm; 01009 int16_t long_b_offset_mm; 01010 } VL53L1_per_vcsel_period_offset_cal_data_t; 01011 01012 01013 01014 01015 01016 typedef struct { 01017 01018 uint32_t VL53L1_p_020; 01019 01020 uint32_t VL53L1_p_021; 01021 01022 uint16_t VL53L1_p_014; 01023 01024 uint8_t range_status; 01025 01026 01027 } VL53L1_object_data_t; 01028 01029 01030 01031 01032 typedef struct { 01033 01034 VL53L1_DeviceState cfg_device_state; 01035 01036 VL53L1_DeviceState rd_device_state; 01037 01038 uint8_t zone_id; 01039 01040 uint8_t stream_count; 01041 01042 uint8_t max_objects; 01043 01044 uint8_t active_objects; 01045 01046 VL53L1_object_data_t VL53L1_p_002[VL53L1_MAX_RANGE_RESULTS]; 01047 01048 01049 VL53L1_object_data_t xmonitor; 01050 01051 01052 } VL53L1_zone_objects_t; 01053 01054 01055 01056 01057 01058 01059 typedef struct { 01060 01061 uint8_t max_zones; 01062 01063 uint8_t active_zones; 01064 01065 VL53L1_zone_objects_t VL53L1_p_002[VL53L1_MAX_USER_ZONES]; 01066 01067 01068 } VL53L1_zone_results_t; 01069 01070 01071 01072 01073 typedef struct { 01074 01075 VL53L1_DeviceState rd_device_state; 01076 01077 01078 uint8_t number_of_ambient_bins; 01079 01080 01081 uint16_t result__dss_actual_effective_spads; 01082 01083 uint8_t VL53L1_p_009; 01084 01085 uint32_t total_periods_elapsed; 01086 01087 01088 int32_t ambient_events_sum; 01089 01090 01091 } VL53L1_zone_hist_info_t; 01092 01093 01094 01095 01096 typedef struct { 01097 01098 uint8_t max_zones; 01099 01100 uint8_t active_zones; 01101 01102 VL53L1_zone_hist_info_t VL53L1_p_002[VL53L1_MAX_USER_ZONES]; 01103 01104 01105 } VL53L1_zone_histograms_t; 01106 01107 01108 01109 01110 typedef struct { 01111 01112 uint32_t no_of_samples; 01113 01114 uint32_t effective_spads; 01115 01116 uint32_t peak_rate_mcps; 01117 01118 uint32_t VL53L1_p_014; 01119 01120 uint32_t VL53L1_p_005; 01121 01122 int32_t median_range_mm; 01123 01124 int32_t range_mm_offset; 01125 01126 01127 } VL53L1_zone_calibration_data_t; 01128 01129 01130 01131 01132 01133 01134 typedef struct { 01135 01136 uint32_t struct_version; 01137 01138 VL53L1_DevicePresetModes preset_mode; 01139 01140 VL53L1_DeviceZonePreset zone_preset; 01141 01142 int16_t cal_distance_mm; 01143 01144 uint16_t cal_reflectance_pc; 01145 01146 uint16_t phasecal_result__reference_phase; 01147 01148 uint16_t zero_distance_phase; 01149 01150 VL53L1_Error cal_status; 01151 01152 uint8_t max_zones; 01153 01154 uint8_t active_zones; 01155 01156 VL53L1_zone_calibration_data_t VL53L1_p_002[VL53L1_MAX_USER_ZONES]; 01157 01158 01159 } VL53L1_zone_calibration_results_t; 01160 01161 01162 01163 01164 01165 typedef struct { 01166 01167 int16_t cal_distance_mm; 01168 01169 uint16_t cal_reflectance_pc; 01170 01171 uint16_t max_samples; 01172 01173 uint16_t width; 01174 01175 uint16_t height; 01176 01177 uint16_t peak_rate_mcps[VL53L1_NVM_PEAK_RATE_MAP_SAMPLES]; 01178 01179 01180 } VL53L1_cal_peak_rate_map_t; 01181 01182 01183 01184 01185 typedef struct { 01186 01187 uint8_t expected_stream_count; 01188 01189 uint8_t expected_gph_id; 01190 01191 uint8_t dss_mode; 01192 01193 uint16_t dss_requested_effective_spad_count; 01194 01195 uint8_t seed_cfg; 01196 01197 uint8_t initial_phase_seed; 01198 01199 01200 uint8_t roi_config__user_roi_centre_spad; 01201 01202 uint8_t roi_config__user_roi_requested_global_xy_size; 01203 01204 01205 } VL53L1_zone_private_dyn_cfg_t; 01206 01207 01208 01209 01210 typedef struct { 01211 01212 uint8_t max_zones; 01213 01214 uint8_t active_zones; 01215 01216 VL53L1_zone_private_dyn_cfg_t VL53L1_p_002[VL53L1_MAX_USER_ZONES]; 01217 01218 01219 } VL53L1_zone_private_dyn_cfgs_t; 01220 01221 01222 01223 typedef struct { 01224 01225 uint32_t algo__crosstalk_compensation_plane_offset_kcps; 01226 01227 int16_t algo__crosstalk_compensation_x_plane_gradient_kcps; 01228 01229 int16_t algo__crosstalk_compensation_y_plane_gradient_kcps; 01230 01231 uint32_t algo__xtalk_cpo_HistoMerge_kcps[VL53L1_BIN_REC_SIZE]; 01232 01233 01234 } VL53L1_xtalk_calibration_results_t; 01235 01236 01237 01238 01239 typedef struct { 01240 01241 01242 uint32_t sample_count; 01243 01244 01245 uint32_t pll_period_mm; 01246 01247 01248 uint32_t peak_duration_us_sum; 01249 01250 01251 uint32_t effective_spad_count_sum; 01252 01253 01254 uint32_t zero_distance_phase_sum; 01255 01256 01257 uint32_t zero_distance_phase_avg; 01258 01259 01260 int32_t event_scaler_sum; 01261 01262 01263 int32_t event_scaler_avg; 01264 01265 01266 int32_t signal_events_sum; 01267 01268 01269 uint32_t xtalk_rate_kcps_per_spad; 01270 01271 01272 int32_t xtalk_start_phase; 01273 01274 01275 int32_t xtalk_end_phase; 01276 01277 01278 int32_t xtalk_width_phase; 01279 01280 01281 int32_t target_start_phase; 01282 01283 01284 int32_t target_end_phase; 01285 01286 01287 int32_t target_width_phase; 01288 01289 01290 int32_t effective_width; 01291 01292 01293 int32_t event_scaler; 01294 01295 01296 uint8_t VL53L1_p_015; 01297 01298 01299 uint8_t VL53L1_p_016; 01300 01301 01302 uint8_t target_start; 01303 01304 01305 int32_t max_shape_value; 01306 01307 01308 int32_t bin_data_sums[VL53L1_XTALK_HISTO_BINS]; 01309 01310 } VL53L1_hist_xtalk_extract_data_t; 01311 01312 01313 01314 01315 typedef struct { 01316 01317 uint16_t standard_ranging_gain_factor; 01318 01319 uint16_t histogram_ranging_gain_factor; 01320 01321 01322 } VL53L1_gain_calibration_data_t; 01323 01324 01325 01326 01327 typedef struct { 01328 01329 VL53L1_DeviceState cfg_device_state; 01330 01331 uint8_t cfg_stream_count; 01332 01333 uint8_t cfg_internal_stream_count; 01334 01335 uint8_t cfg_internal_stream_count_val; 01336 01337 uint8_t cfg_gph_id; 01338 01339 uint8_t cfg_timing_status; 01340 01341 uint8_t cfg_zone_id; 01342 01343 01344 VL53L1_DeviceState rd_device_state; 01345 01346 uint8_t rd_stream_count; 01347 01348 uint8_t rd_internal_stream_count; 01349 01350 uint8_t rd_internal_stream_count_val; 01351 01352 uint8_t rd_gph_id; 01353 01354 uint8_t rd_timing_status; 01355 01356 uint8_t rd_zone_id; 01357 01358 01359 } VL53L1_ll_driver_state_t; 01360 01361 01362 01363 01364 typedef struct { 01365 01366 uint8_t wait_method; 01367 01368 VL53L1_DevicePresetModes preset_mode; 01369 01370 VL53L1_DeviceZonePreset zone_preset; 01371 01372 VL53L1_DeviceMeasurementModes measurement_mode; 01373 01374 VL53L1_OffsetCalibrationMode offset_calibration_mode; 01375 01376 VL53L1_OffsetCorrectionMode offset_correction_mode; 01377 01378 VL53L1_DeviceDmaxMode dmax_mode; 01379 01380 uint32_t phasecal_config_timeout_us; 01381 01382 uint32_t mm_config_timeout_us; 01383 01384 uint32_t range_config_timeout_us; 01385 01386 uint32_t inter_measurement_period_ms; 01387 01388 uint16_t dss_config__target_total_rate_mcps; 01389 01390 uint32_t fw_ready_poll_duration_ms; 01391 01392 uint8_t fw_ready; 01393 01394 uint8_t debug_mode; 01395 01396 01397 01398 VL53L1_ll_version_t version; 01399 01400 01401 VL53L1_ll_driver_state_t ll_state; 01402 01403 01404 VL53L1_GPIO_interrupt_config_t gpio_interrupt_config; 01405 01406 01407 VL53L1_customer_nvm_managed_t customer; 01408 VL53L1_cal_peak_rate_map_t cal_peak_rate_map; 01409 VL53L1_additional_offset_cal_data_t add_off_cal_data; 01410 VL53L1_dmax_calibration_data_t fmt_dmax_cal; 01411 VL53L1_dmax_calibration_data_t cust_dmax_cal; 01412 VL53L1_gain_calibration_data_t gain_cal; 01413 VL53L1_user_zone_t mm_roi; 01414 VL53L1_optical_centre_t optical_centre; 01415 VL53L1_zone_config_t zone_cfg; 01416 01417 01418 VL53L1_tuning_parm_storage_t tuning_parms; 01419 01420 01421 uint8_t rtn_good_spads[VL53L1_RTN_SPAD_BUFFER_SIZE]; 01422 01423 01424 VL53L1_refspadchar_config_t refspadchar; 01425 VL53L1_ssc_config_t ssc_cfg; 01426 VL53L1_hist_post_process_config_t histpostprocess; 01427 VL53L1_hist_gen3_dmax_config_t dmax_cfg; 01428 VL53L1_xtalkextract_config_t xtalk_extract_cfg; 01429 VL53L1_xtalk_config_t xtalk_cfg; 01430 VL53L1_offsetcal_config_t offsetcal_cfg; 01431 VL53L1_zonecal_config_t zonecal_cfg; 01432 01433 01434 VL53L1_static_nvm_managed_t stat_nvm; 01435 VL53L1_histogram_config_t hist_cfg; 01436 VL53L1_static_config_t stat_cfg; 01437 VL53L1_general_config_t gen_cfg; 01438 VL53L1_timing_config_t tim_cfg; 01439 VL53L1_dynamic_config_t dyn_cfg; 01440 VL53L1_system_control_t sys_ctrl; 01441 VL53L1_system_results_t sys_results; 01442 VL53L1_nvm_copy_data_t nvm_copy_data; 01443 01444 01445 VL53L1_histogram_bin_data_t hist_data; 01446 VL53L1_histogram_bin_data_t hist_xtalk; 01447 01448 01449 VL53L1_xtalk_histogram_data_t xtalk_shapes; 01450 VL53L1_xtalk_range_results_t xtalk_results; 01451 VL53L1_xtalk_calibration_results_t xtalk_cal; 01452 VL53L1_hist_xtalk_extract_data_t xtalk_extract; 01453 01454 01455 VL53L1_offset_range_results_t offset_results; 01456 01457 01458 VL53L1_core_results_t core_results; 01459 VL53L1_debug_results_t dbg_results; 01460 01461 VL53L1_smudge_corrector_config_t smudge_correct_config; 01462 01463 VL53L1_smudge_corrector_internals_t smudge_corrector_internals; 01464 01465 01466 01467 01468 VL53L1_low_power_auto_data_t low_power_auto_data; 01469 01470 01471 #ifdef PAL_EXTENDED 01472 01473 VL53L1_patch_results_t patch_results; 01474 VL53L1_shadow_core_results_t shadow_core_results; 01475 VL53L1_shadow_system_results_t shadow_sys_results; 01476 VL53L1_prev_shadow_core_results_t prev_shadow_core_results; 01477 VL53L1_prev_shadow_system_results_t prev_shadow_sys_results; 01478 #endif 01479 uint8_t wArea1[1536]; 01480 uint8_t wArea2[512]; 01481 VL53L1_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data; 01482 01483 uint8_t bin_rec_pos; 01484 01485 uint8_t pos_before_next_recom; 01486 01487 int32_t multi_bins_rec[VL53L1_BIN_REC_SIZE] 01488 [VL53L1_TIMING_CONF_A_B_SIZE][VL53L1_HISTOGRAM_BUFFER_SIZE]; 01489 01490 int16_t PreviousRangeMilliMeter[VL53L1_MAX_RANGE_RESULTS]; 01491 uint8_t PreviousRangeStatus[VL53L1_MAX_RANGE_RESULTS]; 01492 uint8_t PreviousExtendedRange[VL53L1_MAX_RANGE_RESULTS]; 01493 uint8_t PreviousStreamCount; 01494 01495 } VL53L1_LLDriverData_t; 01496 01497 01498 01499 01500 typedef struct { 01501 01502 01503 VL53L1_range_results_t range_results; 01504 01505 01506 VL53L1_zone_private_dyn_cfgs_t zone_dyn_cfgs; 01507 01508 01509 VL53L1_zone_results_t zone_results; 01510 VL53L1_zone_histograms_t zone_hists; 01511 VL53L1_zone_calibration_results_t zone_cal; 01512 01513 } VL53L1_LLDriverResults_t; 01514 01515 01516 01517 01518 typedef struct { 01519 01520 uint32_t struct_version; 01521 VL53L1_customer_nvm_managed_t customer; 01522 VL53L1_dmax_calibration_data_t fmt_dmax_cal; 01523 VL53L1_dmax_calibration_data_t cust_dmax_cal; 01524 VL53L1_additional_offset_cal_data_t add_off_cal_data; 01525 VL53L1_optical_centre_t optical_centre; 01526 VL53L1_xtalk_histogram_data_t xtalkhisto; 01527 VL53L1_gain_calibration_data_t gain_cal; 01528 VL53L1_cal_peak_rate_map_t cal_peak_rate_map; 01529 VL53L1_per_vcsel_period_offset_cal_data_t per_vcsel_cal_data; 01530 01531 } VL53L1_calibration_data_t; 01532 01533 01534 01535 01536 typedef struct { 01537 01538 VL53L1_customer_nvm_managed_t customer; 01539 VL53L1_xtalkextract_config_t xtalk_extract_cfg; 01540 VL53L1_xtalk_config_t xtalk_cfg; 01541 VL53L1_histogram_bin_data_t hist_data; 01542 VL53L1_xtalk_histogram_data_t xtalk_shapes; 01543 VL53L1_xtalk_range_results_t xtalk_results; 01544 01545 } VL53L1_xtalk_debug_data_t; 01546 01547 01548 01549 01550 typedef struct { 01551 01552 VL53L1_customer_nvm_managed_t customer; 01553 VL53L1_dmax_calibration_data_t fmt_dmax_cal; 01554 VL53L1_dmax_calibration_data_t cust_dmax_cal; 01555 VL53L1_additional_offset_cal_data_t add_off_cal_data; 01556 VL53L1_offset_range_results_t offset_results; 01557 01558 } VL53L1_offset_debug_data_t; 01559 01560 01561 01562 01563 typedef struct { 01564 uint16_t vl53l1_tuningparm_version; 01565 uint16_t vl53l1_tuningparm_key_table_version; 01566 uint16_t vl53l1_tuningparm_lld_version; 01567 uint8_t vl53l1_tuningparm_hist_algo_select; 01568 uint8_t vl53l1_tuningparm_hist_target_order; 01569 uint8_t vl53l1_tuningparm_hist_filter_woi_0; 01570 uint8_t vl53l1_tuningparm_hist_filter_woi_1; 01571 uint8_t vl53l1_tuningparm_hist_amb_est_method; 01572 uint8_t vl53l1_tuningparm_hist_amb_thresh_sigma_0; 01573 uint8_t vl53l1_tuningparm_hist_amb_thresh_sigma_1; 01574 int32_t vl53l1_tuningparm_hist_min_amb_thresh_events; 01575 uint16_t vl53l1_tuningparm_hist_amb_events_scaler; 01576 uint16_t vl53l1_tuningparm_hist_noise_threshold; 01577 int32_t vl53l1_tuningparm_hist_signal_total_events_limit; 01578 uint8_t vl53l1_tuningparm_hist_sigma_est_ref_mm; 01579 uint16_t vl53l1_tuningparm_hist_sigma_thresh_mm; 01580 uint16_t vl53l1_tuningparm_hist_gain_factor; 01581 uint8_t vl53l1_tuningparm_consistency_hist_phase_tolerance; 01582 uint16_t vl53l1_tuningparm_consistency_hist_min_max_tolerance_mm; 01583 uint8_t vl53l1_tuningparm_consistency_hist_event_sigma; 01584 uint16_t vl53l1_tuningparm_consistency_hist_event_sigma_min_spad_limit; 01585 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_long_range; 01586 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_med_range; 01587 uint8_t vl53l1_tuningparm_initial_phase_rtn_histo_short_range; 01588 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_long_range; 01589 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_med_range; 01590 uint8_t vl53l1_tuningparm_initial_phase_ref_histo_short_range; 01591 int16_t vl53l1_tuningparm_xtalk_detect_min_valid_range_mm; 01592 int16_t vl53l1_tuningparm_xtalk_detect_max_valid_range_mm; 01593 uint16_t vl53l1_tuningparm_xtalk_detect_max_sigma_mm; 01594 uint16_t vl53l1_tuningparm_xtalk_detect_min_max_tolerance; 01595 uint16_t vl53l1_tuningparm_xtalk_detect_max_valid_rate_kcps; 01596 uint8_t vl53l1_tuningparm_xtalk_detect_event_sigma; 01597 int16_t vl53l1_tuningparm_hist_xtalk_margin_kcps; 01598 uint8_t vl53l1_tuningparm_consistency_lite_phase_tolerance; 01599 uint8_t vl53l1_tuningparm_phasecal_target; 01600 uint16_t vl53l1_tuningparm_lite_cal_repeat_rate; 01601 uint16_t vl53l1_tuningparm_lite_ranging_gain_factor; 01602 uint8_t vl53l1_tuningparm_lite_min_clip_mm; 01603 uint16_t vl53l1_tuningparm_lite_long_sigma_thresh_mm; 01604 uint16_t vl53l1_tuningparm_lite_med_sigma_thresh_mm; 01605 uint16_t vl53l1_tuningparm_lite_short_sigma_thresh_mm; 01606 uint16_t vl53l1_tuningparm_lite_long_min_count_rate_rtn_mcps; 01607 uint16_t vl53l1_tuningparm_lite_med_min_count_rate_rtn_mcps; 01608 uint16_t vl53l1_tuningparm_lite_short_min_count_rate_rtn_mcps; 01609 uint8_t vl53l1_tuningparm_lite_sigma_est_pulse_width; 01610 uint8_t vl53l1_tuningparm_lite_sigma_est_amb_width_ns; 01611 uint8_t vl53l1_tuningparm_lite_sigma_ref_mm; 01612 uint8_t vl53l1_tuningparm_lite_rit_mult; 01613 uint8_t vl53l1_tuningparm_lite_seed_config; 01614 uint8_t vl53l1_tuningparm_lite_quantifier; 01615 uint8_t vl53l1_tuningparm_lite_first_order_select; 01616 int16_t vl53l1_tuningparm_lite_xtalk_margin_kcps; 01617 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_long_range; 01618 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_med_range; 01619 uint8_t vl53l1_tuningparm_initial_phase_rtn_lite_short_range; 01620 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_long_range; 01621 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_med_range; 01622 uint8_t vl53l1_tuningparm_initial_phase_ref_lite_short_range; 01623 uint8_t vl53l1_tuningparm_timed_seed_config; 01624 uint8_t vl53l1_tuningparm_dmax_cfg_signal_thresh_sigma; 01625 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_0; 01626 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_1; 01627 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_2; 01628 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_3; 01629 uint16_t vl53l1_tuningparm_dmax_cfg_reflectance_array_4; 01630 uint8_t vl53l1_tuningparm_vhv_loopbound; 01631 uint8_t vl53l1_tuningparm_refspadchar_device_test_mode; 01632 uint8_t vl53l1_tuningparm_refspadchar_vcsel_period; 01633 uint32_t vl53l1_tuningparm_refspadchar_phasecal_timeout_us; 01634 uint16_t vl53l1_tuningparm_refspadchar_target_count_rate_mcps; 01635 uint16_t vl53l1_tuningparm_refspadchar_min_countrate_limit_mcps; 01636 uint16_t vl53l1_tuningparm_refspadchar_max_countrate_limit_mcps; 01637 uint8_t vl53l1_tuningparm_xtalk_extract_num_of_samples; 01638 int16_t vl53l1_tuningparm_xtalk_extract_min_filter_thresh_mm; 01639 int16_t vl53l1_tuningparm_xtalk_extract_max_filter_thresh_mm; 01640 uint16_t vl53l1_tuningparm_xtalk_extract_dss_rate_mcps; 01641 uint32_t vl53l1_tuningparm_xtalk_extract_phasecal_timeout_us; 01642 uint16_t vl53l1_tuningparm_xtalk_extract_max_valid_rate_kcps; 01643 uint16_t vl53l1_tuningparm_xtalk_extract_sigma_threshold_mm; 01644 uint32_t vl53l1_tuningparm_xtalk_extract_dss_timeout_us; 01645 uint32_t vl53l1_tuningparm_xtalk_extract_bin_timeout_us; 01646 uint16_t vl53l1_tuningparm_offset_cal_dss_rate_mcps; 01647 uint32_t vl53l1_tuningparm_offset_cal_phasecal_timeout_us; 01648 uint32_t vl53l1_tuningparm_offset_cal_mm_timeout_us; 01649 uint32_t vl53l1_tuningparm_offset_cal_range_timeout_us; 01650 uint8_t vl53l1_tuningparm_offset_cal_pre_samples; 01651 uint8_t vl53l1_tuningparm_offset_cal_mm1_samples; 01652 uint8_t vl53l1_tuningparm_offset_cal_mm2_samples; 01653 uint16_t vl53l1_tuningparm_zone_cal_dss_rate_mcps; 01654 uint32_t vl53l1_tuningparm_zone_cal_phasecal_timeout_us; 01655 uint32_t vl53l1_tuningparm_zone_cal_dss_timeout_us; 01656 uint16_t vl53l1_tuningparm_zone_cal_phasecal_num_samples; 01657 uint32_t vl53l1_tuningparm_zone_cal_range_timeout_us; 01658 uint16_t vl53l1_tuningparm_zone_cal_zone_num_samples; 01659 uint8_t vl53l1_tuningparm_spadmap_vcsel_period; 01660 uint8_t vl53l1_tuningparm_spadmap_vcsel_start; 01661 uint16_t vl53l1_tuningparm_spadmap_rate_limit_mcps; 01662 uint16_t vl53l1_tuningparm_lite_dss_config_target_total_rate_mcps; 01663 uint16_t vl53l1_tuningparm_ranging_dss_config_target_total_rate_mcps; 01664 uint16_t vl53l1_tuningparm_mz_dss_config_target_total_rate_mcps; 01665 uint16_t vl53l1_tuningparm_timed_dss_config_target_total_rate_mcps; 01666 uint32_t vl53l1_tuningparm_lite_phasecal_config_timeout_us; 01667 uint32_t vl53l1_tuningparm_ranging_long_phasecal_config_timeout_us; 01668 uint32_t vl53l1_tuningparm_ranging_med_phasecal_config_timeout_us; 01669 uint32_t vl53l1_tuningparm_ranging_short_phasecal_config_timeout_us; 01670 uint32_t vl53l1_tuningparm_mz_long_phasecal_config_timeout_us; 01671 uint32_t vl53l1_tuningparm_mz_med_phasecal_config_timeout_us; 01672 uint32_t vl53l1_tuningparm_mz_short_phasecal_config_timeout_us; 01673 uint32_t vl53l1_tuningparm_timed_phasecal_config_timeout_us; 01674 uint32_t vl53l1_tuningparm_lite_mm_config_timeout_us; 01675 uint32_t vl53l1_tuningparm_ranging_mm_config_timeout_us; 01676 uint32_t vl53l1_tuningparm_mz_mm_config_timeout_us; 01677 uint32_t vl53l1_tuningparm_timed_mm_config_timeout_us; 01678 uint32_t vl53l1_tuningparm_lite_range_config_timeout_us; 01679 uint32_t vl53l1_tuningparm_ranging_range_config_timeout_us; 01680 uint32_t vl53l1_tuningparm_mz_range_config_timeout_us; 01681 uint32_t vl53l1_tuningparm_timed_range_config_timeout_us; 01682 uint16_t vl53l1_tuningparm_dynxtalk_smudge_margin; 01683 uint32_t vl53l1_tuningparm_dynxtalk_noise_margin; 01684 uint32_t vl53l1_tuningparm_dynxtalk_xtalk_offset_limit; 01685 uint8_t vl53l1_tuningparm_dynxtalk_xtalk_offset_limit_hi; 01686 uint32_t vl53l1_tuningparm_dynxtalk_sample_limit; 01687 uint32_t vl53l1_tuningparm_dynxtalk_single_xtalk_delta; 01688 uint32_t vl53l1_tuningparm_dynxtalk_averaged_xtalk_delta; 01689 uint32_t vl53l1_tuningparm_dynxtalk_clip_limit; 01690 uint8_t vl53l1_tuningparm_dynxtalk_scaler_calc_method; 01691 int16_t vl53l1_tuningparm_dynxtalk_xgradient_scaler; 01692 int16_t vl53l1_tuningparm_dynxtalk_ygradient_scaler; 01693 uint8_t vl53l1_tuningparm_dynxtalk_user_scaler_set; 01694 uint8_t vl53l1_tuningparm_dynxtalk_smudge_cor_single_apply; 01695 uint32_t vl53l1_tuningparm_dynxtalk_xtalk_amb_threshold; 01696 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_amb_threshold_kcps; 01697 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_sample_limit; 01698 uint32_t vl53l1_tuningparm_dynxtalk_nodetect_xtalk_offset_kcps; 01699 uint16_t vl53l1_tuningparm_dynxtalk_nodetect_min_range_mm; 01700 uint8_t vl53l1_tuningparm_lowpowerauto_vhv_loop_bound; 01701 uint32_t vl53l1_tuningparm_lowpowerauto_mm_config_timeout_us; 01702 uint32_t vl53l1_tuningparm_lowpowerauto_range_config_timeout_us; 01703 uint16_t vl53l1_tuningparm_very_short_dss_rate_mcps; 01704 uint32_t vl53l1_tuningparm_phasecal_patch_power; 01705 } VL53L1_tuning_parameters_t; 01706 01707 01708 01709 01710 01711 typedef struct { 01712 01713 uint16_t target_reflectance_for_dmax[VL53L1_MAX_AMBIENT_DMAX_VALUES]; 01714 01715 } VL53L1_dmax_reflectance_array_t; 01716 01717 01718 01719 01720 typedef struct { 01721 01722 uint8_t spad_type; 01723 01724 uint16_t VL53L1_p_023; 01725 01726 uint16_t rate_data[VL53L1_NO_OF_SPAD_ENABLES]; 01727 01728 uint16_t no_of_values; 01729 01730 uint8_t fractional_bits; 01731 01732 uint8_t error_status; 01733 01734 01735 } VL53L1_spad_rate_data_t; 01736 01737 01738 01739 01740 01741 01742 typedef struct { 01743 01744 VL53L1_DevicePresetModes preset_mode; 01745 01746 VL53L1_DeviceZonePreset zone_preset; 01747 01748 VL53L1_DeviceMeasurementModes measurement_mode; 01749 01750 VL53L1_OffsetCalibrationMode offset_calibration_mode; 01751 01752 VL53L1_OffsetCorrectionMode offset_correction_mode; 01753 01754 VL53L1_DeviceDmaxMode dmax_mode; 01755 01756 01757 uint32_t phasecal_config_timeout_us; 01758 01759 uint32_t mm_config_timeout_us; 01760 01761 uint32_t range_config_timeout_us; 01762 01763 uint32_t inter_measurement_period_ms; 01764 01765 uint16_t dss_config__target_total_rate_mcps; 01766 01767 01768 VL53L1_histogram_bin_data_t VL53L1_p_010; 01769 01770 01771 } VL53L1_additional_data_t; 01772 01773 01774 01775 01776 01777 01778 01779 01780 #define SUPPRESS_UNUSED_WARNING(x) \ 01781 ((void) (x)) 01782 01783 01784 #define IGNORE_STATUS(__FUNCTION_ID__, __ERROR_STATUS_CHECK__, __STATUS__) \ 01785 do { \ 01786 DISABLE_WARNINGS(); \ 01787 if (__FUNCTION_ID__) { \ 01788 if (__STATUS__ == __ERROR_STATUS_CHECK__) { \ 01789 __STATUS__ = VL53L1_ERROR_NONE; \ 01790 WARN_OVERRIDE_STATUS(__FUNCTION_ID__); \ 01791 } \ 01792 } \ 01793 ENABLE_WARNINGS(); \ 01794 } \ 01795 while (0) 01796 01797 #define VL53L1_COPYSTRING(str, ...) \ 01798 (strncpy(str, ##__VA_ARGS__, VL53L1_MAX_STRING_LENGTH-1)) 01799 01800 #ifdef __cplusplus 01801 } 01802 #endif 01803 01804 #endif 01805 01806 01807 01808
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