for frequency correction testing
Dependencies: FreescaleIAP SimpleDMA mbed-rtos mbed
Fork of CDMS_CODE by
adf.h
00001 //without reset feature , with state checks. 00002 InterruptIn IRQ(ADF_IRQ); 00003 //Ticker ticker; 00004 00005 bool loop_on; 00006 bool ADF_off; 00007 bool buffer_state; 00008 bool finish_write_data; 00009 uint8_t signal = 0x00; 00010 unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,/*PA Level Byte*/0x57/*PA Parameters*/,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x20,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xE0,0x00,0x10,0x04,0x00,0x00,0x00,0x00,0x00}; 00011 bool data_irq_err=0; 00012 bool data_err= false; 00013 unsigned char temp_byte=0x00; 00014 unsigned char data_err1[112]; 00015 unsigned char data_err_cnt=0; 00016 unsigned int byte_count =0; 00017 #define DATA_ERR_THRS 20 00018 bool rolling_buffer_settings_error=true; 00019 bool bbram_write_success=true; 00020 int bbram_err_cnt=0; 00021 int rbp_err_cnt=0; 00022 bool reset_flag=false; 00023 #define RBP_THRS 4 00024 bool quit_configuration=false; 00025 bool power_reset_flag=false; 00026 unsigned int power_reset_count=0; 00027 bool Configuration_done=false; 00028 #define HW_THRS 2 00029 00030 //int initialise_card(); 00031 //int disk_initialize(); 00032 //------------------------------------------------------------------------ 00033 // state checking functions 00034 //bool assrt_phy_off( int, int, int); 00035 //bool assrt_phy_on( int,int,int); 00036 //bool assrt_phy_tx(int,int,int); 00037 00038 #define TRANSMIT_LEN_1 0xFF 00039 #define TRANSMIT_LEN_2 0xFF 00040 /***/ 00041 Timer T; 00042 00043 #define START_ADDRESS 0x020; 00044 #define MISO_PIN PTE3 00045 /**************Defining Counter Limits**************/ 00046 #define THRS 20 00047 #define STATE_ERR_THRS 20 00048 #define PHY_OFF_EXEC_TIME 300 00049 #define PHY_ON_EXEC_TIME 300 00050 #define PHY_TX_EXEC_TIME 600 00051 /******DEFINING COMMANDS*********/ 00052 #define CMD_HW_RESET 0xC8 00053 #define CMD_PHY_ON 0xB1 00054 #define CMD_PHY_OFF 0xB0 00055 #define CMD_PHY_TX 0xB5 00056 #define CMD_CONFIG_DEV 0xBB 00057 /**STATES**/ 00058 //======================= 00059 #define PHY_OFF 0xB1 00060 #define PHY_ON 0xB2 00061 #define PHY_TX 0xB4 00062 #define BUSY 0x00 00063 //=================================================== 00064 00065 unsigned int Adf_data_counter=0; 00066 unsigned char status =0; 00067 unsigned int cmd_err_cnt=0; 00068 unsigned int data_length; 00069 unsigned int state_err_cnt=0; 00070 unsigned int miso_err_cnt=0; 00071 unsigned int hw_reset_err_cnt=0; 00072 unsigned int counter =0; 00073 bool temp_return = 0; 00074 bool bcn_flag=0; 00075 bool bbram_flag=0; 00076 00077 bool stop_transmission=false; 00078 00079 #define reset_flags {\ 00080 finish_write_data = false;\ 00081 buffer_state = true;\ 00082 last_buffer = false;\ 00083 loop_on = true;\ 00084 ADF_off = false;\ 00085 buffer_state = true;\ 00086 loop_on = true;\ 00087 ADF_off = false;\ 00088 /*sent_tmfrom_SDcard = false;*/\ 00089 Adf_data_counter=0;\ 00090 status =0;\ 00091 cmd_err_cnt=0;\ 00092 data_length;\ 00093 state_err_cnt=0;\ 00094 miso_err_cnt=0;\ 00095 hw_reset_err_cnt=0;\ 00096 counter =0;\ 00097 bcn_flag=0;\ 00098 bbram_flag=0;\ 00099 stop_transmission=false;\ 00100 } 00101 00102 00103 int err_arr[64]; 00104 bool bbram_err=false; 00105 int err_idx=-1; 00106 int err[64]; 00107 #define bbram_check gCS_ADF=0;\ 00108 for(int i=0;i<64;i++){\ 00109 err_arr[i]=0;\ 00110 }\ 00111 for(int i=0;i<64;i++){\ 00112 err[i]=0;\ 00113 }\ 00114 bbram_err=false;\ 00115 gCS_ADF=0;\ 00116 spi.write(0x39);\ 00117 spi.write(0x00);\ 00118 spi.write(0xFF);\ 00119 for(int i=0;i<64;i++){\ 00120 err_arr[i]=spi.write(0xFF);\ 00121 if(err_arr[i]!=bbram_buffer[i+2]){\ 00122 err[i]=1;\ 00123 bbram_err=true;\ 00124 }\ 00125 }\ 00126 gCS_ADF=1;\ 00127 if(!bbram_err)\ 00128 gPC.printf("BBRAM verified \r\n");\ 00129 else\ 00130 gPC.printf("BBRAM error \r\n");\ 00131 00132 00133 bool tx_loop=1; 00134 00135 #define PRNT_ONCE {\ 00136 gPC.printf("%d %d lol_ what?\r\n",segment_len,EOS_len);\ 00137 } 00138 00139 #define bbram_write {\ 00140 gCS_ADF=0;\ 00141 spi.write(0xB0);\ 00142 wait_us(300);\ 00143 gCS_ADF=1;\ 00144 gCS_ADF=0;\ 00145 for(int i=0;i<66;i++){\ 00146 spi.write(bbram_buffer[i]);\ 00147 }\ 00148 gCS_ADF=1;\ 00149 } 00150 //------------------------------------------------------------------------ 00151 // state checking functions 00152 //bool assrt_phy_off( int, int, int); 00153 //bool assrt_phy_on( int,int,int); 00154 //bool assrt_phy_tx(int,int,int); 00155 00156 #define check_status {\ 00157 unsigned char stat=0;\ 00158 gCS_ADF=0;\ 00159 spi.write(0xFF);\ 00160 stat = spi.write(0xFF);\ 00161 gCS_ADF=1;\ 00162 status = stat;\ 00163 } 00164 /***********************/ 00165 /**********Restart ADF**************/ 00166 00167 /**************************/ 00168 00169 /*CMD_VAR*/ 00170 bool cmd_bit=true; 00171 bool cmd_err_flag=false; 00172 unsigned char command = 0x00; 00173 void CMD(uint8_t command) { 00174 cmd_err_cnt=0; 00175 cmd_err_flag=false; 00176 while(cmd_err_cnt<3) { 00177 check_status; 00178 cmd_bit=status&0x20; 00179 if(cmd_bit) { 00180 gCS_ADF=0; 00181 spi.write(command); 00182 gCS_ADF=1; 00183 break; 00184 } else { 00185 wait_us(5); 00186 cmd_err_cnt++; 00187 } 00188 } 00189 if(cmd_err_cnt==3) { 00190 cmd_err_flag=true; 00191 } 00192 } 00193 00194 // all three arguments are int 00195 #define assrt_phy_off {\ 00196 int state_err_cnt = 0;\ 00197 CMD(CMD_PHY_OFF);\ 00198 if(cmd_err_flag){\ 00199 temp_return=1;\ 00200 }\ 00201 else{\ 00202 for(int i = 0 ; i < 40 ;i++){\ 00203 CMD(CMD_PHY_OFF);\ 00204 check_status;\ 00205 if(status == PHY_OFF){\ 00206 temp_return = 0;\ 00207 break;\ 00208 }\ 00209 else if(state_err_cnt>THRS){\ 00210 temp_return = 1;\ 00211 break;\ 00212 }\ 00213 else {\ 00214 wait_ms(1);\ 00215 }\ 00216 }\ 00217 }\ 00218 } 00219 00220 00221 bool hardware_reset(int bcn_call) 00222 { 00223 for(int i= 0; i < 2 ; i++) { 00224 gCS_ADF=0; 00225 spi.write(CMD_HW_RESET); 00226 gCS_ADF=1; 00227 wait_ms(2);// Typically 1 ms 00228 int count=0; 00229 temp_return = 0; 00230 while(count<10 && miso_err_cnt<10) { 00231 if(MISO_PIN) { 00232 // assrt_phy_off; 00233 /*asseert_phyoff Starts**/ 00234 {\ 00235 int state_err_cnt = 0;\ 00236 CMD(CMD_PHY_OFF);\ 00237 if(cmd_err_flag){\ 00238 temp_return=1;\ 00239 }\ 00240 else{\ 00241 for(int i = 0 ; i < 40 ;i++){\ 00242 CMD(CMD_PHY_OFF);\ 00243 check_status;\ 00244 if(status == PHY_OFF){\ 00245 temp_return = 0;\ 00246 break;\ 00247 }\ 00248 else if(state_err_cnt>THRS){\ 00249 temp_return = 1;\ 00250 break;\ 00251 }\ 00252 else {\ 00253 wait_ms(1);\ 00254 }\ 00255 }\ 00256 }\ 00257 }\ 00258 /*Assert_phy_off_ends*/ 00259 00260 00261 00262 00263 00264 if(!temp_return){ 00265 return 0; 00266 } 00267 count++; 00268 } else { 00269 wait_us(50); 00270 miso_err_cnt++; 00271 } 00272 } 00273 } 00274 return 1; 00275 } 00276 //for reseting the transmission call assert function after b5 and b1. after b1 assert_phi_on and after b5 assert_phi_tx. 00277 //---------------------------------------------------------------------------- 00278 unsigned char temp; 00279 bool reg_err; 00280 int reg_err_cnt; 00281 #define REG_ERR_THRS 5 00282 #define reg_check(addr1,addr2,reg_val){\ 00283 gCS_ADF=0;\ 00284 reg_err=false;\ 00285 spi.write(addr1);\ 00286 spi.write(addr2);\ 00287 spi.write(0xFF);\ 00288 temp = spi.write(0xFF);\ 00289 if(temp==reg_val)\ 00290 reg_err = false;\ 00291 else\ 00292 reg_err=true;\ 00293 gCS_ADF=1;\ 00294 } 00295 00296 #define initiate {\ 00297 gCS_ADF=0;\ 00298 spi.write(0xFF);\ 00299 spi.write(0xFF);\ 00300 gCS_ADF=1;\ 00301 reg_err=true;\ 00302 for(reg_err_cnt=0;reg_err_cnt<REG_ERR_THRS && reg_err;reg_err_cnt++){\ 00303 gCS_ADF=0;\ 00304 spi.write(0x08);\ 00305 spi.write(0x14);\ 00306 spi.write(TRANSMIT_LEN_1);\ 00307 gCS_ADF=1;\ 00308 reg_check(0x28,0x14,TRANSMIT_LEN_1);\ 00309 }\ 00310 if(reg_err)\ 00311 gPC.printf("Reg_err_ignored %x \r\n",(int)temp);\ 00312 else\ 00313 gPC.printf("reg written successful %x \r\n",(int)temp);\ 00314 reg_err=true;\ 00315 for(reg_err_cnt=0;reg_err_cnt<REG_ERR_THRS && reg_err;reg_err_cnt++){\ 00316 gCS_ADF=0;\ 00317 spi.write(0x08);\ 00318 spi.write(0x15);\ 00319 spi.write(TRANSMIT_LEN_2);\ 00320 gCS_ADF=1;\ 00321 reg_check(0x28,0x15,TRANSMIT_LEN_2);\ 00322 }\ 00323 if(reg_err)\ 00324 gPC.printf("Reg_err_ignored %x \r\n",(int)temp);\ 00325 else\ 00326 gPC.printf("reg written successful %x \r\n",(int)temp);\ 00327 } 00328 00329 #define write_data {\ 00330 counter++;\ 00331 if(counter==584){\ 00332 finish_write_data=true;\ 00333 restart_adf_flag=true;\ 00334 counter=0;\ 00335 }\ 00336 gCS_ADF=0;\ 00337 spi.write(0x0B);\ 00338 spi.write(0x36);\ 00339 spi.write(0xFF);\ 00340 gCS_ADF=1;\ 00341 data_err_cnt=0;\ 00342 data_err=true;\ 00343 while(data_err && (data_err_cnt<DATA_ERR_THRS)){\ 00344 gCS_ADF=0;\ 00345 if(buffer_state){\ 00346 spi.write(0x18);\ 00347 spi.write(0x20);\ 00348 for(unsigned char i=0; i<112;i++){\ 00349 spi.write(buffer_112[i]);\ 00350 /*gPC.printf("0x%X,",spi.write(buffer_112[i]));*/\ 00351 }\ 00352 }\ 00353 else{\ 00354 spi.write(0x18);\ 00355 spi.write(0x90);\ 00356 for(unsigned char i=0; i<112;i++){\ 00357 spi.write(buffer_112[i]);\ 00358 /*gPC.printf("0x%X,",spi.write(buffer_112[i]));*/\ 00359 }\ 00360 }\ 00361 gCS_ADF=1;\ 00362 wait_us(5);\ 00363 data_err=false;\ 00364 gCS_ADF=0;\ 00365 spi.write(0x38);\ 00366 if(buffer_state){\ 00367 spi.write(0x20);\ 00368 }\ 00369 else{\ 00370 spi.write(0x90);\ 00371 }\ 00372 spi.write(0xFF);\ 00373 for(unsigned char i=0; i<112;i++){\ 00374 temp_byte=spi.write(0xFF);\ 00375 if(buffer_112[i]!=temp_byte){\ 00376 data_err1[i]=1;\ 00377 data_err=true;\ 00378 }\ 00379 }\ 00380 gCS_ADF=1;\ 00381 /*SPI_mutex.unlock();*/\ 00382 if(data_err==false){\ 00383 buffer_state = !buffer_state;\ 00384 }\ 00385 data_err_cnt++;\ 00386 if(last_buffer){\ 00387 finish_write_data = true;\ 00388 /*gPC.puts("adf_off\r\n");*/\ 00389 }\ 00390 }\ 00391 } 00392 00393 #define check {\ 00394 check_status;\ 00395 /*gPC.printf("I 0x%X\r\n",(int)status);*/\ 00396 if(IRQ){\ 00397 /*gPC.printf("det\r\n");*/\ 00398 if(!ADF_off) {\ 00399 if(finish_write_data || restart_adf_flag) {\ 00400 write_data;\ 00401 ADF_off=true;\ 00402 } else {\ 00403 write_data;\ 00404 if(sent_tmfrom_SDcard)\ 00405 send_tm_from_SD_card_fun();\ 00406 else snd_tm.transmit_data(buffer_112,&last_buffer);\ 00407 }\ 00408 } else {\ 00409 wait_ms(20);\ 00410 gCS_ADF=0;\ 00411 spi.write(0xB1);\ 00412 gCS_ADF=1;\ 00413 gPC.puts("transmission done\r\n");\ 00414 loop_on=false;\ 00415 if(restart_adf_flag)\ 00416 {\ 00417 restart_adf_flag=false;\ 00418 ADF_off=false;\ 00419 send_data;\ 00420 loop_on=true;\ 00421 CMD(CMD_PHY_TX);\ 00422 wait_us(2000);\ 00423 }\ 00424 /*Stop_the_Timer*/\ 00425 }\ 00426 }\ 00427 /*else{*/\ 00428 /*if(T.read_us()>98000){*/\ 00429 /*data_irq_err=true;*/\ 00430 /*CMD(CMD_PHY_ON);*/\ 00431 /*gPC.printf("Data_error_detected");*/\ 00432 /*}*/\ 00433 /*}*/\ 00434 } 00435 00436 #define send_data {\ 00437 gCS_ADF=0;\ 00438 spi.write(0xBB);\ 00439 gCS_ADF=1;\ 00440 gCS_ADF=0;\ 00441 spi.write(0xFF);\ 00442 spi.write(0xFF);\ 00443 gCS_ADF=1;\ 00444 if(sent_tmfrom_SDcard){\ 00445 send_tm_from_SD_card_fun();\ 00446 }else{\ 00447 snd_tm.transmit_data(buffer_112,&last_buffer);\ 00448 }\ 00449 write_data;\ 00450 if(sent_tmfrom_SDcard){\ 00451 send_tm_from_SD_card_fun();\ 00452 }else{\ 00453 snd_tm.transmit_data(buffer_112,&last_buffer);\ 00454 }\ 00455 write_data;\ 00456 if(sent_tmfrom_SDcard){\ 00457 send_tm_from_SD_card_fun();\ 00458 }else{\ 00459 snd_tm.transmit_data(buffer_112,&last_buffer);\ 00460 }\ 00461 gCS_ADF=0;\ 00462 spi.write(0xB1);\ 00463 gCS_ADF=1;\ 00464 wait_us(300);\ 00465 gCS_ADF=0;\ 00466 spi.write(0xFF);\ 00467 spi.write(0xFF);\ 00468 gCS_ADF=1;\ 00469 gCS_ADF=0;\ 00470 spi.write(0xB5);\ 00471 gCS_ADF=1;\ 00472 wait_us(300);\ 00473 gCS_ADF=0;\ 00474 spi.write(0xFF);\ 00475 spi.write(0xFF);\ 00476 gCS_ADF=1;\ 00477 } 00478 00479 #define initial_adf_check {\ 00480 bool Configuration_Done=false;\ 00481 quit_configuration=false;\ 00482 bool reset_flag1 = 0;\ 00483 bool flag = false;\ 00484 while((hw_reset_err_cnt<HW_THRS)&&(quit_configuration==false)){\ 00485 while((bbram_err_cnt<2)&&(quit_configuration==false)){\ 00486 /*assrt_phy_off;*/\ 00487 /*Assrt_phy_off Begin*/\ 00488 {\ 00489 int state_err_cnt = 0;\ 00490 CMD(CMD_PHY_OFF);\ 00491 if(cmd_err_flag){\ 00492 temp_return=1;\ 00493 }\ 00494 else{\ 00495 for(int i = 0 ; i < 40 ;i++){\ 00496 CMD(CMD_PHY_OFF);\ 00497 check_status;\ 00498 if(status == PHY_OFF){\ 00499 temp_return = 0;\ 00500 break;\ 00501 }\ 00502 else if(state_err_cnt>THRS){\ 00503 temp_return = 1;\ 00504 break;\ 00505 }\ 00506 else {\ 00507 wait_ms(1);\ 00508 }\ 00509 }\ 00510 }\ 00511 }\ 00512 /*Assrt_phy_off end*/\ 00513 reset_flag1=temp_return;\ 00514 if(!reset_flag1){\ 00515 bbram_write;\ 00516 while((rbp_err_cnt<RBP_THRS)&&(quit_configuration==false)){\ 00517 bbram_check;\ 00518 if(bbram_err==0){\ 00519 bbram_write_success=true;\ 00520 bbram_err_cnt=0;\ 00521 initiate;\ 00522 if(reg_err){\ 00523 rbp_err_cnt++;\ 00524 }\ 00525 else{\ 00526 rbp_err_cnt=0;\ 00527 gPC.printf("NO Reg err\r\n");\ 00528 CMD(CMD_CONFIG_DEV);\ 00529 if(cmd_err_flag){\ 00530 reset_flag=1;\ 00531 gPC.printf("CMD ERR\r\n");\ 00532 }\ 00533 else{\ 00534 reset_flag=0;\ 00535 gPC.printf("NO CMD ERR CONFIG_DONE\r\n");\ 00536 quit_configuration=true;\ 00537 }\ 00538 }\ 00539 }\ 00540 else{\ 00541 bbram_write_success=false;\ 00542 bbram_err_cnt++;\ 00543 break;\ 00544 }\ 00545 }\ 00546 }\ 00547 else{\ 00548 break;\ 00549 }\ 00550 }\ 00551 if(reset_flag1){\ 00552 hardware_reset(0);\ 00553 hw_reset_err_cnt++;\ 00554 gPC.puts("Resetting hardware\r\n");\ 00555 }\ 00556 }\ 00557 if(hw_reset_err_cnt==HW_THRS){\ 00558 power_reset_flag=1;\ 00559 power_reset_count++;\ 00560 }\ 00561 else{\ 00562 Configuration_Done=true;\ 00563 gPC.printf("Configuration_Done\n");\ 00564 }\ 00565 } 00566 00567 #define configure_adf {\ 00568 reset_flags;\ 00569 initial_adf_check;\ 00570 gPC.puts("Config_part done\r\n");\ 00571 } 00572 00573 #define transmit_adf {\ 00574 restart_adf_flag=false;\ 00575 bool tx_err=false;\ 00576 configure_adf;\ 00577 send_data;\ 00578 CMD(CMD_PHY_TX);\ 00579 /*PA MCR level*/;\ 00580 gCS_ADF=0;\ 00581 spi.write(0x1B);\ 00582 spi.write(0x07);\ 00583 spi.write(0x35);\ 00584 gCS_ADF=1;\ 00585 wait_us(2000);\ 00586 while(loop_on){\ 00587 wait_us(20);\ 00588 check;\ 00589 if(data_irq_err||tx_err){\ 00590 break;\ 00591 }\ 00592 }\ 00593 /*gPC.puts("after while loop\r\n");*/\ 00594 }
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