Sylvain Savon
BSP library for DISCO-STM32F746NG board. Added support for on-board QSPI Flash memory MICRO N25Q128A. Ported from library BSP_DISCO_L476VG.
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stm32746g_discovery_sdram.c@0:c9112f0c67e3, 2015-09-28 (annotated)
- Committer:
- bcostm
- Date:
- Mon Sep 28 13:34:16 2015 +0000
- Revision:
- 0:c9112f0c67e3
Initial version.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bcostm | 0:c9112f0c67e3 | 1 | /** |
| bcostm | 0:c9112f0c67e3 | 2 | ****************************************************************************** |
| bcostm | 0:c9112f0c67e3 | 3 | * @file stm32746g_discovery_sdram.c |
| bcostm | 0:c9112f0c67e3 | 4 | * @author MCD Application Team |
| bcostm | 0:c9112f0c67e3 | 5 | * @version V1.0.0 |
| bcostm | 0:c9112f0c67e3 | 6 | * @date 25-June-2015 |
| bcostm | 0:c9112f0c67e3 | 7 | * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory |
| bcostm | 0:c9112f0c67e3 | 8 | * device mounted on STM32746G-Discovery board. |
| bcostm | 0:c9112f0c67e3 | 9 | @verbatim |
| bcostm | 0:c9112f0c67e3 | 10 | 1. How To use this driver: |
| bcostm | 0:c9112f0c67e3 | 11 | -------------------------- |
| bcostm | 0:c9112f0c67e3 | 12 | - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted |
| bcostm | 0:c9112f0c67e3 | 13 | on STM32746G-Discovery board. |
| bcostm | 0:c9112f0c67e3 | 14 | - This driver does not need a specific component driver for the SDRAM device |
| bcostm | 0:c9112f0c67e3 | 15 | to be included with. |
| bcostm | 0:c9112f0c67e3 | 16 | |
| bcostm | 0:c9112f0c67e3 | 17 | 2. Driver description: |
| bcostm | 0:c9112f0c67e3 | 18 | --------------------- |
| bcostm | 0:c9112f0c67e3 | 19 | + Initialization steps: |
| bcostm | 0:c9112f0c67e3 | 20 | o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This |
| bcostm | 0:c9112f0c67e3 | 21 | function includes the MSP layer hardware resources initialization and the |
| bcostm | 0:c9112f0c67e3 | 22 | FMC controller configuration to interface with the external SDRAM memory. |
| bcostm | 0:c9112f0c67e3 | 23 | o It contains the SDRAM initialization sequence to program the SDRAM external |
| bcostm | 0:c9112f0c67e3 | 24 | device using the function BSP_SDRAM_Initialization_sequence(). Note that this |
| bcostm | 0:c9112f0c67e3 | 25 | sequence is standard for all SDRAM devices, but can include some differences |
| bcostm | 0:c9112f0c67e3 | 26 | from a device to another. If it is the case, the right sequence should be |
| bcostm | 0:c9112f0c67e3 | 27 | implemented separately. |
| bcostm | 0:c9112f0c67e3 | 28 | |
| bcostm | 0:c9112f0c67e3 | 29 | + SDRAM read/write operations |
| bcostm | 0:c9112f0c67e3 | 30 | o SDRAM external memory can be accessed with read/write operations once it is |
| bcostm | 0:c9112f0c67e3 | 31 | initialized. |
| bcostm | 0:c9112f0c67e3 | 32 | Read/write operation can be performed with AHB access using the functions |
| bcostm | 0:c9112f0c67e3 | 33 | BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions |
| bcostm | 0:c9112f0c67e3 | 34 | BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). |
| bcostm | 0:c9112f0c67e3 | 35 | o The AHB access is performed with 32-bit width transaction, the DMA transfer |
| bcostm | 0:c9112f0c67e3 | 36 | configuration is fixed at single (no burst) word transfer (see the |
| bcostm | 0:c9112f0c67e3 | 37 | SDRAM_MspInit() static function). |
| bcostm | 0:c9112f0c67e3 | 38 | o User can implement his own functions for read/write access with his desired |
| bcostm | 0:c9112f0c67e3 | 39 | configurations. |
| bcostm | 0:c9112f0c67e3 | 40 | o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() |
| bcostm | 0:c9112f0c67e3 | 41 | is called in IRQ handler file, to serve the generated interrupt once the DMA |
| bcostm | 0:c9112f0c67e3 | 42 | transfer is complete. |
| bcostm | 0:c9112f0c67e3 | 43 | o You can send a command to the SDRAM device in runtime using the function |
| bcostm | 0:c9112f0c67e3 | 44 | BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between |
| bcostm | 0:c9112f0c67e3 | 45 | the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. |
| bcostm | 0:c9112f0c67e3 | 46 | |
| bcostm | 0:c9112f0c67e3 | 47 | @endverbatim |
| bcostm | 0:c9112f0c67e3 | 48 | ****************************************************************************** |
| bcostm | 0:c9112f0c67e3 | 49 | * @attention |
| bcostm | 0:c9112f0c67e3 | 50 | * |
| bcostm | 0:c9112f0c67e3 | 51 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| bcostm | 0:c9112f0c67e3 | 52 | * |
| bcostm | 0:c9112f0c67e3 | 53 | * Redistribution and use in source and binary forms, with or without modification, |
| bcostm | 0:c9112f0c67e3 | 54 | * are permitted provided that the following conditions are met: |
| bcostm | 0:c9112f0c67e3 | 55 | * 1. Redistributions of source code must retain the above copyright notice, |
| bcostm | 0:c9112f0c67e3 | 56 | * this list of conditions and the following disclaimer. |
| bcostm | 0:c9112f0c67e3 | 57 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bcostm | 0:c9112f0c67e3 | 58 | * this list of conditions and the following disclaimer in the documentation |
| bcostm | 0:c9112f0c67e3 | 59 | * and/or other materials provided with the distribution. |
| bcostm | 0:c9112f0c67e3 | 60 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bcostm | 0:c9112f0c67e3 | 61 | * may be used to endorse or promote products derived from this software |
| bcostm | 0:c9112f0c67e3 | 62 | * without specific prior written permission. |
| bcostm | 0:c9112f0c67e3 | 63 | * |
| bcostm | 0:c9112f0c67e3 | 64 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bcostm | 0:c9112f0c67e3 | 65 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bcostm | 0:c9112f0c67e3 | 66 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bcostm | 0:c9112f0c67e3 | 67 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bcostm | 0:c9112f0c67e3 | 68 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bcostm | 0:c9112f0c67e3 | 69 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bcostm | 0:c9112f0c67e3 | 70 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bcostm | 0:c9112f0c67e3 | 71 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bcostm | 0:c9112f0c67e3 | 72 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bcostm | 0:c9112f0c67e3 | 73 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bcostm | 0:c9112f0c67e3 | 74 | * |
| bcostm | 0:c9112f0c67e3 | 75 | ****************************************************************************** |
| bcostm | 0:c9112f0c67e3 | 76 | */ |
| bcostm | 0:c9112f0c67e3 | 77 | |
| bcostm | 0:c9112f0c67e3 | 78 | /* Includes ------------------------------------------------------------------*/ |
| bcostm | 0:c9112f0c67e3 | 79 | #include "stm32746g_discovery_sdram.h" |
| bcostm | 0:c9112f0c67e3 | 80 | |
| bcostm | 0:c9112f0c67e3 | 81 | // mbed function to replace HAL_Delay function |
| bcostm | 0:c9112f0c67e3 | 82 | void wait_ms(int ms); |
| bcostm | 0:c9112f0c67e3 | 83 | |
| bcostm | 0:c9112f0c67e3 | 84 | /** @addtogroup BSP |
| bcostm | 0:c9112f0c67e3 | 85 | * @{ |
| bcostm | 0:c9112f0c67e3 | 86 | */ |
| bcostm | 0:c9112f0c67e3 | 87 | |
| bcostm | 0:c9112f0c67e3 | 88 | /** @addtogroup STM32746G_DISCOVERY |
| bcostm | 0:c9112f0c67e3 | 89 | * @{ |
| bcostm | 0:c9112f0c67e3 | 90 | */ |
| bcostm | 0:c9112f0c67e3 | 91 | |
| bcostm | 0:c9112f0c67e3 | 92 | /** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM |
| bcostm | 0:c9112f0c67e3 | 93 | * @{ |
| bcostm | 0:c9112f0c67e3 | 94 | */ |
| bcostm | 0:c9112f0c67e3 | 95 | |
| bcostm | 0:c9112f0c67e3 | 96 | /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions |
| bcostm | 0:c9112f0c67e3 | 97 | * @{ |
| bcostm | 0:c9112f0c67e3 | 98 | */ |
| bcostm | 0:c9112f0c67e3 | 99 | /** |
| bcostm | 0:c9112f0c67e3 | 100 | * @} |
| bcostm | 0:c9112f0c67e3 | 101 | */ |
| bcostm | 0:c9112f0c67e3 | 102 | |
| bcostm | 0:c9112f0c67e3 | 103 | /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines |
| bcostm | 0:c9112f0c67e3 | 104 | * @{ |
| bcostm | 0:c9112f0c67e3 | 105 | */ |
| bcostm | 0:c9112f0c67e3 | 106 | /** |
| bcostm | 0:c9112f0c67e3 | 107 | * @} |
| bcostm | 0:c9112f0c67e3 | 108 | */ |
| bcostm | 0:c9112f0c67e3 | 109 | |
| bcostm | 0:c9112f0c67e3 | 110 | /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros |
| bcostm | 0:c9112f0c67e3 | 111 | * @{ |
| bcostm | 0:c9112f0c67e3 | 112 | */ |
| bcostm | 0:c9112f0c67e3 | 113 | /** |
| bcostm | 0:c9112f0c67e3 | 114 | * @} |
| bcostm | 0:c9112f0c67e3 | 115 | */ |
| bcostm | 0:c9112f0c67e3 | 116 | |
| bcostm | 0:c9112f0c67e3 | 117 | /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables |
| bcostm | 0:c9112f0c67e3 | 118 | * @{ |
| bcostm | 0:c9112f0c67e3 | 119 | */ |
| bcostm | 0:c9112f0c67e3 | 120 | static SDRAM_HandleTypeDef sdramHandle; |
| bcostm | 0:c9112f0c67e3 | 121 | static FMC_SDRAM_TimingTypeDef Timing; |
| bcostm | 0:c9112f0c67e3 | 122 | static FMC_SDRAM_CommandTypeDef Command; |
| bcostm | 0:c9112f0c67e3 | 123 | /** |
| bcostm | 0:c9112f0c67e3 | 124 | * @} |
| bcostm | 0:c9112f0c67e3 | 125 | */ |
| bcostm | 0:c9112f0c67e3 | 126 | |
| bcostm | 0:c9112f0c67e3 | 127 | /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes |
| bcostm | 0:c9112f0c67e3 | 128 | * @{ |
| bcostm | 0:c9112f0c67e3 | 129 | */ |
| bcostm | 0:c9112f0c67e3 | 130 | /** |
| bcostm | 0:c9112f0c67e3 | 131 | * @} |
| bcostm | 0:c9112f0c67e3 | 132 | */ |
| bcostm | 0:c9112f0c67e3 | 133 | |
| bcostm | 0:c9112f0c67e3 | 134 | /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions |
| bcostm | 0:c9112f0c67e3 | 135 | * @{ |
| bcostm | 0:c9112f0c67e3 | 136 | */ |
| bcostm | 0:c9112f0c67e3 | 137 | |
| bcostm | 0:c9112f0c67e3 | 138 | /** |
| bcostm | 0:c9112f0c67e3 | 139 | * @brief Initializes the SDRAM device. |
| bcostm | 0:c9112f0c67e3 | 140 | * @retval SDRAM status |
| bcostm | 0:c9112f0c67e3 | 141 | */ |
| bcostm | 0:c9112f0c67e3 | 142 | uint8_t BSP_SDRAM_Init(void) |
| bcostm | 0:c9112f0c67e3 | 143 | { |
| bcostm | 0:c9112f0c67e3 | 144 | static uint8_t sdramstatus = SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 145 | /* SDRAM device configuration */ |
| bcostm | 0:c9112f0c67e3 | 146 | sdramHandle.Instance = FMC_SDRAM_DEVICE; |
| bcostm | 0:c9112f0c67e3 | 147 | |
| bcostm | 0:c9112f0c67e3 | 148 | /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */ |
| bcostm | 0:c9112f0c67e3 | 149 | Timing.LoadToActiveDelay = 2; |
| bcostm | 0:c9112f0c67e3 | 150 | Timing.ExitSelfRefreshDelay = 7; |
| bcostm | 0:c9112f0c67e3 | 151 | Timing.SelfRefreshTime = 4; |
| bcostm | 0:c9112f0c67e3 | 152 | Timing.RowCycleDelay = 7; |
| bcostm | 0:c9112f0c67e3 | 153 | Timing.WriteRecoveryTime = 2; |
| bcostm | 0:c9112f0c67e3 | 154 | Timing.RPDelay = 2; |
| bcostm | 0:c9112f0c67e3 | 155 | Timing.RCDDelay = 2; |
| bcostm | 0:c9112f0c67e3 | 156 | |
| bcostm | 0:c9112f0c67e3 | 157 | sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; |
| bcostm | 0:c9112f0c67e3 | 158 | sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; |
| bcostm | 0:c9112f0c67e3 | 159 | sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; |
| bcostm | 0:c9112f0c67e3 | 160 | sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; |
| bcostm | 0:c9112f0c67e3 | 161 | sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; |
| bcostm | 0:c9112f0c67e3 | 162 | sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; |
| bcostm | 0:c9112f0c67e3 | 163 | sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; |
| bcostm | 0:c9112f0c67e3 | 164 | sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; |
| bcostm | 0:c9112f0c67e3 | 165 | sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; |
| bcostm | 0:c9112f0c67e3 | 166 | sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; |
| bcostm | 0:c9112f0c67e3 | 167 | |
| bcostm | 0:c9112f0c67e3 | 168 | /* SDRAM controller initialization */ |
| bcostm | 0:c9112f0c67e3 | 169 | |
| bcostm | 0:c9112f0c67e3 | 170 | BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ |
| bcostm | 0:c9112f0c67e3 | 171 | |
| bcostm | 0:c9112f0c67e3 | 172 | if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) |
| bcostm | 0:c9112f0c67e3 | 173 | { |
| bcostm | 0:c9112f0c67e3 | 174 | sdramstatus = SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 175 | } |
| bcostm | 0:c9112f0c67e3 | 176 | else |
| bcostm | 0:c9112f0c67e3 | 177 | { |
| bcostm | 0:c9112f0c67e3 | 178 | sdramstatus = SDRAM_OK; |
| bcostm | 0:c9112f0c67e3 | 179 | } |
| bcostm | 0:c9112f0c67e3 | 180 | |
| bcostm | 0:c9112f0c67e3 | 181 | /* SDRAM initialization sequence */ |
| bcostm | 0:c9112f0c67e3 | 182 | BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); |
| bcostm | 0:c9112f0c67e3 | 183 | |
| bcostm | 0:c9112f0c67e3 | 184 | return sdramstatus; |
| bcostm | 0:c9112f0c67e3 | 185 | } |
| bcostm | 0:c9112f0c67e3 | 186 | |
| bcostm | 0:c9112f0c67e3 | 187 | /** |
| bcostm | 0:c9112f0c67e3 | 188 | * @brief DeInitializes the SDRAM device. |
| bcostm | 0:c9112f0c67e3 | 189 | * @retval SDRAM status |
| bcostm | 0:c9112f0c67e3 | 190 | */ |
| bcostm | 0:c9112f0c67e3 | 191 | uint8_t BSP_SDRAM_DeInit(void) |
| bcostm | 0:c9112f0c67e3 | 192 | { |
| bcostm | 0:c9112f0c67e3 | 193 | static uint8_t sdramstatus = SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 194 | /* SDRAM device de-initialization */ |
| bcostm | 0:c9112f0c67e3 | 195 | sdramHandle.Instance = FMC_SDRAM_DEVICE; |
| bcostm | 0:c9112f0c67e3 | 196 | |
| bcostm | 0:c9112f0c67e3 | 197 | if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) |
| bcostm | 0:c9112f0c67e3 | 198 | { |
| bcostm | 0:c9112f0c67e3 | 199 | sdramstatus = SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 200 | } |
| bcostm | 0:c9112f0c67e3 | 201 | else |
| bcostm | 0:c9112f0c67e3 | 202 | { |
| bcostm | 0:c9112f0c67e3 | 203 | sdramstatus = SDRAM_OK; |
| bcostm | 0:c9112f0c67e3 | 204 | } |
| bcostm | 0:c9112f0c67e3 | 205 | |
| bcostm | 0:c9112f0c67e3 | 206 | /* SDRAM controller de-initialization */ |
| bcostm | 0:c9112f0c67e3 | 207 | BSP_SDRAM_MspDeInit(&sdramHandle, NULL); |
| bcostm | 0:c9112f0c67e3 | 208 | |
| bcostm | 0:c9112f0c67e3 | 209 | return sdramstatus; |
| bcostm | 0:c9112f0c67e3 | 210 | } |
| bcostm | 0:c9112f0c67e3 | 211 | |
| bcostm | 0:c9112f0c67e3 | 212 | /** |
| bcostm | 0:c9112f0c67e3 | 213 | * @brief Programs the SDRAM device. |
| bcostm | 0:c9112f0c67e3 | 214 | * @param RefreshCount: SDRAM refresh counter value |
| bcostm | 0:c9112f0c67e3 | 215 | * @retval None |
| bcostm | 0:c9112f0c67e3 | 216 | */ |
| bcostm | 0:c9112f0c67e3 | 217 | void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) |
| bcostm | 0:c9112f0c67e3 | 218 | { |
| bcostm | 0:c9112f0c67e3 | 219 | __IO uint32_t tmpmrd = 0; |
| bcostm | 0:c9112f0c67e3 | 220 | |
| bcostm | 0:c9112f0c67e3 | 221 | /* Step 1: Configure a clock configuration enable command */ |
| bcostm | 0:c9112f0c67e3 | 222 | Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; |
| bcostm | 0:c9112f0c67e3 | 223 | Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; |
| bcostm | 0:c9112f0c67e3 | 224 | Command.AutoRefreshNumber = 1; |
| bcostm | 0:c9112f0c67e3 | 225 | Command.ModeRegisterDefinition = 0; |
| bcostm | 0:c9112f0c67e3 | 226 | |
| bcostm | 0:c9112f0c67e3 | 227 | /* Send the command */ |
| bcostm | 0:c9112f0c67e3 | 228 | HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); |
| bcostm | 0:c9112f0c67e3 | 229 | |
| bcostm | 0:c9112f0c67e3 | 230 | /* Step 2: Insert 100 us minimum delay */ |
| bcostm | 0:c9112f0c67e3 | 231 | /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ |
| bcostm | 0:c9112f0c67e3 | 232 | //HAL_Delay(1); |
| bcostm | 0:c9112f0c67e3 | 233 | wait_ms(1); |
| bcostm | 0:c9112f0c67e3 | 234 | |
| bcostm | 0:c9112f0c67e3 | 235 | /* Step 3: Configure a PALL (precharge all) command */ |
| bcostm | 0:c9112f0c67e3 | 236 | Command.CommandMode = FMC_SDRAM_CMD_PALL; |
| bcostm | 0:c9112f0c67e3 | 237 | Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; |
| bcostm | 0:c9112f0c67e3 | 238 | Command.AutoRefreshNumber = 1; |
| bcostm | 0:c9112f0c67e3 | 239 | Command.ModeRegisterDefinition = 0; |
| bcostm | 0:c9112f0c67e3 | 240 | |
| bcostm | 0:c9112f0c67e3 | 241 | /* Send the command */ |
| bcostm | 0:c9112f0c67e3 | 242 | HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); |
| bcostm | 0:c9112f0c67e3 | 243 | |
| bcostm | 0:c9112f0c67e3 | 244 | /* Step 4: Configure an Auto Refresh command */ |
| bcostm | 0:c9112f0c67e3 | 245 | Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; |
| bcostm | 0:c9112f0c67e3 | 246 | Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; |
| bcostm | 0:c9112f0c67e3 | 247 | Command.AutoRefreshNumber = 8; |
| bcostm | 0:c9112f0c67e3 | 248 | Command.ModeRegisterDefinition = 0; |
| bcostm | 0:c9112f0c67e3 | 249 | |
| bcostm | 0:c9112f0c67e3 | 250 | /* Send the command */ |
| bcostm | 0:c9112f0c67e3 | 251 | HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); |
| bcostm | 0:c9112f0c67e3 | 252 | |
| bcostm | 0:c9112f0c67e3 | 253 | /* Step 5: Program the external memory mode register */ |
| bcostm | 0:c9112f0c67e3 | 254 | tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ |
| bcostm | 0:c9112f0c67e3 | 255 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ |
| bcostm | 0:c9112f0c67e3 | 256 | SDRAM_MODEREG_CAS_LATENCY_2 |\ |
| bcostm | 0:c9112f0c67e3 | 257 | SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ |
| bcostm | 0:c9112f0c67e3 | 258 | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; |
| bcostm | 0:c9112f0c67e3 | 259 | |
| bcostm | 0:c9112f0c67e3 | 260 | Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; |
| bcostm | 0:c9112f0c67e3 | 261 | Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; |
| bcostm | 0:c9112f0c67e3 | 262 | Command.AutoRefreshNumber = 1; |
| bcostm | 0:c9112f0c67e3 | 263 | Command.ModeRegisterDefinition = tmpmrd; |
| bcostm | 0:c9112f0c67e3 | 264 | |
| bcostm | 0:c9112f0c67e3 | 265 | /* Send the command */ |
| bcostm | 0:c9112f0c67e3 | 266 | HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); |
| bcostm | 0:c9112f0c67e3 | 267 | |
| bcostm | 0:c9112f0c67e3 | 268 | /* Step 6: Set the refresh rate counter */ |
| bcostm | 0:c9112f0c67e3 | 269 | /* Set the device refresh rate */ |
| bcostm | 0:c9112f0c67e3 | 270 | HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); |
| bcostm | 0:c9112f0c67e3 | 271 | } |
| bcostm | 0:c9112f0c67e3 | 272 | |
| bcostm | 0:c9112f0c67e3 | 273 | /** |
| bcostm | 0:c9112f0c67e3 | 274 | * @brief Reads an amount of data from the SDRAM memory in polling mode. |
| bcostm | 0:c9112f0c67e3 | 275 | * @param uwStartAddress: Read start address |
| bcostm | 0:c9112f0c67e3 | 276 | * @param pData: Pointer to data to be read |
| bcostm | 0:c9112f0c67e3 | 277 | * @param uwDataSize: Size of read data from the memory |
| bcostm | 0:c9112f0c67e3 | 278 | * @retval SDRAM status |
| bcostm | 0:c9112f0c67e3 | 279 | */ |
| bcostm | 0:c9112f0c67e3 | 280 | uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) |
| bcostm | 0:c9112f0c67e3 | 281 | { |
| bcostm | 0:c9112f0c67e3 | 282 | if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) |
| bcostm | 0:c9112f0c67e3 | 283 | { |
| bcostm | 0:c9112f0c67e3 | 284 | return SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 285 | } |
| bcostm | 0:c9112f0c67e3 | 286 | else |
| bcostm | 0:c9112f0c67e3 | 287 | { |
| bcostm | 0:c9112f0c67e3 | 288 | return SDRAM_OK; |
| bcostm | 0:c9112f0c67e3 | 289 | } |
| bcostm | 0:c9112f0c67e3 | 290 | } |
| bcostm | 0:c9112f0c67e3 | 291 | |
| bcostm | 0:c9112f0c67e3 | 292 | /** |
| bcostm | 0:c9112f0c67e3 | 293 | * @brief Reads an amount of data from the SDRAM memory in DMA mode. |
| bcostm | 0:c9112f0c67e3 | 294 | * @param uwStartAddress: Read start address |
| bcostm | 0:c9112f0c67e3 | 295 | * @param pData: Pointer to data to be read |
| bcostm | 0:c9112f0c67e3 | 296 | * @param uwDataSize: Size of read data from the memory |
| bcostm | 0:c9112f0c67e3 | 297 | * @retval SDRAM status |
| bcostm | 0:c9112f0c67e3 | 298 | */ |
| bcostm | 0:c9112f0c67e3 | 299 | uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) |
| bcostm | 0:c9112f0c67e3 | 300 | { |
| bcostm | 0:c9112f0c67e3 | 301 | if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) |
| bcostm | 0:c9112f0c67e3 | 302 | { |
| bcostm | 0:c9112f0c67e3 | 303 | return SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 304 | } |
| bcostm | 0:c9112f0c67e3 | 305 | else |
| bcostm | 0:c9112f0c67e3 | 306 | { |
| bcostm | 0:c9112f0c67e3 | 307 | return SDRAM_OK; |
| bcostm | 0:c9112f0c67e3 | 308 | } |
| bcostm | 0:c9112f0c67e3 | 309 | } |
| bcostm | 0:c9112f0c67e3 | 310 | |
| bcostm | 0:c9112f0c67e3 | 311 | /** |
| bcostm | 0:c9112f0c67e3 | 312 | * @brief Writes an amount of data to the SDRAM memory in polling mode. |
| bcostm | 0:c9112f0c67e3 | 313 | * @param uwStartAddress: Write start address |
| bcostm | 0:c9112f0c67e3 | 314 | * @param pData: Pointer to data to be written |
| bcostm | 0:c9112f0c67e3 | 315 | * @param uwDataSize: Size of written data from the memory |
| bcostm | 0:c9112f0c67e3 | 316 | * @retval SDRAM status |
| bcostm | 0:c9112f0c67e3 | 317 | */ |
| bcostm | 0:c9112f0c67e3 | 318 | uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) |
| bcostm | 0:c9112f0c67e3 | 319 | { |
| bcostm | 0:c9112f0c67e3 | 320 | if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) |
| bcostm | 0:c9112f0c67e3 | 321 | { |
| bcostm | 0:c9112f0c67e3 | 322 | return SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 323 | } |
| bcostm | 0:c9112f0c67e3 | 324 | else |
| bcostm | 0:c9112f0c67e3 | 325 | { |
| bcostm | 0:c9112f0c67e3 | 326 | return SDRAM_OK; |
| bcostm | 0:c9112f0c67e3 | 327 | } |
| bcostm | 0:c9112f0c67e3 | 328 | } |
| bcostm | 0:c9112f0c67e3 | 329 | |
| bcostm | 0:c9112f0c67e3 | 330 | /** |
| bcostm | 0:c9112f0c67e3 | 331 | * @brief Writes an amount of data to the SDRAM memory in DMA mode. |
| bcostm | 0:c9112f0c67e3 | 332 | * @param uwStartAddress: Write start address |
| bcostm | 0:c9112f0c67e3 | 333 | * @param pData: Pointer to data to be written |
| bcostm | 0:c9112f0c67e3 | 334 | * @param uwDataSize: Size of written data from the memory |
| bcostm | 0:c9112f0c67e3 | 335 | * @retval SDRAM status |
| bcostm | 0:c9112f0c67e3 | 336 | */ |
| bcostm | 0:c9112f0c67e3 | 337 | uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) |
| bcostm | 0:c9112f0c67e3 | 338 | { |
| bcostm | 0:c9112f0c67e3 | 339 | if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) |
| bcostm | 0:c9112f0c67e3 | 340 | { |
| bcostm | 0:c9112f0c67e3 | 341 | return SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 342 | } |
| bcostm | 0:c9112f0c67e3 | 343 | else |
| bcostm | 0:c9112f0c67e3 | 344 | { |
| bcostm | 0:c9112f0c67e3 | 345 | return SDRAM_OK; |
| bcostm | 0:c9112f0c67e3 | 346 | } |
| bcostm | 0:c9112f0c67e3 | 347 | } |
| bcostm | 0:c9112f0c67e3 | 348 | |
| bcostm | 0:c9112f0c67e3 | 349 | /** |
| bcostm | 0:c9112f0c67e3 | 350 | * @brief Sends command to the SDRAM bank. |
| bcostm | 0:c9112f0c67e3 | 351 | * @param SdramCmd: Pointer to SDRAM command structure |
| bcostm | 0:c9112f0c67e3 | 352 | * @retval SDRAM status |
| bcostm | 0:c9112f0c67e3 | 353 | */ |
| bcostm | 0:c9112f0c67e3 | 354 | uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) |
| bcostm | 0:c9112f0c67e3 | 355 | { |
| bcostm | 0:c9112f0c67e3 | 356 | if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) |
| bcostm | 0:c9112f0c67e3 | 357 | { |
| bcostm | 0:c9112f0c67e3 | 358 | return SDRAM_ERROR; |
| bcostm | 0:c9112f0c67e3 | 359 | } |
| bcostm | 0:c9112f0c67e3 | 360 | else |
| bcostm | 0:c9112f0c67e3 | 361 | { |
| bcostm | 0:c9112f0c67e3 | 362 | return SDRAM_OK; |
| bcostm | 0:c9112f0c67e3 | 363 | } |
| bcostm | 0:c9112f0c67e3 | 364 | } |
| bcostm | 0:c9112f0c67e3 | 365 | |
| bcostm | 0:c9112f0c67e3 | 366 | /** |
| bcostm | 0:c9112f0c67e3 | 367 | * @brief Handles SDRAM DMA transfer interrupt request. |
| bcostm | 0:c9112f0c67e3 | 368 | * @retval None |
| bcostm | 0:c9112f0c67e3 | 369 | */ |
| bcostm | 0:c9112f0c67e3 | 370 | void BSP_SDRAM_DMA_IRQHandler(void) |
| bcostm | 0:c9112f0c67e3 | 371 | { |
| bcostm | 0:c9112f0c67e3 | 372 | HAL_DMA_IRQHandler(sdramHandle.hdma); |
| bcostm | 0:c9112f0c67e3 | 373 | } |
| bcostm | 0:c9112f0c67e3 | 374 | |
| bcostm | 0:c9112f0c67e3 | 375 | /** |
| bcostm | 0:c9112f0c67e3 | 376 | * @brief Initializes SDRAM MSP. |
| bcostm | 0:c9112f0c67e3 | 377 | * @param hsdram: SDRAM handle |
| bcostm | 0:c9112f0c67e3 | 378 | * @param Params |
| bcostm | 0:c9112f0c67e3 | 379 | * @retval None |
| bcostm | 0:c9112f0c67e3 | 380 | */ |
| bcostm | 0:c9112f0c67e3 | 381 | __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) |
| bcostm | 0:c9112f0c67e3 | 382 | { |
| bcostm | 0:c9112f0c67e3 | 383 | static DMA_HandleTypeDef dma_handle; |
| bcostm | 0:c9112f0c67e3 | 384 | GPIO_InitTypeDef gpio_init_structure; |
| bcostm | 0:c9112f0c67e3 | 385 | |
| bcostm | 0:c9112f0c67e3 | 386 | /* Enable FMC clock */ |
| bcostm | 0:c9112f0c67e3 | 387 | __HAL_RCC_FMC_CLK_ENABLE(); |
| bcostm | 0:c9112f0c67e3 | 388 | |
| bcostm | 0:c9112f0c67e3 | 389 | /* Enable chosen DMAx clock */ |
| bcostm | 0:c9112f0c67e3 | 390 | __DMAx_CLK_ENABLE(); |
| bcostm | 0:c9112f0c67e3 | 391 | |
| bcostm | 0:c9112f0c67e3 | 392 | /* Enable GPIOs clock */ |
| bcostm | 0:c9112f0c67e3 | 393 | __HAL_RCC_GPIOC_CLK_ENABLE(); |
| bcostm | 0:c9112f0c67e3 | 394 | __HAL_RCC_GPIOD_CLK_ENABLE(); |
| bcostm | 0:c9112f0c67e3 | 395 | __HAL_RCC_GPIOE_CLK_ENABLE(); |
| bcostm | 0:c9112f0c67e3 | 396 | __HAL_RCC_GPIOF_CLK_ENABLE(); |
| bcostm | 0:c9112f0c67e3 | 397 | __HAL_RCC_GPIOG_CLK_ENABLE(); |
| bcostm | 0:c9112f0c67e3 | 398 | __HAL_RCC_GPIOH_CLK_ENABLE(); |
| bcostm | 0:c9112f0c67e3 | 399 | |
| bcostm | 0:c9112f0c67e3 | 400 | /* Common GPIO configuration */ |
| bcostm | 0:c9112f0c67e3 | 401 | gpio_init_structure.Mode = GPIO_MODE_AF_PP; |
| bcostm | 0:c9112f0c67e3 | 402 | gpio_init_structure.Pull = GPIO_PULLUP; |
| bcostm | 0:c9112f0c67e3 | 403 | gpio_init_structure.Speed = GPIO_SPEED_FAST; |
| bcostm | 0:c9112f0c67e3 | 404 | gpio_init_structure.Alternate = GPIO_AF12_FMC; |
| bcostm | 0:c9112f0c67e3 | 405 | |
| bcostm | 0:c9112f0c67e3 | 406 | /* GPIOC configuration */ |
| bcostm | 0:c9112f0c67e3 | 407 | gpio_init_structure.Pin = GPIO_PIN_3; |
| bcostm | 0:c9112f0c67e3 | 408 | HAL_GPIO_Init(GPIOC, &gpio_init_structure); |
| bcostm | 0:c9112f0c67e3 | 409 | |
| bcostm | 0:c9112f0c67e3 | 410 | /* GPIOD configuration */ |
| bcostm | 0:c9112f0c67e3 | 411 | gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 | |
| bcostm | 0:c9112f0c67e3 | 412 | GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; |
| bcostm | 0:c9112f0c67e3 | 413 | HAL_GPIO_Init(GPIOD, &gpio_init_structure); |
| bcostm | 0:c9112f0c67e3 | 414 | |
| bcostm | 0:c9112f0c67e3 | 415 | /* GPIOE configuration */ |
| bcostm | 0:c9112f0c67e3 | 416 | gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ |
| bcostm | 0:c9112f0c67e3 | 417 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ |
| bcostm | 0:c9112f0c67e3 | 418 | GPIO_PIN_15; |
| bcostm | 0:c9112f0c67e3 | 419 | HAL_GPIO_Init(GPIOE, &gpio_init_structure); |
| bcostm | 0:c9112f0c67e3 | 420 | |
| bcostm | 0:c9112f0c67e3 | 421 | /* GPIOF configuration */ |
| bcostm | 0:c9112f0c67e3 | 422 | gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ |
| bcostm | 0:c9112f0c67e3 | 423 | GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ |
| bcostm | 0:c9112f0c67e3 | 424 | GPIO_PIN_15; |
| bcostm | 0:c9112f0c67e3 | 425 | HAL_GPIO_Init(GPIOF, &gpio_init_structure); |
| bcostm | 0:c9112f0c67e3 | 426 | |
| bcostm | 0:c9112f0c67e3 | 427 | /* GPIOG configuration */ |
| bcostm | 0:c9112f0c67e3 | 428 | gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ |
| bcostm | 0:c9112f0c67e3 | 429 | GPIO_PIN_15; |
| bcostm | 0:c9112f0c67e3 | 430 | HAL_GPIO_Init(GPIOG, &gpio_init_structure); |
| bcostm | 0:c9112f0c67e3 | 431 | |
| bcostm | 0:c9112f0c67e3 | 432 | /* GPIOH configuration */ |
| bcostm | 0:c9112f0c67e3 | 433 | gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; |
| bcostm | 0:c9112f0c67e3 | 434 | HAL_GPIO_Init(GPIOH, &gpio_init_structure); |
| bcostm | 0:c9112f0c67e3 | 435 | |
| bcostm | 0:c9112f0c67e3 | 436 | /* Configure common DMA parameters */ |
| bcostm | 0:c9112f0c67e3 | 437 | dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; |
| bcostm | 0:c9112f0c67e3 | 438 | dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; |
| bcostm | 0:c9112f0c67e3 | 439 | dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; |
| bcostm | 0:c9112f0c67e3 | 440 | dma_handle.Init.MemInc = DMA_MINC_ENABLE; |
| bcostm | 0:c9112f0c67e3 | 441 | dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; |
| bcostm | 0:c9112f0c67e3 | 442 | dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; |
| bcostm | 0:c9112f0c67e3 | 443 | dma_handle.Init.Mode = DMA_NORMAL; |
| bcostm | 0:c9112f0c67e3 | 444 | dma_handle.Init.Priority = DMA_PRIORITY_HIGH; |
| bcostm | 0:c9112f0c67e3 | 445 | dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; |
| bcostm | 0:c9112f0c67e3 | 446 | dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; |
| bcostm | 0:c9112f0c67e3 | 447 | dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; |
| bcostm | 0:c9112f0c67e3 | 448 | dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; |
| bcostm | 0:c9112f0c67e3 | 449 | |
| bcostm | 0:c9112f0c67e3 | 450 | dma_handle.Instance = SDRAM_DMAx_STREAM; |
| bcostm | 0:c9112f0c67e3 | 451 | |
| bcostm | 0:c9112f0c67e3 | 452 | /* Associate the DMA handle */ |
| bcostm | 0:c9112f0c67e3 | 453 | __HAL_LINKDMA(hsdram, hdma, dma_handle); |
| bcostm | 0:c9112f0c67e3 | 454 | |
| bcostm | 0:c9112f0c67e3 | 455 | /* Deinitialize the stream for new transfer */ |
| bcostm | 0:c9112f0c67e3 | 456 | HAL_DMA_DeInit(&dma_handle); |
| bcostm | 0:c9112f0c67e3 | 457 | |
| bcostm | 0:c9112f0c67e3 | 458 | /* Configure the DMA stream */ |
| bcostm | 0:c9112f0c67e3 | 459 | HAL_DMA_Init(&dma_handle); |
| bcostm | 0:c9112f0c67e3 | 460 | |
| bcostm | 0:c9112f0c67e3 | 461 | /* NVIC configuration for DMA transfer complete interrupt */ |
| bcostm | 0:c9112f0c67e3 | 462 | HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); |
| bcostm | 0:c9112f0c67e3 | 463 | HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); |
| bcostm | 0:c9112f0c67e3 | 464 | } |
| bcostm | 0:c9112f0c67e3 | 465 | |
| bcostm | 0:c9112f0c67e3 | 466 | /** |
| bcostm | 0:c9112f0c67e3 | 467 | * @brief DeInitializes SDRAM MSP. |
| bcostm | 0:c9112f0c67e3 | 468 | * @param hsdram: SDRAM handle |
| bcostm | 0:c9112f0c67e3 | 469 | * @param Params |
| bcostm | 0:c9112f0c67e3 | 470 | * @retval None |
| bcostm | 0:c9112f0c67e3 | 471 | */ |
| bcostm | 0:c9112f0c67e3 | 472 | __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) |
| bcostm | 0:c9112f0c67e3 | 473 | { |
| bcostm | 0:c9112f0c67e3 | 474 | static DMA_HandleTypeDef dma_handle; |
| bcostm | 0:c9112f0c67e3 | 475 | |
| bcostm | 0:c9112f0c67e3 | 476 | /* Disable NVIC configuration for DMA interrupt */ |
| bcostm | 0:c9112f0c67e3 | 477 | HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); |
| bcostm | 0:c9112f0c67e3 | 478 | |
| bcostm | 0:c9112f0c67e3 | 479 | /* Deinitialize the stream for new transfer */ |
| bcostm | 0:c9112f0c67e3 | 480 | dma_handle.Instance = SDRAM_DMAx_STREAM; |
| bcostm | 0:c9112f0c67e3 | 481 | HAL_DMA_DeInit(&dma_handle); |
| bcostm | 0:c9112f0c67e3 | 482 | |
| bcostm | 0:c9112f0c67e3 | 483 | /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications |
| bcostm | 0:c9112f0c67e3 | 484 | by surcharging this __weak function */ |
| bcostm | 0:c9112f0c67e3 | 485 | } |
| bcostm | 0:c9112f0c67e3 | 486 | |
| bcostm | 0:c9112f0c67e3 | 487 | /** |
| bcostm | 0:c9112f0c67e3 | 488 | * @} |
| bcostm | 0:c9112f0c67e3 | 489 | */ |
| bcostm | 0:c9112f0c67e3 | 490 | |
| bcostm | 0:c9112f0c67e3 | 491 | /** |
| bcostm | 0:c9112f0c67e3 | 492 | * @} |
| bcostm | 0:c9112f0c67e3 | 493 | */ |
| bcostm | 0:c9112f0c67e3 | 494 | |
| bcostm | 0:c9112f0c67e3 | 495 | /** |
| bcostm | 0:c9112f0c67e3 | 496 | * @} |
| bcostm | 0:c9112f0c67e3 | 497 | */ |
| bcostm | 0:c9112f0c67e3 | 498 | |
| bcostm | 0:c9112f0c67e3 | 499 | /** |
| bcostm | 0:c9112f0c67e3 | 500 | * @} |
| bcostm | 0:c9112f0c67e3 | 501 | */ |
| bcostm | 0:c9112f0c67e3 | 502 | |
| bcostm | 0:c9112f0c67e3 | 503 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |