test

Dependencies:   BMI160 max32630hsp3 MemoryLCD USBDevice

Committer:
seyhmus.cacina
Date:
Mon Mar 18 10:21:53 2019 +0300
Revision:
0:ac4dea3e2894
ME11B Sample Code First Commit

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seyhmus.cacina 0:ac4dea3e2894 1 /*******************************************************************************
seyhmus.cacina 0:ac4dea3e2894 2 * Copyright (C) 2018 Maxim Integrated Products, Inc., All Rights Reserved.
seyhmus.cacina 0:ac4dea3e2894 3 *
seyhmus.cacina 0:ac4dea3e2894 4 * Permission is hereby granted, free of charge, to any person obtaining a
seyhmus.cacina 0:ac4dea3e2894 5 * copy of this software and associated documentation files (the "Software"),
seyhmus.cacina 0:ac4dea3e2894 6 * to deal in the Software without restriction, including without limitation
seyhmus.cacina 0:ac4dea3e2894 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
seyhmus.cacina 0:ac4dea3e2894 8 * and/or sell copies of the Software, and to permit persons to whom the
seyhmus.cacina 0:ac4dea3e2894 9 * Software is furnished to do so, subject to the following conditions:
seyhmus.cacina 0:ac4dea3e2894 10 *
seyhmus.cacina 0:ac4dea3e2894 11 * The above copyright notice and this permission notice shall be included
seyhmus.cacina 0:ac4dea3e2894 12 * in all copies or substantial portions of the Software.
seyhmus.cacina 0:ac4dea3e2894 13 *
seyhmus.cacina 0:ac4dea3e2894 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
seyhmus.cacina 0:ac4dea3e2894 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
seyhmus.cacina 0:ac4dea3e2894 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
seyhmus.cacina 0:ac4dea3e2894 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
seyhmus.cacina 0:ac4dea3e2894 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
seyhmus.cacina 0:ac4dea3e2894 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
seyhmus.cacina 0:ac4dea3e2894 20 * OTHER DEALINGS IN THE SOFTWARE.
seyhmus.cacina 0:ac4dea3e2894 21 *
seyhmus.cacina 0:ac4dea3e2894 22 * Except as contained in this notice, the name of Maxim Integrated
seyhmus.cacina 0:ac4dea3e2894 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
seyhmus.cacina 0:ac4dea3e2894 24 * Products, Inc. Branding Policy.
seyhmus.cacina 0:ac4dea3e2894 25 *
seyhmus.cacina 0:ac4dea3e2894 26 * The mere transfer of this software does not imply any licenses
seyhmus.cacina 0:ac4dea3e2894 27 * of trade secrets, proprietary technology, copyrights, patents,
seyhmus.cacina 0:ac4dea3e2894 28 * trademarks, maskwork rights, or any other form of intellectual
seyhmus.cacina 0:ac4dea3e2894 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
seyhmus.cacina 0:ac4dea3e2894 30 * ownership rights.
seyhmus.cacina 0:ac4dea3e2894 31 *******************************************************************************
seyhmus.cacina 0:ac4dea3e2894 32 */
seyhmus.cacina 0:ac4dea3e2894 33 #ifndef __MAX20303_H_
seyhmus.cacina 0:ac4dea3e2894 34 #define __MAX20303_H_
seyhmus.cacina 0:ac4dea3e2894 35
seyhmus.cacina 0:ac4dea3e2894 36 #include "mbed.h"
seyhmus.cacina 0:ac4dea3e2894 37
seyhmus.cacina 0:ac4dea3e2894 38 #define MAX20303_SLAVE_ADDR (0x50 >> 1)
seyhmus.cacina 0:ac4dea3e2894 39 #define MAX20303_SLAVE_WR_ADDR ((MAX20303_SLAVE_ADDR << 1))
seyhmus.cacina 0:ac4dea3e2894 40 #define MAX20303_SLAVE_RD_ADDR ((MAX20303_SLAVE_ADDR << 1) | 1)
seyhmus.cacina 0:ac4dea3e2894 41
seyhmus.cacina 0:ac4dea3e2894 42
seyhmus.cacina 0:ac4dea3e2894 43 #define MAX20303_NO_ERROR 0
seyhmus.cacina 0:ac4dea3e2894 44 #define MAX20303_ERROR -1
seyhmus.cacina 0:ac4dea3e2894 45
seyhmus.cacina 0:ac4dea3e2894 46 #define MAX20303_I2C_ADDR_FUEL_GAUGE 0x6c
seyhmus.cacina 0:ac4dea3e2894 47 #define MAX20303_I2C_ADDR_FUEL_GAUGE 0x6C
seyhmus.cacina 0:ac4dea3e2894 48
seyhmus.cacina 0:ac4dea3e2894 49 #define MAX20303_LDO_MIN_MV 800
seyhmus.cacina 0:ac4dea3e2894 50 #define MAX20303_LDO_MAX_MV 3600
seyhmus.cacina 0:ac4dea3e2894 51 #define MAX20303_LDO_STEP_MV 100
seyhmus.cacina 0:ac4dea3e2894 52
seyhmus.cacina 0:ac4dea3e2894 53 #define MAX20303_OFF_COMMAND 0xB2
seyhmus.cacina 0:ac4dea3e2894 54
seyhmus.cacina 0:ac4dea3e2894 55 class MAX20303
seyhmus.cacina 0:ac4dea3e2894 56 {
seyhmus.cacina 0:ac4dea3e2894 57
seyhmus.cacina 0:ac4dea3e2894 58 public:
seyhmus.cacina 0:ac4dea3e2894 59 /**
seyhmus.cacina 0:ac4dea3e2894 60 * @brief Register Addresses
seyhmus.cacina 0:ac4dea3e2894 61 * @details Enumerated MAX20303 register addresses
seyhmus.cacina 0:ac4dea3e2894 62 */
seyhmus.cacina 0:ac4dea3e2894 63 enum registers_t {
seyhmus.cacina 0:ac4dea3e2894 64 REG_HARDWARE_ID = 0x00, ///< HardwareID Register
seyhmus.cacina 0:ac4dea3e2894 65 REG_FIRMWARE_REV = 0x01, ///< FirmwareID Register
seyhmus.cacina 0:ac4dea3e2894 66 // = 0x02, ///<
seyhmus.cacina 0:ac4dea3e2894 67 REG_INT0 = 0x03, ///< Int0 Register
seyhmus.cacina 0:ac4dea3e2894 68 REG_INT1 = 0x04, ///< Int1 Register
seyhmus.cacina 0:ac4dea3e2894 69 REG_INT2 = 0x05, ///< Int2 Register
seyhmus.cacina 0:ac4dea3e2894 70 REG_STATUS0 = 0x06, ///< Status Register 0
seyhmus.cacina 0:ac4dea3e2894 71 REG_STATUS1 = 0x07, ///< Status Register 1
seyhmus.cacina 0:ac4dea3e2894 72 REG_STATUS2 = 0x08, ///< Status Register 2
seyhmus.cacina 0:ac4dea3e2894 73 REG_STATUS3 = 0x09, ///< Status Register 2
seyhmus.cacina 0:ac4dea3e2894 74 // = 0x0A, ///<
seyhmus.cacina 0:ac4dea3e2894 75 REG_SYSTEM_ERROR = 0x0B, ///< SystemError Register
seyhmus.cacina 0:ac4dea3e2894 76 REG_INT_MASK0 = 0x0C, ///< IntMask0 Register
seyhmus.cacina 0:ac4dea3e2894 77 REG_INT_MASK1 = 0x0D, ///< IntMask1 Register
seyhmus.cacina 0:ac4dea3e2894 78 REG_INT_MASK2 = 0x0E, ///< IntMask1 Register
seyhmus.cacina 0:ac4dea3e2894 79 REG_AP_DATOUT0 = 0x0F, ///< APDataOut0 Register
seyhmus.cacina 0:ac4dea3e2894 80 REG_AP_DATOUT1 = 0x10, ///< APDataOut1 Register
seyhmus.cacina 0:ac4dea3e2894 81 REG_AP_DATOUT2 = 0x11, ///< APDataOut2 Register
seyhmus.cacina 0:ac4dea3e2894 82 REG_AP_DATOUT3 = 0x12, ///< APDataOut3 Register
seyhmus.cacina 0:ac4dea3e2894 83 REG_AP_DATOUT4 = 0x13, ///< APDataOut4 Register
seyhmus.cacina 0:ac4dea3e2894 84 REG_AP_DATOUT5 = 0x14, ///< APDataOut5 Register
seyhmus.cacina 0:ac4dea3e2894 85 REG_AP_DATOUT6 = 0x15, ///< APDataOut6 Register
seyhmus.cacina 0:ac4dea3e2894 86 REG_AP_CMDOUT = 0x17, ///< APCmdOut Register
seyhmus.cacina 0:ac4dea3e2894 87 REG_AP_RESPONSE = 0x18, ///< APResponse Register
seyhmus.cacina 0:ac4dea3e2894 88 REG_AP_DATAIN0 = 0x19,
seyhmus.cacina 0:ac4dea3e2894 89 REG_AP_DATAIN1 = 0x1A,
seyhmus.cacina 0:ac4dea3e2894 90 REG_AP_DATAIN2 = 0x1B,
seyhmus.cacina 0:ac4dea3e2894 91 REG_AP_DATAIN3 = 0x1C,
seyhmus.cacina 0:ac4dea3e2894 92 REG_AP_DATAIN4 = 0x1D,
seyhmus.cacina 0:ac4dea3e2894 93 REG_AP_DATAIN5 = 0x1E,
seyhmus.cacina 0:ac4dea3e2894 94 // = 0x1F, ///<
seyhmus.cacina 0:ac4dea3e2894 95 REG_LDO_DIRECT = 0x20,
seyhmus.cacina 0:ac4dea3e2894 96 REG_MPC_DIRECTWRITE = 0x21,
seyhmus.cacina 0:ac4dea3e2894 97 REG_MPC_DIRECTRED = 0x22,
seyhmus.cacina 0:ac4dea3e2894 98
seyhmus.cacina 0:ac4dea3e2894 99 REG_LED_STEP_DIRECT = 0x2C,
seyhmus.cacina 0:ac4dea3e2894 100 REG_LED0_DIRECT = 0x2D,
seyhmus.cacina 0:ac4dea3e2894 101 REG_LED1_DIRECT = 0x2E,
seyhmus.cacina 0:ac4dea3e2894 102 REG_LED2_DIRECT = 0x2F,
seyhmus.cacina 0:ac4dea3e2894 103
seyhmus.cacina 0:ac4dea3e2894 104
seyhmus.cacina 0:ac4dea3e2894 105 REG_LDO1_CONFIG_WRITE = 0x40,
seyhmus.cacina 0:ac4dea3e2894 106 REG_LDO1_CONFIG_READ = 0x41,
seyhmus.cacina 0:ac4dea3e2894 107 REG_LDO2_CONFIG_WRITE = 0x42,
seyhmus.cacina 0:ac4dea3e2894 108 REG_LDO2_CONFIG_READ = 0x43
seyhmus.cacina 0:ac4dea3e2894 109
seyhmus.cacina 0:ac4dea3e2894 110 /*
seyhmus.cacina 0:ac4dea3e2894 111 REG_CHG_TMR = 0x0C, ///< Charger Timers
seyhmus.cacina 0:ac4dea3e2894 112 REG_BUCK1_CFG = 0x0D, ///< Buck 1 Configuration
seyhmus.cacina 0:ac4dea3e2894 113 REG_BUCK1_VSET = 0x0E, ///< Buck 1 Voltage Setting
seyhmus.cacina 0:ac4dea3e2894 114 REG_BUCK2_CFG = 0x0F, ///< Buck 2 Configuration
seyhmus.cacina 0:ac4dea3e2894 115 REG_BUCK2_VSET = 0x10, ///< Buck 2 Voltage Setting
seyhmus.cacina 0:ac4dea3e2894 116 REG_RSVD_11 = 0x11, ///< Reserved 0x11
seyhmus.cacina 0:ac4dea3e2894 117 REG_LDO1_CFG = 0x12, ///< LDO 1 Configuration
seyhmus.cacina 0:ac4dea3e2894 118 REG_LDO1_VSET = 0x13, ///< LDO 1 Voltage Setting
seyhmus.cacina 0:ac4dea3e2894 119 REG_LDO2_CFG = 0x14, ///< LDO 2 Configuration
seyhmus.cacina 0:ac4dea3e2894 120 REG_LDO2_VSET = 0x15, ///< LDO 2 Voltage Setting
seyhmus.cacina 0:ac4dea3e2894 121 REG_LDO3_CFG = 0x16, ///< LDO 3 Configuration
seyhmus.cacina 0:ac4dea3e2894 122 REG_LDO3_VSET = 0x17, ///< LDO 3 Voltage Setting
seyhmus.cacina 0:ac4dea3e2894 123 REG_THRM_CFG = 0x18, ///< Thermistor Configuration
seyhmus.cacina 0:ac4dea3e2894 124 REG_MON_CFG = 0x19, ///< Monitor Multiplexer Configuration
seyhmus.cacina 0:ac4dea3e2894 125 REG_BOOT_CFG = 0x1A, ///< Boot Configuration
seyhmus.cacina 0:ac4dea3e2894 126 REG_PIN_STATUS = 0x1B, ///< Pin Status
seyhmus.cacina 0:ac4dea3e2894 127 REG_BUCK_EXTRA = 0x1C, ///< Additional Buck Settings
seyhmus.cacina 0:ac4dea3e2894 128 REG_PWR_CFG = 0x1D, ///< Power Configuration
seyhmus.cacina 0:ac4dea3e2894 129 REG_NULL = 0x1E, ///< Reserved 0x1E
seyhmus.cacina 0:ac4dea3e2894 130 REG_PWR_OFF = 0x1F, ///< Power Off Register
seyhmus.cacina 0:ac4dea3e2894 131 */
seyhmus.cacina 0:ac4dea3e2894 132 };
seyhmus.cacina 0:ac4dea3e2894 133
seyhmus.cacina 0:ac4dea3e2894 134 /**
seyhmus.cacina 0:ac4dea3e2894 135 * @brief Constructor using reference to I2C object
seyhmus.cacina 0:ac4dea3e2894 136 * @param i2c - Reference to I2C object
seyhmus.cacina 0:ac4dea3e2894 137 * @param slaveAddress - 7-bit I2C address
seyhmus.cacina 0:ac4dea3e2894 138 */
seyhmus.cacina 0:ac4dea3e2894 139 MAX20303(I2C *i2c);
seyhmus.cacina 0:ac4dea3e2894 140
seyhmus.cacina 0:ac4dea3e2894 141 /** @brief Destructor */
seyhmus.cacina 0:ac4dea3e2894 142 ~MAX20303(void);
seyhmus.cacina 0:ac4dea3e2894 143
seyhmus.cacina 0:ac4dea3e2894 144 int led0on(char enable);
seyhmus.cacina 0:ac4dea3e2894 145 int led1on(char enable);
seyhmus.cacina 0:ac4dea3e2894 146 int led2on(char enable);
seyhmus.cacina 0:ac4dea3e2894 147 int BoostEnable(void);
seyhmus.cacina 0:ac4dea3e2894 148 int BuckBoostEnable(void);
seyhmus.cacina 0:ac4dea3e2894 149
seyhmus.cacina 0:ac4dea3e2894 150 /// @brief Enable the 1.8V output rail **/
seyhmus.cacina 0:ac4dea3e2894 151 int LDO1Config(void);
seyhmus.cacina 0:ac4dea3e2894 152
seyhmus.cacina 0:ac4dea3e2894 153 /// @brief Enable the 3V output rail **/
seyhmus.cacina 0:ac4dea3e2894 154 int LDO2Config(void);
seyhmus.cacina 0:ac4dea3e2894 155
seyhmus.cacina 0:ac4dea3e2894 156
seyhmus.cacina 0:ac4dea3e2894 157 int mv2bits(int mV);
seyhmus.cacina 0:ac4dea3e2894 158
seyhmus.cacina 0:ac4dea3e2894 159 /** @brief Power Off the board
seyhmus.cacina 0:ac4dea3e2894 160 */
seyhmus.cacina 0:ac4dea3e2894 161 int PowerOffthePMIC();
seyhmus.cacina 0:ac4dea3e2894 162
seyhmus.cacina 0:ac4dea3e2894 163 /** @brief Power Off the board with 30ms delay
seyhmus.cacina 0:ac4dea3e2894 164 */
seyhmus.cacina 0:ac4dea3e2894 165 int PowerOffDelaythePMIC();
seyhmus.cacina 0:ac4dea3e2894 166
seyhmus.cacina 0:ac4dea3e2894 167 /** @brief Soft reset the PMIC
seyhmus.cacina 0:ac4dea3e2894 168 */
seyhmus.cacina 0:ac4dea3e2894 169 int SoftResetthePMIC();
seyhmus.cacina 0:ac4dea3e2894 170
seyhmus.cacina 0:ac4dea3e2894 171 /** @brief Hard reset the PMIC
seyhmus.cacina 0:ac4dea3e2894 172 */
seyhmus.cacina 0:ac4dea3e2894 173 int HardResetthePMIC();
seyhmus.cacina 0:ac4dea3e2894 174
seyhmus.cacina 0:ac4dea3e2894 175 /** @brief check if can communicate with max20303
seyhmus.cacina 0:ac4dea3e2894 176 */
seyhmus.cacina 0:ac4dea3e2894 177 char CheckPMICHWID();
seyhmus.cacina 0:ac4dea3e2894 178
seyhmus.cacina 0:ac4dea3e2894 179 /** @brief CheckPMICStatusRegisters
seyhmus.cacina 0:ac4dea3e2894 180 */
seyhmus.cacina 0:ac4dea3e2894 181 int CheckPMICStatusRegisters(unsigned char buf_results[5]);
seyhmus.cacina 0:ac4dea3e2894 182
seyhmus.cacina 0:ac4dea3e2894 183 int Max20303_BatteryGauge(unsigned char *batterylevel);
seyhmus.cacina 0:ac4dea3e2894 184
seyhmus.cacina 0:ac4dea3e2894 185 private:
seyhmus.cacina 0:ac4dea3e2894 186
seyhmus.cacina 0:ac4dea3e2894 187 int writeReg(registers_t reg, uint8_t value);
seyhmus.cacina 0:ac4dea3e2894 188 int readReg(registers_t reg, uint8_t &value);
seyhmus.cacina 0:ac4dea3e2894 189
seyhmus.cacina 0:ac4dea3e2894 190 int writeRegMulti(registers_t reg, uint8_t *value, uint8_t len);
seyhmus.cacina 0:ac4dea3e2894 191 int readRegMulti(registers_t reg, uint8_t *value, uint8_t len);
seyhmus.cacina 0:ac4dea3e2894 192
seyhmus.cacina 0:ac4dea3e2894 193 /// I2C object
seyhmus.cacina 0:ac4dea3e2894 194 I2C *m_i2c;
seyhmus.cacina 0:ac4dea3e2894 195
seyhmus.cacina 0:ac4dea3e2894 196 /// Device slave addresses
seyhmus.cacina 0:ac4dea3e2894 197 uint8_t m_writeAddress, m_readAddress;
seyhmus.cacina 0:ac4dea3e2894 198
seyhmus.cacina 0:ac4dea3e2894 199 // Application Processor Interface Related Variables
seyhmus.cacina 0:ac4dea3e2894 200 uint8_t i2cbuffer_[16];
seyhmus.cacina 0:ac4dea3e2894 201 uint8_t appdatainoutbuffer_[8];
seyhmus.cacina 0:ac4dea3e2894 202 uint8_t appcmdoutvalue_;
seyhmus.cacina 0:ac4dea3e2894 203
seyhmus.cacina 0:ac4dea3e2894 204
seyhmus.cacina 0:ac4dea3e2894 205 /** @brief API Related Functions ***/
seyhmus.cacina 0:ac4dea3e2894 206
seyhmus.cacina 0:ac4dea3e2894 207 /***
seyhmus.cacina 0:ac4dea3e2894 208 * @brief starts writing from ApResponse register 0x0F
seyhmus.cacina 0:ac4dea3e2894 209 * check the datasheet to determine the value of dataoutlen
seyhmus.cacina 0:ac4dea3e2894 210 */
seyhmus.cacina 0:ac4dea3e2894 211 int AppWrite(uint8_t dataoutlen);
seyhmus.cacina 0:ac4dea3e2894 212
seyhmus.cacina 0:ac4dea3e2894 213 /** @brief starts reading from ApResponse register 0x18
seyhmus.cacina 0:ac4dea3e2894 214 * check the datasheet to determine the value of datainlen
seyhmus.cacina 0:ac4dea3e2894 215 * the result values are written into i2cbuffer
seyhmus.cacina 0:ac4dea3e2894 216 *
seyhmus.cacina 0:ac4dea3e2894 217 */
seyhmus.cacina 0:ac4dea3e2894 218 int AppRead(uint8_t datainlen);
seyhmus.cacina 0:ac4dea3e2894 219 };
seyhmus.cacina 0:ac4dea3e2894 220
seyhmus.cacina 0:ac4dea3e2894 221 #endif /* __MAX20303_H_ */
seyhmus.cacina 0:ac4dea3e2894 222