YOSHIHISA TABUCHI / Mbed OS Host_Software_MAX32664GWEB_HR_EXTENDEDtest

test

Dependencies:   BMI160 max32630hsp3 MemoryLCD USBDevice

Drivers/USBDevice/USBDevice/USBHAL_STM32F4.cpp@0:ac4dea3e2894, 2019-03-18 (annotated)

Committer:
seyhmus.cacina
Date:
Mon Mar 18 10:21:53 2019 +0300
Revision:
0:ac4dea3e2894
ME11B Sample Code First Commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
seyhmus.cacina 0:ac4dea3e2894 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
seyhmus.cacina 0:ac4dea3e2894 2 *
seyhmus.cacina 0:ac4dea3e2894 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
seyhmus.cacina 0:ac4dea3e2894 4 * and associated documentation files (the "Software"), to deal in the Software without
seyhmus.cacina 0:ac4dea3e2894 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
seyhmus.cacina 0:ac4dea3e2894 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
seyhmus.cacina 0:ac4dea3e2894 7 * Software is furnished to do so, subject to the following conditions:
seyhmus.cacina 0:ac4dea3e2894 8 *
seyhmus.cacina 0:ac4dea3e2894 9 * The above copyright notice and this permission notice shall be included in all copies or
seyhmus.cacina 0:ac4dea3e2894 10 * substantial portions of the Software.
seyhmus.cacina 0:ac4dea3e2894 11 *
seyhmus.cacina 0:ac4dea3e2894 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
seyhmus.cacina 0:ac4dea3e2894 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
seyhmus.cacina 0:ac4dea3e2894 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
seyhmus.cacina 0:ac4dea3e2894 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
seyhmus.cacina 0:ac4dea3e2894 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
seyhmus.cacina 0:ac4dea3e2894 17 */
seyhmus.cacina 0:ac4dea3e2894 18
seyhmus.cacina 0:ac4dea3e2894 19 #if defined(TARGET_STM32F4)
seyhmus.cacina 0:ac4dea3e2894 20
seyhmus.cacina 0:ac4dea3e2894 21 #include "USBHAL.h"
seyhmus.cacina 0:ac4dea3e2894 22 #include "USBRegs_STM32.h"
seyhmus.cacina 0:ac4dea3e2894 23 #include "pinmap.h"
seyhmus.cacina 0:ac4dea3e2894 24
seyhmus.cacina 0:ac4dea3e2894 25 USBHAL * USBHAL::instance;
seyhmus.cacina 0:ac4dea3e2894 26
seyhmus.cacina 0:ac4dea3e2894 27 static volatile int epComplete = 0;
seyhmus.cacina 0:ac4dea3e2894 28
seyhmus.cacina 0:ac4dea3e2894 29 static uint32_t bufferEnd = 0;
seyhmus.cacina 0:ac4dea3e2894 30 static const uint32_t rxFifoSize = 512;
seyhmus.cacina 0:ac4dea3e2894 31 static uint32_t rxFifoCount = 0;
seyhmus.cacina 0:ac4dea3e2894 32
seyhmus.cacina 0:ac4dea3e2894 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
seyhmus.cacina 0:ac4dea3e2894 34
seyhmus.cacina 0:ac4dea3e2894 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 36 return 0;
seyhmus.cacina 0:ac4dea3e2894 37 }
seyhmus.cacina 0:ac4dea3e2894 38
seyhmus.cacina 0:ac4dea3e2894 39 USBHAL::USBHAL(void) {
seyhmus.cacina 0:ac4dea3e2894 40 NVIC_DisableIRQ(OTG_FS_IRQn);
seyhmus.cacina 0:ac4dea3e2894 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 42 epCallback[1] = &USBHAL::EP1_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 44 epCallback[3] = &USBHAL::EP2_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 46 epCallback[5] = &USBHAL::EP3_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 47
seyhmus.cacina 0:ac4dea3e2894 48 // Enable power and clocking
seyhmus.cacina 0:ac4dea3e2894 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
seyhmus.cacina 0:ac4dea3e2894 50
seyhmus.cacina 0:ac4dea3e2894 51 #if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F429ZI)
seyhmus.cacina 0:ac4dea3e2894 52 pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
seyhmus.cacina 0:ac4dea3e2894 53 pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
seyhmus.cacina 0:ac4dea3e2894 54 pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
seyhmus.cacina 0:ac4dea3e2894 55 pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
seyhmus.cacina 0:ac4dea3e2894 56 pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
seyhmus.cacina 0:ac4dea3e2894 57 #else
seyhmus.cacina 0:ac4dea3e2894 58 pin_function(PA_8, STM_PIN_DATA(2, 10));
seyhmus.cacina 0:ac4dea3e2894 59 pin_function(PA_9, STM_PIN_DATA(0, 0));
seyhmus.cacina 0:ac4dea3e2894 60 pin_function(PA_10, STM_PIN_DATA(2, 10));
seyhmus.cacina 0:ac4dea3e2894 61 pin_function(PA_11, STM_PIN_DATA(2, 10));
seyhmus.cacina 0:ac4dea3e2894 62 pin_function(PA_12, STM_PIN_DATA(2, 10));
seyhmus.cacina 0:ac4dea3e2894 63
seyhmus.cacina 0:ac4dea3e2894 64 // Set ID pin to open drain with pull-up resistor
seyhmus.cacina 0:ac4dea3e2894 65 pin_mode(PA_10, OpenDrain);
seyhmus.cacina 0:ac4dea3e2894 66 GPIOA->PUPDR &= ~(0x3 << 20);
seyhmus.cacina 0:ac4dea3e2894 67 GPIOA->PUPDR |= 1 << 20;
seyhmus.cacina 0:ac4dea3e2894 68
seyhmus.cacina 0:ac4dea3e2894 69 // Set VBUS pin to open drain
seyhmus.cacina 0:ac4dea3e2894 70 pin_mode(PA_9, OpenDrain);
seyhmus.cacina 0:ac4dea3e2894 71 #endif
seyhmus.cacina 0:ac4dea3e2894 72
seyhmus.cacina 0:ac4dea3e2894 73 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
seyhmus.cacina 0:ac4dea3e2894 74
seyhmus.cacina 0:ac4dea3e2894 75 // Enable interrupts
seyhmus.cacina 0:ac4dea3e2894 76 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
seyhmus.cacina 0:ac4dea3e2894 77
seyhmus.cacina 0:ac4dea3e2894 78 // Turnaround time to maximum value - too small causes packet loss
seyhmus.cacina 0:ac4dea3e2894 79 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
seyhmus.cacina 0:ac4dea3e2894 80
seyhmus.cacina 0:ac4dea3e2894 81 // Unmask global interrupts
seyhmus.cacina 0:ac4dea3e2894 82 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
seyhmus.cacina 0:ac4dea3e2894 83 (1 << 4) | // RX FIFO not empty
seyhmus.cacina 0:ac4dea3e2894 84 (1 << 12); // USB reset
seyhmus.cacina 0:ac4dea3e2894 85
seyhmus.cacina 0:ac4dea3e2894 86 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
seyhmus.cacina 0:ac4dea3e2894 87 (1 << 2); // Non-zero-length status OUT handshake
seyhmus.cacina 0:ac4dea3e2894 88
seyhmus.cacina 0:ac4dea3e2894 89 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
seyhmus.cacina 0:ac4dea3e2894 90 (1 << 16); // Power Up
seyhmus.cacina 0:ac4dea3e2894 91
seyhmus.cacina 0:ac4dea3e2894 92 instance = this;
seyhmus.cacina 0:ac4dea3e2894 93 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
seyhmus.cacina 0:ac4dea3e2894 94 NVIC_SetPriority(OTG_FS_IRQn, 1);
seyhmus.cacina 0:ac4dea3e2894 95 }
seyhmus.cacina 0:ac4dea3e2894 96
seyhmus.cacina 0:ac4dea3e2894 97 USBHAL::~USBHAL(void) {
seyhmus.cacina 0:ac4dea3e2894 98 }
seyhmus.cacina 0:ac4dea3e2894 99
seyhmus.cacina 0:ac4dea3e2894 100 void USBHAL::connect(void) {
seyhmus.cacina 0:ac4dea3e2894 101 NVIC_EnableIRQ(OTG_FS_IRQn);
seyhmus.cacina 0:ac4dea3e2894 102 }
seyhmus.cacina 0:ac4dea3e2894 103
seyhmus.cacina 0:ac4dea3e2894 104 void USBHAL::disconnect(void) {
seyhmus.cacina 0:ac4dea3e2894 105 NVIC_DisableIRQ(OTG_FS_IRQn);
seyhmus.cacina 0:ac4dea3e2894 106 }
seyhmus.cacina 0:ac4dea3e2894 107
seyhmus.cacina 0:ac4dea3e2894 108 void USBHAL::configureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 109 // Not needed
seyhmus.cacina 0:ac4dea3e2894 110 }
seyhmus.cacina 0:ac4dea3e2894 111
seyhmus.cacina 0:ac4dea3e2894 112 void USBHAL::unconfigureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 113 // Not needed
seyhmus.cacina 0:ac4dea3e2894 114 }
seyhmus.cacina 0:ac4dea3e2894 115
seyhmus.cacina 0:ac4dea3e2894 116 void USBHAL::setAddress(uint8_t address) {
seyhmus.cacina 0:ac4dea3e2894 117 OTG_FS->DREGS.DCFG |= (address << 4);
seyhmus.cacina 0:ac4dea3e2894 118 EP0write(0, 0);
seyhmus.cacina 0:ac4dea3e2894 119 }
seyhmus.cacina 0:ac4dea3e2894 120
seyhmus.cacina 0:ac4dea3e2894 121 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
seyhmus.cacina 0:ac4dea3e2894 122 uint32_t flags) {
seyhmus.cacina 0:ac4dea3e2894 123 uint32_t epIndex = endpoint >> 1;
seyhmus.cacina 0:ac4dea3e2894 124
seyhmus.cacina 0:ac4dea3e2894 125 uint32_t type;
seyhmus.cacina 0:ac4dea3e2894 126 switch (endpoint) {
seyhmus.cacina 0:ac4dea3e2894 127 case EP0IN:
seyhmus.cacina 0:ac4dea3e2894 128 case EP0OUT:
seyhmus.cacina 0:ac4dea3e2894 129 type = 0;
seyhmus.cacina 0:ac4dea3e2894 130 break;
seyhmus.cacina 0:ac4dea3e2894 131 case EPISO_IN:
seyhmus.cacina 0:ac4dea3e2894 132 case EPISO_OUT:
seyhmus.cacina 0:ac4dea3e2894 133 type = 1;
seyhmus.cacina 0:ac4dea3e2894 134 case EPBULK_IN:
seyhmus.cacina 0:ac4dea3e2894 135 case EPBULK_OUT:
seyhmus.cacina 0:ac4dea3e2894 136 type = 2;
seyhmus.cacina 0:ac4dea3e2894 137 break;
seyhmus.cacina 0:ac4dea3e2894 138 case EPINT_IN:
seyhmus.cacina 0:ac4dea3e2894 139 case EPINT_OUT:
seyhmus.cacina 0:ac4dea3e2894 140 type = 3;
seyhmus.cacina 0:ac4dea3e2894 141 break;
seyhmus.cacina 0:ac4dea3e2894 142 }
seyhmus.cacina 0:ac4dea3e2894 143
seyhmus.cacina 0:ac4dea3e2894 144 // Generic in or out EP controls
seyhmus.cacina 0:ac4dea3e2894 145 uint32_t control = (maxPacket << 0) | // Packet size
seyhmus.cacina 0:ac4dea3e2894 146 (1 << 15) | // Active endpoint
seyhmus.cacina 0:ac4dea3e2894 147 (type << 18); // Endpoint type
seyhmus.cacina 0:ac4dea3e2894 148
seyhmus.cacina 0:ac4dea3e2894 149 if (endpoint & 0x1) { // In Endpoint
seyhmus.cacina 0:ac4dea3e2894 150 // Set up the Tx FIFO
seyhmus.cacina 0:ac4dea3e2894 151 if (endpoint == EP0IN) {
seyhmus.cacina 0:ac4dea3e2894 152 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
seyhmus.cacina 0:ac4dea3e2894 153 (bufferEnd << 0);
seyhmus.cacina 0:ac4dea3e2894 154 }
seyhmus.cacina 0:ac4dea3e2894 155 else {
seyhmus.cacina 0:ac4dea3e2894 156 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
seyhmus.cacina 0:ac4dea3e2894 157 (bufferEnd << 0);
seyhmus.cacina 0:ac4dea3e2894 158 }
seyhmus.cacina 0:ac4dea3e2894 159 bufferEnd += maxPacket >> 2;
seyhmus.cacina 0:ac4dea3e2894 160
seyhmus.cacina 0:ac4dea3e2894 161 // Set the In EP specific control settings
seyhmus.cacina 0:ac4dea3e2894 162 if (endpoint != EP0IN) {
seyhmus.cacina 0:ac4dea3e2894 163 control |= (1 << 28); // SD0PID
seyhmus.cacina 0:ac4dea3e2894 164 }
seyhmus.cacina 0:ac4dea3e2894 165
seyhmus.cacina 0:ac4dea3e2894 166 control |= (epIndex << 22) | // TxFIFO index
seyhmus.cacina 0:ac4dea3e2894 167 (1 << 27); // SNAK
seyhmus.cacina 0:ac4dea3e2894 168 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
seyhmus.cacina 0:ac4dea3e2894 169
seyhmus.cacina 0:ac4dea3e2894 170 // Unmask the interrupt
seyhmus.cacina 0:ac4dea3e2894 171 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
seyhmus.cacina 0:ac4dea3e2894 172 }
seyhmus.cacina 0:ac4dea3e2894 173 else { // Out endpoint
seyhmus.cacina 0:ac4dea3e2894 174 // Set the out EP specific control settings
seyhmus.cacina 0:ac4dea3e2894 175 control |= (1 << 26); // CNAK
seyhmus.cacina 0:ac4dea3e2894 176 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
seyhmus.cacina 0:ac4dea3e2894 177
seyhmus.cacina 0:ac4dea3e2894 178 // Unmask the interrupt
seyhmus.cacina 0:ac4dea3e2894 179 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
seyhmus.cacina 0:ac4dea3e2894 180 }
seyhmus.cacina 0:ac4dea3e2894 181 return true;
seyhmus.cacina 0:ac4dea3e2894 182 }
seyhmus.cacina 0:ac4dea3e2894 183
seyhmus.cacina 0:ac4dea3e2894 184 // read setup packet
seyhmus.cacina 0:ac4dea3e2894 185 void USBHAL::EP0setup(uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 186 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
seyhmus.cacina 0:ac4dea3e2894 187 }
seyhmus.cacina 0:ac4dea3e2894 188
seyhmus.cacina 0:ac4dea3e2894 189 void USBHAL::EP0readStage(void) {
seyhmus.cacina 0:ac4dea3e2894 190 }
seyhmus.cacina 0:ac4dea3e2894 191
seyhmus.cacina 0:ac4dea3e2894 192 void USBHAL::EP0read(void) {
seyhmus.cacina 0:ac4dea3e2894 193 }
seyhmus.cacina 0:ac4dea3e2894 194
seyhmus.cacina 0:ac4dea3e2894 195 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 196 uint32_t* buffer32 = (uint32_t *) buffer;
seyhmus.cacina 0:ac4dea3e2894 197 uint32_t length = rxFifoCount;
seyhmus.cacina 0:ac4dea3e2894 198 for (uint32_t i = 0; i < length; i += 4) {
seyhmus.cacina 0:ac4dea3e2894 199 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
seyhmus.cacina 0:ac4dea3e2894 200 }
seyhmus.cacina 0:ac4dea3e2894 201
seyhmus.cacina 0:ac4dea3e2894 202 rxFifoCount = 0;
seyhmus.cacina 0:ac4dea3e2894 203 return length;
seyhmus.cacina 0:ac4dea3e2894 204 }
seyhmus.cacina 0:ac4dea3e2894 205
seyhmus.cacina 0:ac4dea3e2894 206 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 207 endpointWrite(0, buffer, size);
seyhmus.cacina 0:ac4dea3e2894 208 }
seyhmus.cacina 0:ac4dea3e2894 209
seyhmus.cacina 0:ac4dea3e2894 210 void USBHAL::EP0getWriteResult(void) {
seyhmus.cacina 0:ac4dea3e2894 211 }
seyhmus.cacina 0:ac4dea3e2894 212
seyhmus.cacina 0:ac4dea3e2894 213 void USBHAL::EP0stall(void) {
seyhmus.cacina 0:ac4dea3e2894 214 // If we stall the out endpoint here then we have problems transferring
seyhmus.cacina 0:ac4dea3e2894 215 // and setup requests after the (stalled) get device qualifier requests.
seyhmus.cacina 0:ac4dea3e2894 216 // TODO: Find out if this is correct behavior, or whether we are doing
seyhmus.cacina 0:ac4dea3e2894 217 // something else wrong
seyhmus.cacina 0:ac4dea3e2894 218 stallEndpoint(EP0IN);
seyhmus.cacina 0:ac4dea3e2894 219 // stallEndpoint(EP0OUT);
seyhmus.cacina 0:ac4dea3e2894 220 }
seyhmus.cacina 0:ac4dea3e2894 221
seyhmus.cacina 0:ac4dea3e2894 222 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
seyhmus.cacina 0:ac4dea3e2894 223 uint32_t epIndex = endpoint >> 1;
seyhmus.cacina 0:ac4dea3e2894 224 uint32_t size = (1 << 19) | // 1 packet
seyhmus.cacina 0:ac4dea3e2894 225 (maximumSize << 0); // Packet size
seyhmus.cacina 0:ac4dea3e2894 226 // if (endpoint == EP0OUT) {
seyhmus.cacina 0:ac4dea3e2894 227 size |= (1 << 29); // 1 setup packet
seyhmus.cacina 0:ac4dea3e2894 228 // }
seyhmus.cacina 0:ac4dea3e2894 229 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
seyhmus.cacina 0:ac4dea3e2894 230 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
seyhmus.cacina 0:ac4dea3e2894 231 (1 << 26); // Clear NAK
seyhmus.cacina 0:ac4dea3e2894 232
seyhmus.cacina 0:ac4dea3e2894 233 epComplete &= ~(1 << endpoint);
seyhmus.cacina 0:ac4dea3e2894 234 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 235 }
seyhmus.cacina 0:ac4dea3e2894 236
seyhmus.cacina 0:ac4dea3e2894 237 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
seyhmus.cacina 0:ac4dea3e2894 238 if (!(epComplete & (1 << endpoint))) {
seyhmus.cacina 0:ac4dea3e2894 239 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 240 }
seyhmus.cacina 0:ac4dea3e2894 241
seyhmus.cacina 0:ac4dea3e2894 242 uint32_t* buffer32 = (uint32_t *) buffer;
seyhmus.cacina 0:ac4dea3e2894 243 uint32_t length = rxFifoCount;
seyhmus.cacina 0:ac4dea3e2894 244 for (uint32_t i = 0; i < length; i += 4) {
seyhmus.cacina 0:ac4dea3e2894 245 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
seyhmus.cacina 0:ac4dea3e2894 246 }
seyhmus.cacina 0:ac4dea3e2894 247 rxFifoCount = 0;
seyhmus.cacina 0:ac4dea3e2894 248 *bytesRead = length;
seyhmus.cacina 0:ac4dea3e2894 249 return EP_COMPLETED;
seyhmus.cacina 0:ac4dea3e2894 250 }
seyhmus.cacina 0:ac4dea3e2894 251
seyhmus.cacina 0:ac4dea3e2894 252 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 253 uint32_t epIndex = endpoint >> 1;
seyhmus.cacina 0:ac4dea3e2894 254 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
seyhmus.cacina 0:ac4dea3e2894 255 (size << 0); // Size of packet
seyhmus.cacina 0:ac4dea3e2894 256 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
seyhmus.cacina 0:ac4dea3e2894 257 (1 << 26); // CNAK
seyhmus.cacina 0:ac4dea3e2894 258 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
seyhmus.cacina 0:ac4dea3e2894 259
seyhmus.cacina 0:ac4dea3e2894 260 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
seyhmus.cacina 0:ac4dea3e2894 261
seyhmus.cacina 0:ac4dea3e2894 262 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
seyhmus.cacina 0:ac4dea3e2894 263 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
seyhmus.cacina 0:ac4dea3e2894 264 }
seyhmus.cacina 0:ac4dea3e2894 265
seyhmus.cacina 0:ac4dea3e2894 266 epComplete &= ~(1 << endpoint);
seyhmus.cacina 0:ac4dea3e2894 267
seyhmus.cacina 0:ac4dea3e2894 268 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 269 }
seyhmus.cacina 0:ac4dea3e2894 270
seyhmus.cacina 0:ac4dea3e2894 271 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 272 if (epComplete & (1 << endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 273 epComplete &= ~(1 << endpoint);
seyhmus.cacina 0:ac4dea3e2894 274 return EP_COMPLETED;
seyhmus.cacina 0:ac4dea3e2894 275 }
seyhmus.cacina 0:ac4dea3e2894 276
seyhmus.cacina 0:ac4dea3e2894 277 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 278 }
seyhmus.cacina 0:ac4dea3e2894 279
seyhmus.cacina 0:ac4dea3e2894 280 void USBHAL::stallEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 281 if (endpoint & 0x1) { // In EP
seyhmus.cacina 0:ac4dea3e2894 282 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
seyhmus.cacina 0:ac4dea3e2894 283 (1 << 21); // Stall
seyhmus.cacina 0:ac4dea3e2894 284 }
seyhmus.cacina 0:ac4dea3e2894 285 else { // Out EP
seyhmus.cacina 0:ac4dea3e2894 286 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
seyhmus.cacina 0:ac4dea3e2894 287 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
seyhmus.cacina 0:ac4dea3e2894 288 (1 << 21); // Stall
seyhmus.cacina 0:ac4dea3e2894 289 }
seyhmus.cacina 0:ac4dea3e2894 290 }
seyhmus.cacina 0:ac4dea3e2894 291
seyhmus.cacina 0:ac4dea3e2894 292 void USBHAL::unstallEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 293
seyhmus.cacina 0:ac4dea3e2894 294 }
seyhmus.cacina 0:ac4dea3e2894 295
seyhmus.cacina 0:ac4dea3e2894 296 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 297 return false;
seyhmus.cacina 0:ac4dea3e2894 298 }
seyhmus.cacina 0:ac4dea3e2894 299
seyhmus.cacina 0:ac4dea3e2894 300 void USBHAL::remoteWakeup(void) {
seyhmus.cacina 0:ac4dea3e2894 301 }
seyhmus.cacina 0:ac4dea3e2894 302
seyhmus.cacina 0:ac4dea3e2894 303
seyhmus.cacina 0:ac4dea3e2894 304 void USBHAL::_usbisr(void) {
seyhmus.cacina 0:ac4dea3e2894 305 instance->usbisr();
seyhmus.cacina 0:ac4dea3e2894 306 }
seyhmus.cacina 0:ac4dea3e2894 307
seyhmus.cacina 0:ac4dea3e2894 308
seyhmus.cacina 0:ac4dea3e2894 309 void USBHAL::usbisr(void) {
seyhmus.cacina 0:ac4dea3e2894 310 if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend
seyhmus.cacina 0:ac4dea3e2894 311 suspendStateChanged(1);
seyhmus.cacina 0:ac4dea3e2894 312 };
seyhmus.cacina 0:ac4dea3e2894 313
seyhmus.cacina 0:ac4dea3e2894 314 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
seyhmus.cacina 0:ac4dea3e2894 315 suspendStateChanged(0);
seyhmus.cacina 0:ac4dea3e2894 316
seyhmus.cacina 0:ac4dea3e2894 317 // Set SNAK bits
seyhmus.cacina 0:ac4dea3e2894 318 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
seyhmus.cacina 0:ac4dea3e2894 319 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
seyhmus.cacina 0:ac4dea3e2894 320 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
seyhmus.cacina 0:ac4dea3e2894 321 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
seyhmus.cacina 0:ac4dea3e2894 322
seyhmus.cacina 0:ac4dea3e2894 323 OTG_FS->DREGS.DIEPMSK = (1 << 0);
seyhmus.cacina 0:ac4dea3e2894 324
seyhmus.cacina 0:ac4dea3e2894 325 bufferEnd = 0;
seyhmus.cacina 0:ac4dea3e2894 326
seyhmus.cacina 0:ac4dea3e2894 327 // Set the receive FIFO size
seyhmus.cacina 0:ac4dea3e2894 328 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
seyhmus.cacina 0:ac4dea3e2894 329 bufferEnd += rxFifoSize >> 2;
seyhmus.cacina 0:ac4dea3e2894 330
seyhmus.cacina 0:ac4dea3e2894 331 // Create the endpoints, and wait for setup packets on out EP0
seyhmus.cacina 0:ac4dea3e2894 332 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
seyhmus.cacina 0:ac4dea3e2894 333 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
seyhmus.cacina 0:ac4dea3e2894 334 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
seyhmus.cacina 0:ac4dea3e2894 335
seyhmus.cacina 0:ac4dea3e2894 336 OTG_FS->GREGS.GINTSTS = (1 << 12);
seyhmus.cacina 0:ac4dea3e2894 337 }
seyhmus.cacina 0:ac4dea3e2894 338
seyhmus.cacina 0:ac4dea3e2894 339 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
seyhmus.cacina 0:ac4dea3e2894 340 uint32_t status = OTG_FS->GREGS.GRXSTSP;
seyhmus.cacina 0:ac4dea3e2894 341
seyhmus.cacina 0:ac4dea3e2894 342 uint32_t endpoint = (status & 0xF) << 1;
seyhmus.cacina 0:ac4dea3e2894 343 uint32_t length = (status >> 4) & 0x7FF;
seyhmus.cacina 0:ac4dea3e2894 344 uint32_t type = (status >> 17) & 0xF;
seyhmus.cacina 0:ac4dea3e2894 345
seyhmus.cacina 0:ac4dea3e2894 346 rxFifoCount = length;
seyhmus.cacina 0:ac4dea3e2894 347
seyhmus.cacina 0:ac4dea3e2894 348 if (type == 0x6) {
seyhmus.cacina 0:ac4dea3e2894 349 // Setup packet
seyhmus.cacina 0:ac4dea3e2894 350 for (uint32_t i=0; i<length; i+=4) {
seyhmus.cacina 0:ac4dea3e2894 351 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
seyhmus.cacina 0:ac4dea3e2894 352 }
seyhmus.cacina 0:ac4dea3e2894 353 rxFifoCount = 0;
seyhmus.cacina 0:ac4dea3e2894 354 }
seyhmus.cacina 0:ac4dea3e2894 355
seyhmus.cacina 0:ac4dea3e2894 356 if (type == 0x4) {
seyhmus.cacina 0:ac4dea3e2894 357 // Setup complete
seyhmus.cacina 0:ac4dea3e2894 358 EP0setupCallback();
seyhmus.cacina 0:ac4dea3e2894 359 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
seyhmus.cacina 0:ac4dea3e2894 360 }
seyhmus.cacina 0:ac4dea3e2894 361
seyhmus.cacina 0:ac4dea3e2894 362 if (type == 0x2) {
seyhmus.cacina 0:ac4dea3e2894 363 // Out packet
seyhmus.cacina 0:ac4dea3e2894 364 if (endpoint == EP0OUT) {
seyhmus.cacina 0:ac4dea3e2894 365 EP0out();
seyhmus.cacina 0:ac4dea3e2894 366 }
seyhmus.cacina 0:ac4dea3e2894 367 else {
seyhmus.cacina 0:ac4dea3e2894 368 epComplete |= (1 << endpoint);
seyhmus.cacina 0:ac4dea3e2894 369 if ((instance->*(epCallback[endpoint - 2]))()) {
seyhmus.cacina 0:ac4dea3e2894 370 epComplete &= (1 << endpoint);
seyhmus.cacina 0:ac4dea3e2894 371 }
seyhmus.cacina 0:ac4dea3e2894 372 }
seyhmus.cacina 0:ac4dea3e2894 373 }
seyhmus.cacina 0:ac4dea3e2894 374
seyhmus.cacina 0:ac4dea3e2894 375 for (uint32_t i=0; i<rxFifoCount; i+=4) {
seyhmus.cacina 0:ac4dea3e2894 376 (void) OTG_FS->FIFO[0][0];
seyhmus.cacina 0:ac4dea3e2894 377 }
seyhmus.cacina 0:ac4dea3e2894 378 OTG_FS->GREGS.GINTSTS = (1 << 4);
seyhmus.cacina 0:ac4dea3e2894 379 }
seyhmus.cacina 0:ac4dea3e2894 380
seyhmus.cacina 0:ac4dea3e2894 381 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
seyhmus.cacina 0:ac4dea3e2894 382 // Loop through the in endpoints
seyhmus.cacina 0:ac4dea3e2894 383 for (uint32_t i=0; i<4; i++) {
seyhmus.cacina 0:ac4dea3e2894 384 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
seyhmus.cacina 0:ac4dea3e2894 385
seyhmus.cacina 0:ac4dea3e2894 386 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
seyhmus.cacina 0:ac4dea3e2894 387 // If the Tx FIFO is empty on EP0 we need to send a further
seyhmus.cacina 0:ac4dea3e2894 388 // packet, so call EP0in()
seyhmus.cacina 0:ac4dea3e2894 389 if (i == 0) {
seyhmus.cacina 0:ac4dea3e2894 390 EP0in();
seyhmus.cacina 0:ac4dea3e2894 391 }
seyhmus.cacina 0:ac4dea3e2894 392 // Clear the interrupt
seyhmus.cacina 0:ac4dea3e2894 393 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
seyhmus.cacina 0:ac4dea3e2894 394 // Stop firing Tx empty interrupts
seyhmus.cacina 0:ac4dea3e2894 395 // Will get turned on again if another write is called
seyhmus.cacina 0:ac4dea3e2894 396 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
seyhmus.cacina 0:ac4dea3e2894 397 }
seyhmus.cacina 0:ac4dea3e2894 398
seyhmus.cacina 0:ac4dea3e2894 399 // If the transfer is complete
seyhmus.cacina 0:ac4dea3e2894 400 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
seyhmus.cacina 0:ac4dea3e2894 401 epComplete |= (1 << (1 + (i << 1)));
seyhmus.cacina 0:ac4dea3e2894 402 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
seyhmus.cacina 0:ac4dea3e2894 403 }
seyhmus.cacina 0:ac4dea3e2894 404 }
seyhmus.cacina 0:ac4dea3e2894 405 }
seyhmus.cacina 0:ac4dea3e2894 406 OTG_FS->GREGS.GINTSTS = (1 << 18);
seyhmus.cacina 0:ac4dea3e2894 407 }
seyhmus.cacina 0:ac4dea3e2894 408
seyhmus.cacina 0:ac4dea3e2894 409 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
seyhmus.cacina 0:ac4dea3e2894 410 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
seyhmus.cacina 0:ac4dea3e2894 411 OTG_FS->GREGS.GINTSTS = (1 << 3);
seyhmus.cacina 0:ac4dea3e2894 412 }
seyhmus.cacina 0:ac4dea3e2894 413 }
seyhmus.cacina 0:ac4dea3e2894 414
seyhmus.cacina 0:ac4dea3e2894 415
seyhmus.cacina 0:ac4dea3e2894 416 #endif