YOSHIHISA TABUCHI / Mbed OS Host_Software_MAX32664GWEB_HR_EXTENDEDtest

test

Dependencies:   BMI160 max32630hsp3 MemoryLCD USBDevice

Drivers/USBDevice/USBDevice/USBHAL_LPC11U.cpp@0:ac4dea3e2894, 2019-03-18 (annotated)

Committer:
seyhmus.cacina
Date:
Mon Mar 18 10:21:53 2019 +0300
Revision:
0:ac4dea3e2894
ME11B Sample Code First Commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
seyhmus.cacina 0:ac4dea3e2894 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
seyhmus.cacina 0:ac4dea3e2894 2 *
seyhmus.cacina 0:ac4dea3e2894 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
seyhmus.cacina 0:ac4dea3e2894 4 * and associated documentation files (the "Software"), to deal in the Software without
seyhmus.cacina 0:ac4dea3e2894 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
seyhmus.cacina 0:ac4dea3e2894 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
seyhmus.cacina 0:ac4dea3e2894 7 * Software is furnished to do so, subject to the following conditions:
seyhmus.cacina 0:ac4dea3e2894 8 *
seyhmus.cacina 0:ac4dea3e2894 9 * The above copyright notice and this permission notice shall be included in all copies or
seyhmus.cacina 0:ac4dea3e2894 10 * substantial portions of the Software.
seyhmus.cacina 0:ac4dea3e2894 11 *
seyhmus.cacina 0:ac4dea3e2894 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
seyhmus.cacina 0:ac4dea3e2894 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
seyhmus.cacina 0:ac4dea3e2894 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
seyhmus.cacina 0:ac4dea3e2894 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
seyhmus.cacina 0:ac4dea3e2894 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
seyhmus.cacina 0:ac4dea3e2894 17 */
seyhmus.cacina 0:ac4dea3e2894 18
seyhmus.cacina 0:ac4dea3e2894 19 #if defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
seyhmus.cacina 0:ac4dea3e2894 20
seyhmus.cacina 0:ac4dea3e2894 21 #if defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
seyhmus.cacina 0:ac4dea3e2894 22 #define USB_IRQ USB_IRQ_IRQn
seyhmus.cacina 0:ac4dea3e2894 23 #else
seyhmus.cacina 0:ac4dea3e2894 24 #define USB_IRQ USB_IRQn
seyhmus.cacina 0:ac4dea3e2894 25 #endif
seyhmus.cacina 0:ac4dea3e2894 26
seyhmus.cacina 0:ac4dea3e2894 27 #include "USBHAL.h"
seyhmus.cacina 0:ac4dea3e2894 28
seyhmus.cacina 0:ac4dea3e2894 29 USBHAL * USBHAL::instance;
seyhmus.cacina 0:ac4dea3e2894 30 #if defined(TARGET_LPC1549)
seyhmus.cacina 0:ac4dea3e2894 31 static uint8_t usbmem[2048] __attribute__((aligned(2048)));
seyhmus.cacina 0:ac4dea3e2894 32 #endif
seyhmus.cacina 0:ac4dea3e2894 33
seyhmus.cacina 0:ac4dea3e2894 34 // Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
seyhmus.cacina 0:ac4dea3e2894 35 #define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
seyhmus.cacina 0:ac4dea3e2894 36
seyhmus.cacina 0:ac4dea3e2894 37 // Convert physical endpoint number to register bit
seyhmus.cacina 0:ac4dea3e2894 38 #define EP(endpoint) (1UL<<endpoint)
seyhmus.cacina 0:ac4dea3e2894 39
seyhmus.cacina 0:ac4dea3e2894 40 // Convert physical to logical
seyhmus.cacina 0:ac4dea3e2894 41 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
seyhmus.cacina 0:ac4dea3e2894 42
seyhmus.cacina 0:ac4dea3e2894 43 // Get endpoint direction
seyhmus.cacina 0:ac4dea3e2894 44 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
seyhmus.cacina 0:ac4dea3e2894 45 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
seyhmus.cacina 0:ac4dea3e2894 46
seyhmus.cacina 0:ac4dea3e2894 47 // USB RAM
seyhmus.cacina 0:ac4dea3e2894 48 #if defined(TARGET_LPC1549)
seyhmus.cacina 0:ac4dea3e2894 49 #define USB_RAM_START ((uint32_t)usbmem)
seyhmus.cacina 0:ac4dea3e2894 50 #define USB_RAM_SIZE sizeof(usbmem)
seyhmus.cacina 0:ac4dea3e2894 51 #else
seyhmus.cacina 0:ac4dea3e2894 52 #define USB_RAM_START (0x20004000)
seyhmus.cacina 0:ac4dea3e2894 53 #define USB_RAM_SIZE (0x00000800)
seyhmus.cacina 0:ac4dea3e2894 54 #endif
seyhmus.cacina 0:ac4dea3e2894 55
seyhmus.cacina 0:ac4dea3e2894 56 // SYSAHBCLKCTRL
seyhmus.cacina 0:ac4dea3e2894 57 #if defined(TARGET_LPC1549)
seyhmus.cacina 0:ac4dea3e2894 58 #define CLK_USB (1UL<<23)
seyhmus.cacina 0:ac4dea3e2894 59 #else
seyhmus.cacina 0:ac4dea3e2894 60 #define CLK_USB (1UL<<14)
seyhmus.cacina 0:ac4dea3e2894 61 #define CLK_USBRAM (1UL<<27)
seyhmus.cacina 0:ac4dea3e2894 62 #endif
seyhmus.cacina 0:ac4dea3e2894 63
seyhmus.cacina 0:ac4dea3e2894 64 // USB Information register
seyhmus.cacina 0:ac4dea3e2894 65 #define FRAME_NR(a) ((a) & 0x7ff) // Frame number
seyhmus.cacina 0:ac4dea3e2894 66
seyhmus.cacina 0:ac4dea3e2894 67 // USB Device Command/Status register
seyhmus.cacina 0:ac4dea3e2894 68 #define DEV_ADDR_MASK (0x7f) // Device address
seyhmus.cacina 0:ac4dea3e2894 69 #define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
seyhmus.cacina 0:ac4dea3e2894 70 #define DEV_EN (1UL<<7) // Device enable
seyhmus.cacina 0:ac4dea3e2894 71 #define SETUP (1UL<<8) // SETUP token received
seyhmus.cacina 0:ac4dea3e2894 72 #define PLL_ON (1UL<<9) // PLL enabled in suspend
seyhmus.cacina 0:ac4dea3e2894 73 #define DCON (1UL<<16) // Device status - connect
seyhmus.cacina 0:ac4dea3e2894 74 #define DSUS (1UL<<17) // Device status - suspend
seyhmus.cacina 0:ac4dea3e2894 75 #define DCON_C (1UL<<24) // Connect change
seyhmus.cacina 0:ac4dea3e2894 76 #define DSUS_C (1UL<<25) // Suspend change
seyhmus.cacina 0:ac4dea3e2894 77 #define DRES_C (1UL<<26) // Reset change
seyhmus.cacina 0:ac4dea3e2894 78 #define VBUSDEBOUNCED (1UL<<28) // Vbus detected
seyhmus.cacina 0:ac4dea3e2894 79
seyhmus.cacina 0:ac4dea3e2894 80 // Endpoint Command/Status list
seyhmus.cacina 0:ac4dea3e2894 81 #define CMDSTS_A (1UL<<31) // Active
seyhmus.cacina 0:ac4dea3e2894 82 #define CMDSTS_D (1UL<<30) // Disable
seyhmus.cacina 0:ac4dea3e2894 83 #define CMDSTS_S (1UL<<29) // Stall
seyhmus.cacina 0:ac4dea3e2894 84 #define CMDSTS_TR (1UL<<28) // Toggle Reset
seyhmus.cacina 0:ac4dea3e2894 85 #define CMDSTS_RF (1UL<<27) // Rate Feedback mode
seyhmus.cacina 0:ac4dea3e2894 86 #define CMDSTS_TV (1UL<<27) // Toggle Value
seyhmus.cacina 0:ac4dea3e2894 87 #define CMDSTS_T (1UL<<26) // Endpoint Type
seyhmus.cacina 0:ac4dea3e2894 88 #define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
seyhmus.cacina 0:ac4dea3e2894 89 #define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
seyhmus.cacina 0:ac4dea3e2894 90
seyhmus.cacina 0:ac4dea3e2894 91 #define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
seyhmus.cacina 0:ac4dea3e2894 92
seyhmus.cacina 0:ac4dea3e2894 93 // USB Non-endpoint interrupt sources
seyhmus.cacina 0:ac4dea3e2894 94 #define FRAME_INT (1UL<<30)
seyhmus.cacina 0:ac4dea3e2894 95 #define DEV_INT (1UL<<31)
seyhmus.cacina 0:ac4dea3e2894 96
seyhmus.cacina 0:ac4dea3e2894 97 static volatile int epComplete = 0;
seyhmus.cacina 0:ac4dea3e2894 98
seyhmus.cacina 0:ac4dea3e2894 99 // One entry for a double-buffered logical endpoint in the endpoint
seyhmus.cacina 0:ac4dea3e2894 100 // command/status list. Endpoint 0 is single buffered, out[1] is used
seyhmus.cacina 0:ac4dea3e2894 101 // for the SETUP packet and in[1] is not used
seyhmus.cacina 0:ac4dea3e2894 102 typedef struct {
seyhmus.cacina 0:ac4dea3e2894 103 uint32_t out[2];
seyhmus.cacina 0:ac4dea3e2894 104 uint32_t in[2];
seyhmus.cacina 0:ac4dea3e2894 105 } PACKED EP_COMMAND_STATUS;
seyhmus.cacina 0:ac4dea3e2894 106
seyhmus.cacina 0:ac4dea3e2894 107 typedef struct {
seyhmus.cacina 0:ac4dea3e2894 108 uint8_t out[MAX_PACKET_SIZE_EP0];
seyhmus.cacina 0:ac4dea3e2894 109 uint8_t in[MAX_PACKET_SIZE_EP0];
seyhmus.cacina 0:ac4dea3e2894 110 uint8_t setup[SETUP_PACKET_SIZE];
seyhmus.cacina 0:ac4dea3e2894 111 } PACKED CONTROL_TRANSFER;
seyhmus.cacina 0:ac4dea3e2894 112
seyhmus.cacina 0:ac4dea3e2894 113 typedef struct {
seyhmus.cacina 0:ac4dea3e2894 114 uint32_t maxPacket;
seyhmus.cacina 0:ac4dea3e2894 115 uint32_t buffer[2];
seyhmus.cacina 0:ac4dea3e2894 116 uint32_t options;
seyhmus.cacina 0:ac4dea3e2894 117 } PACKED EP_STATE;
seyhmus.cacina 0:ac4dea3e2894 118
seyhmus.cacina 0:ac4dea3e2894 119 static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
seyhmus.cacina 0:ac4dea3e2894 120
seyhmus.cacina 0:ac4dea3e2894 121 // Pointer to the endpoint command/status list
seyhmus.cacina 0:ac4dea3e2894 122 static EP_COMMAND_STATUS *ep = NULL;
seyhmus.cacina 0:ac4dea3e2894 123
seyhmus.cacina 0:ac4dea3e2894 124 // Pointer to endpoint 0 data (IN/OUT and SETUP)
seyhmus.cacina 0:ac4dea3e2894 125 static CONTROL_TRANSFER *ct = NULL;
seyhmus.cacina 0:ac4dea3e2894 126
seyhmus.cacina 0:ac4dea3e2894 127 // Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
seyhmus.cacina 0:ac4dea3e2894 128 // initiating a remote wakeup event.
seyhmus.cacina 0:ac4dea3e2894 129 static volatile uint32_t devCmdStat;
seyhmus.cacina 0:ac4dea3e2894 130
seyhmus.cacina 0:ac4dea3e2894 131 // Pointers used to allocate USB RAM
seyhmus.cacina 0:ac4dea3e2894 132 static uint32_t usbRamPtr = USB_RAM_START;
seyhmus.cacina 0:ac4dea3e2894 133 static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
seyhmus.cacina 0:ac4dea3e2894 134
seyhmus.cacina 0:ac4dea3e2894 135 #define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
seyhmus.cacina 0:ac4dea3e2894 136
seyhmus.cacina 0:ac4dea3e2894 137 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
seyhmus.cacina 0:ac4dea3e2894 138 void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 139 if (size > 0) {
seyhmus.cacina 0:ac4dea3e2894 140 do {
seyhmus.cacina 0:ac4dea3e2894 141 *dst++ = *src++;
seyhmus.cacina 0:ac4dea3e2894 142 } while (--size > 0);
seyhmus.cacina 0:ac4dea3e2894 143 }
seyhmus.cacina 0:ac4dea3e2894 144 }
seyhmus.cacina 0:ac4dea3e2894 145
seyhmus.cacina 0:ac4dea3e2894 146
seyhmus.cacina 0:ac4dea3e2894 147 USBHAL::USBHAL(void) {
seyhmus.cacina 0:ac4dea3e2894 148 NVIC_DisableIRQ(USB_IRQ);
seyhmus.cacina 0:ac4dea3e2894 149
seyhmus.cacina 0:ac4dea3e2894 150 // fill in callback array
seyhmus.cacina 0:ac4dea3e2894 151 epCallback[0] = &USBHAL::EP1_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 152 epCallback[1] = &USBHAL::EP1_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 153 epCallback[2] = &USBHAL::EP2_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 154 epCallback[3] = &USBHAL::EP2_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 155 epCallback[4] = &USBHAL::EP3_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 156 epCallback[5] = &USBHAL::EP3_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 157 epCallback[6] = &USBHAL::EP4_OUT_callback;
seyhmus.cacina 0:ac4dea3e2894 158 epCallback[7] = &USBHAL::EP4_IN_callback;
seyhmus.cacina 0:ac4dea3e2894 159
seyhmus.cacina 0:ac4dea3e2894 160 #if defined(TARGET_LPC1549)
seyhmus.cacina 0:ac4dea3e2894 161 /* Set USB PLL input to system oscillator */
seyhmus.cacina 0:ac4dea3e2894 162 LPC_SYSCON->USBPLLCLKSEL = 0x01;
seyhmus.cacina 0:ac4dea3e2894 163
seyhmus.cacina 0:ac4dea3e2894 164 /* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
seyhmus.cacina 0:ac4dea3e2894 165 MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
seyhmus.cacina 0:ac4dea3e2894 166 FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
seyhmus.cacina 0:ac4dea3e2894 167 FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
seyhmus.cacina 0:ac4dea3e2894 168 LPC_SYSCON->USBPLLCTRL = (0x3 | (1UL << 6));
seyhmus.cacina 0:ac4dea3e2894 169
seyhmus.cacina 0:ac4dea3e2894 170 /* Powerup USB PLL */
seyhmus.cacina 0:ac4dea3e2894 171 LPC_SYSCON->PDRUNCFG &= ~(CLK_USB);
seyhmus.cacina 0:ac4dea3e2894 172
seyhmus.cacina 0:ac4dea3e2894 173 /* Wait for PLL to lock */
seyhmus.cacina 0:ac4dea3e2894 174 while(!(LPC_SYSCON->USBPLLSTAT & 0x01));
seyhmus.cacina 0:ac4dea3e2894 175
seyhmus.cacina 0:ac4dea3e2894 176 /* enable USB main clock */
seyhmus.cacina 0:ac4dea3e2894 177 LPC_SYSCON->USBCLKSEL = 0x02;
seyhmus.cacina 0:ac4dea3e2894 178 LPC_SYSCON->USBCLKDIV = 1;
seyhmus.cacina 0:ac4dea3e2894 179
seyhmus.cacina 0:ac4dea3e2894 180 /* Enable AHB clock to the USB block. */
seyhmus.cacina 0:ac4dea3e2894 181 LPC_SYSCON->SYSAHBCLKCTRL1 |= CLK_USB;
seyhmus.cacina 0:ac4dea3e2894 182
seyhmus.cacina 0:ac4dea3e2894 183 /* power UP USB Phy */
seyhmus.cacina 0:ac4dea3e2894 184 LPC_SYSCON->PDRUNCFG &= ~(1UL << 9);
seyhmus.cacina 0:ac4dea3e2894 185
seyhmus.cacina 0:ac4dea3e2894 186 /* Reset USB block */
seyhmus.cacina 0:ac4dea3e2894 187 LPC_SYSCON->PRESETCTRL1 |= (CLK_USB);
seyhmus.cacina 0:ac4dea3e2894 188 LPC_SYSCON->PRESETCTRL1 &= ~(CLK_USB);
seyhmus.cacina 0:ac4dea3e2894 189
seyhmus.cacina 0:ac4dea3e2894 190 #else
seyhmus.cacina 0:ac4dea3e2894 191 #if defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501)
seyhmus.cacina 0:ac4dea3e2894 192 // USB_VBUS input with pull-down
seyhmus.cacina 0:ac4dea3e2894 193 LPC_IOCON->PIO0_3 = 0x00000009;
seyhmus.cacina 0:ac4dea3e2894 194 #endif
seyhmus.cacina 0:ac4dea3e2894 195
seyhmus.cacina 0:ac4dea3e2894 196 // nUSB_CONNECT output
seyhmus.cacina 0:ac4dea3e2894 197 LPC_IOCON->PIO0_6 = 0x00000001;
seyhmus.cacina 0:ac4dea3e2894 198
seyhmus.cacina 0:ac4dea3e2894 199 // Enable clocks (USB registers, USB RAM)
seyhmus.cacina 0:ac4dea3e2894 200 LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
seyhmus.cacina 0:ac4dea3e2894 201
seyhmus.cacina 0:ac4dea3e2894 202 // Ensure device disconnected (DCON not set)
seyhmus.cacina 0:ac4dea3e2894 203 LPC_USB->DEVCMDSTAT = 0;
seyhmus.cacina 0:ac4dea3e2894 204 #endif
seyhmus.cacina 0:ac4dea3e2894 205 // to ensure that the USB host sees the device as
seyhmus.cacina 0:ac4dea3e2894 206 // disconnected if the target CPU is reset.
seyhmus.cacina 0:ac4dea3e2894 207 wait(0.3);
seyhmus.cacina 0:ac4dea3e2894 208
seyhmus.cacina 0:ac4dea3e2894 209 // Reserve space in USB RAM for endpoint command/status list
seyhmus.cacina 0:ac4dea3e2894 210 // Must be 256 byte aligned
seyhmus.cacina 0:ac4dea3e2894 211 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
seyhmus.cacina 0:ac4dea3e2894 212 ep = (EP_COMMAND_STATUS *)usbRamPtr;
seyhmus.cacina 0:ac4dea3e2894 213 usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
seyhmus.cacina 0:ac4dea3e2894 214 LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
seyhmus.cacina 0:ac4dea3e2894 215
seyhmus.cacina 0:ac4dea3e2894 216 // Reserve space in USB RAM for Endpoint 0
seyhmus.cacina 0:ac4dea3e2894 217 // Must be 64 byte aligned
seyhmus.cacina 0:ac4dea3e2894 218 usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
seyhmus.cacina 0:ac4dea3e2894 219 ct = (CONTROL_TRANSFER *)usbRamPtr;
seyhmus.cacina 0:ac4dea3e2894 220 usbRamPtr += sizeof(CONTROL_TRANSFER);
seyhmus.cacina 0:ac4dea3e2894 221 LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
seyhmus.cacina 0:ac4dea3e2894 222
seyhmus.cacina 0:ac4dea3e2894 223 // Setup command/status list for EP0
seyhmus.cacina 0:ac4dea3e2894 224 ep[0].out[0] = 0;
seyhmus.cacina 0:ac4dea3e2894 225 ep[0].in[0] = 0;
seyhmus.cacina 0:ac4dea3e2894 226 ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
seyhmus.cacina 0:ac4dea3e2894 227
seyhmus.cacina 0:ac4dea3e2894 228 // Route all interrupts to IRQ, some can be routed to
seyhmus.cacina 0:ac4dea3e2894 229 // USB_FIQ if you wish.
seyhmus.cacina 0:ac4dea3e2894 230 LPC_USB->INTROUTING = 0;
seyhmus.cacina 0:ac4dea3e2894 231
seyhmus.cacina 0:ac4dea3e2894 232 // Set device address 0, enable USB device, no remote wakeup
seyhmus.cacina 0:ac4dea3e2894 233 devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
seyhmus.cacina 0:ac4dea3e2894 234 LPC_USB->DEVCMDSTAT = devCmdStat;
seyhmus.cacina 0:ac4dea3e2894 235
seyhmus.cacina 0:ac4dea3e2894 236 // Enable interrupts for device events and EP0
seyhmus.cacina 0:ac4dea3e2894 237 LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
seyhmus.cacina 0:ac4dea3e2894 238 instance = this;
seyhmus.cacina 0:ac4dea3e2894 239
seyhmus.cacina 0:ac4dea3e2894 240 //attach IRQ handler and enable interrupts
seyhmus.cacina 0:ac4dea3e2894 241 NVIC_SetVector(USB_IRQ, (uint32_t)&_usbisr);
seyhmus.cacina 0:ac4dea3e2894 242 }
seyhmus.cacina 0:ac4dea3e2894 243
seyhmus.cacina 0:ac4dea3e2894 244 USBHAL::~USBHAL(void) {
seyhmus.cacina 0:ac4dea3e2894 245 // Ensure device disconnected (DCON not set)
seyhmus.cacina 0:ac4dea3e2894 246 LPC_USB->DEVCMDSTAT = 0;
seyhmus.cacina 0:ac4dea3e2894 247 // Disable USB interrupts
seyhmus.cacina 0:ac4dea3e2894 248 NVIC_DisableIRQ(USB_IRQ);
seyhmus.cacina 0:ac4dea3e2894 249 }
seyhmus.cacina 0:ac4dea3e2894 250
seyhmus.cacina 0:ac4dea3e2894 251 void USBHAL::connect(void) {
seyhmus.cacina 0:ac4dea3e2894 252 NVIC_EnableIRQ(USB_IRQ);
seyhmus.cacina 0:ac4dea3e2894 253 devCmdStat |= DCON;
seyhmus.cacina 0:ac4dea3e2894 254 LPC_USB->DEVCMDSTAT = devCmdStat;
seyhmus.cacina 0:ac4dea3e2894 255 }
seyhmus.cacina 0:ac4dea3e2894 256
seyhmus.cacina 0:ac4dea3e2894 257 void USBHAL::disconnect(void) {
seyhmus.cacina 0:ac4dea3e2894 258 NVIC_DisableIRQ(USB_IRQ);
seyhmus.cacina 0:ac4dea3e2894 259 devCmdStat &= ~DCON;
seyhmus.cacina 0:ac4dea3e2894 260 LPC_USB->DEVCMDSTAT = devCmdStat;
seyhmus.cacina 0:ac4dea3e2894 261 }
seyhmus.cacina 0:ac4dea3e2894 262
seyhmus.cacina 0:ac4dea3e2894 263 void USBHAL::configureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 264 // Not required
seyhmus.cacina 0:ac4dea3e2894 265 }
seyhmus.cacina 0:ac4dea3e2894 266
seyhmus.cacina 0:ac4dea3e2894 267 void USBHAL::unconfigureDevice(void) {
seyhmus.cacina 0:ac4dea3e2894 268 // Not required
seyhmus.cacina 0:ac4dea3e2894 269 }
seyhmus.cacina 0:ac4dea3e2894 270
seyhmus.cacina 0:ac4dea3e2894 271 void USBHAL::EP0setup(uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 272 // Copy setup packet data
seyhmus.cacina 0:ac4dea3e2894 273 USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
seyhmus.cacina 0:ac4dea3e2894 274 }
seyhmus.cacina 0:ac4dea3e2894 275
seyhmus.cacina 0:ac4dea3e2894 276 void USBHAL::EP0read(void) {
seyhmus.cacina 0:ac4dea3e2894 277 // Start an endpoint 0 read
seyhmus.cacina 0:ac4dea3e2894 278
seyhmus.cacina 0:ac4dea3e2894 279 // The USB ISR will call USBDevice_EP0out() when a packet has been read,
seyhmus.cacina 0:ac4dea3e2894 280 // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
seyhmus.cacina 0:ac4dea3e2894 281 // read the data.
seyhmus.cacina 0:ac4dea3e2894 282
seyhmus.cacina 0:ac4dea3e2894 283 ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
seyhmus.cacina 0:ac4dea3e2894 284 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
seyhmus.cacina 0:ac4dea3e2894 285 }
seyhmus.cacina 0:ac4dea3e2894 286
seyhmus.cacina 0:ac4dea3e2894 287 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
seyhmus.cacina 0:ac4dea3e2894 288 // Complete an endpoint 0 read
seyhmus.cacina 0:ac4dea3e2894 289 uint32_t bytesRead;
seyhmus.cacina 0:ac4dea3e2894 290
seyhmus.cacina 0:ac4dea3e2894 291 // Find how many bytes were read
seyhmus.cacina 0:ac4dea3e2894 292 bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
seyhmus.cacina 0:ac4dea3e2894 293
seyhmus.cacina 0:ac4dea3e2894 294 // Copy data
seyhmus.cacina 0:ac4dea3e2894 295 USBMemCopy(buffer, ct->out, bytesRead);
seyhmus.cacina 0:ac4dea3e2894 296 return bytesRead;
seyhmus.cacina 0:ac4dea3e2894 297 }
seyhmus.cacina 0:ac4dea3e2894 298
seyhmus.cacina 0:ac4dea3e2894 299
seyhmus.cacina 0:ac4dea3e2894 300 void USBHAL::EP0readStage(void) {
seyhmus.cacina 0:ac4dea3e2894 301 // Not required
seyhmus.cacina 0:ac4dea3e2894 302 }
seyhmus.cacina 0:ac4dea3e2894 303
seyhmus.cacina 0:ac4dea3e2894 304 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 305 // Start and endpoint 0 write
seyhmus.cacina 0:ac4dea3e2894 306
seyhmus.cacina 0:ac4dea3e2894 307 // The USB ISR will call USBDevice_EP0in() when the data has
seyhmus.cacina 0:ac4dea3e2894 308 // been written, the USBDevice layer then calls
seyhmus.cacina 0:ac4dea3e2894 309 // USBBusInterface_EP0getWriteResult() to complete the transaction.
seyhmus.cacina 0:ac4dea3e2894 310
seyhmus.cacina 0:ac4dea3e2894 311 // Copy data
seyhmus.cacina 0:ac4dea3e2894 312 USBMemCopy(ct->in, buffer, size);
seyhmus.cacina 0:ac4dea3e2894 313
seyhmus.cacina 0:ac4dea3e2894 314 // Start transfer
seyhmus.cacina 0:ac4dea3e2894 315 ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
seyhmus.cacina 0:ac4dea3e2894 316 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
seyhmus.cacina 0:ac4dea3e2894 317 }
seyhmus.cacina 0:ac4dea3e2894 318
seyhmus.cacina 0:ac4dea3e2894 319
seyhmus.cacina 0:ac4dea3e2894 320 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
seyhmus.cacina 0:ac4dea3e2894 321 uint8_t bf = 0;
seyhmus.cacina 0:ac4dea3e2894 322 uint32_t flags = 0;
seyhmus.cacina 0:ac4dea3e2894 323
seyhmus.cacina 0:ac4dea3e2894 324 //check which buffer must be filled
seyhmus.cacina 0:ac4dea3e2894 325 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 326 // Double buffered
seyhmus.cacina 0:ac4dea3e2894 327 if (LPC_USB->EPINUSE & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 328 bf = 1;
seyhmus.cacina 0:ac4dea3e2894 329 } else {
seyhmus.cacina 0:ac4dea3e2894 330 bf = 0;
seyhmus.cacina 0:ac4dea3e2894 331 }
seyhmus.cacina 0:ac4dea3e2894 332 }
seyhmus.cacina 0:ac4dea3e2894 333
seyhmus.cacina 0:ac4dea3e2894 334 // if isochronous endpoint, T = 1
seyhmus.cacina 0:ac4dea3e2894 335 if(endpointState[endpoint].options & ISOCHRONOUS)
seyhmus.cacina 0:ac4dea3e2894 336 {
seyhmus.cacina 0:ac4dea3e2894 337 flags |= CMDSTS_T;
seyhmus.cacina 0:ac4dea3e2894 338 }
seyhmus.cacina 0:ac4dea3e2894 339
seyhmus.cacina 0:ac4dea3e2894 340 //Active the endpoint for reading
seyhmus.cacina 0:ac4dea3e2894 341 ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
seyhmus.cacina 0:ac4dea3e2894 342 | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
seyhmus.cacina 0:ac4dea3e2894 343 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 344 }
seyhmus.cacina 0:ac4dea3e2894 345
seyhmus.cacina 0:ac4dea3e2894 346 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
seyhmus.cacina 0:ac4dea3e2894 347
seyhmus.cacina 0:ac4dea3e2894 348 uint8_t bf = 0;
seyhmus.cacina 0:ac4dea3e2894 349
seyhmus.cacina 0:ac4dea3e2894 350 if (!(epComplete & EP(endpoint)))
seyhmus.cacina 0:ac4dea3e2894 351 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 352 else {
seyhmus.cacina 0:ac4dea3e2894 353 epComplete &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 354
seyhmus.cacina 0:ac4dea3e2894 355 //check which buffer has been filled
seyhmus.cacina 0:ac4dea3e2894 356 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 357 // Double buffered (here we read the previous buffer which was used)
seyhmus.cacina 0:ac4dea3e2894 358 if (LPC_USB->EPINUSE & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 359 bf = 0;
seyhmus.cacina 0:ac4dea3e2894 360 } else {
seyhmus.cacina 0:ac4dea3e2894 361 bf = 1;
seyhmus.cacina 0:ac4dea3e2894 362 }
seyhmus.cacina 0:ac4dea3e2894 363 }
seyhmus.cacina 0:ac4dea3e2894 364
seyhmus.cacina 0:ac4dea3e2894 365 // Find how many bytes were read
seyhmus.cacina 0:ac4dea3e2894 366 *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
seyhmus.cacina 0:ac4dea3e2894 367
seyhmus.cacina 0:ac4dea3e2894 368 // Copy data
seyhmus.cacina 0:ac4dea3e2894 369 USBMemCopy(data, ct->out, *bytesRead);
seyhmus.cacina 0:ac4dea3e2894 370 return EP_COMPLETED;
seyhmus.cacina 0:ac4dea3e2894 371 }
seyhmus.cacina 0:ac4dea3e2894 372 }
seyhmus.cacina 0:ac4dea3e2894 373
seyhmus.cacina 0:ac4dea3e2894 374 void USBHAL::EP0getWriteResult(void) {
seyhmus.cacina 0:ac4dea3e2894 375 // Not required
seyhmus.cacina 0:ac4dea3e2894 376 }
seyhmus.cacina 0:ac4dea3e2894 377
seyhmus.cacina 0:ac4dea3e2894 378 void USBHAL::EP0stall(void) {
seyhmus.cacina 0:ac4dea3e2894 379 ep[0].in[0] = CMDSTS_S;
seyhmus.cacina 0:ac4dea3e2894 380 ep[0].out[0] = CMDSTS_S;
seyhmus.cacina 0:ac4dea3e2894 381 }
seyhmus.cacina 0:ac4dea3e2894 382
seyhmus.cacina 0:ac4dea3e2894 383 void USBHAL::setAddress(uint8_t address) {
seyhmus.cacina 0:ac4dea3e2894 384 devCmdStat &= ~DEV_ADDR_MASK;
seyhmus.cacina 0:ac4dea3e2894 385 devCmdStat |= DEV_ADDR(address);
seyhmus.cacina 0:ac4dea3e2894 386 LPC_USB->DEVCMDSTAT = devCmdStat;
seyhmus.cacina 0:ac4dea3e2894 387 }
seyhmus.cacina 0:ac4dea3e2894 388
seyhmus.cacina 0:ac4dea3e2894 389 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
seyhmus.cacina 0:ac4dea3e2894 390 uint32_t flags = 0;
seyhmus.cacina 0:ac4dea3e2894 391 uint32_t bf;
seyhmus.cacina 0:ac4dea3e2894 392
seyhmus.cacina 0:ac4dea3e2894 393 // Validate parameters
seyhmus.cacina 0:ac4dea3e2894 394 if (data == NULL) {
seyhmus.cacina 0:ac4dea3e2894 395 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 396 }
seyhmus.cacina 0:ac4dea3e2894 397
seyhmus.cacina 0:ac4dea3e2894 398 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
seyhmus.cacina 0:ac4dea3e2894 399 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 400 }
seyhmus.cacina 0:ac4dea3e2894 401
seyhmus.cacina 0:ac4dea3e2894 402 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
seyhmus.cacina 0:ac4dea3e2894 403 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 404 }
seyhmus.cacina 0:ac4dea3e2894 405
seyhmus.cacina 0:ac4dea3e2894 406 if (size > endpointState[endpoint].maxPacket) {
seyhmus.cacina 0:ac4dea3e2894 407 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 408 }
seyhmus.cacina 0:ac4dea3e2894 409
seyhmus.cacina 0:ac4dea3e2894 410 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 411 // Double buffered
seyhmus.cacina 0:ac4dea3e2894 412 if (LPC_USB->EPINUSE & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 413 bf = 1;
seyhmus.cacina 0:ac4dea3e2894 414 } else {
seyhmus.cacina 0:ac4dea3e2894 415 bf = 0;
seyhmus.cacina 0:ac4dea3e2894 416 }
seyhmus.cacina 0:ac4dea3e2894 417 } else {
seyhmus.cacina 0:ac4dea3e2894 418 // Single buffered
seyhmus.cacina 0:ac4dea3e2894 419 bf = 0;
seyhmus.cacina 0:ac4dea3e2894 420 }
seyhmus.cacina 0:ac4dea3e2894 421
seyhmus.cacina 0:ac4dea3e2894 422 // Check if already active
seyhmus.cacina 0:ac4dea3e2894 423 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
seyhmus.cacina 0:ac4dea3e2894 424 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 425 }
seyhmus.cacina 0:ac4dea3e2894 426
seyhmus.cacina 0:ac4dea3e2894 427 // Check if stalled
seyhmus.cacina 0:ac4dea3e2894 428 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
seyhmus.cacina 0:ac4dea3e2894 429 return EP_STALLED;
seyhmus.cacina 0:ac4dea3e2894 430 }
seyhmus.cacina 0:ac4dea3e2894 431
seyhmus.cacina 0:ac4dea3e2894 432 // Copy data to USB RAM
seyhmus.cacina 0:ac4dea3e2894 433 USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
seyhmus.cacina 0:ac4dea3e2894 434
seyhmus.cacina 0:ac4dea3e2894 435 // Add options
seyhmus.cacina 0:ac4dea3e2894 436 if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
seyhmus.cacina 0:ac4dea3e2894 437 flags |= CMDSTS_RF;
seyhmus.cacina 0:ac4dea3e2894 438 }
seyhmus.cacina 0:ac4dea3e2894 439
seyhmus.cacina 0:ac4dea3e2894 440 if (endpointState[endpoint].options & ISOCHRONOUS) {
seyhmus.cacina 0:ac4dea3e2894 441 flags |= CMDSTS_T;
seyhmus.cacina 0:ac4dea3e2894 442 }
seyhmus.cacina 0:ac4dea3e2894 443
seyhmus.cacina 0:ac4dea3e2894 444 // Add transfer
seyhmus.cacina 0:ac4dea3e2894 445 ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
seyhmus.cacina 0:ac4dea3e2894 446 endpointState[endpoint].buffer[bf]) \
seyhmus.cacina 0:ac4dea3e2894 447 | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
seyhmus.cacina 0:ac4dea3e2894 448
seyhmus.cacina 0:ac4dea3e2894 449 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 450 }
seyhmus.cacina 0:ac4dea3e2894 451
seyhmus.cacina 0:ac4dea3e2894 452 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 453 uint32_t bf;
seyhmus.cacina 0:ac4dea3e2894 454
seyhmus.cacina 0:ac4dea3e2894 455 // Validate parameters
seyhmus.cacina 0:ac4dea3e2894 456 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
seyhmus.cacina 0:ac4dea3e2894 457 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 458 }
seyhmus.cacina 0:ac4dea3e2894 459
seyhmus.cacina 0:ac4dea3e2894 460 if (OUT_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 461 return EP_INVALID;
seyhmus.cacina 0:ac4dea3e2894 462 }
seyhmus.cacina 0:ac4dea3e2894 463
seyhmus.cacina 0:ac4dea3e2894 464 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 465 // Double buffered // TODO: FIX THIS
seyhmus.cacina 0:ac4dea3e2894 466 if (LPC_USB->EPINUSE & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 467 bf = 1;
seyhmus.cacina 0:ac4dea3e2894 468 } else {
seyhmus.cacina 0:ac4dea3e2894 469 bf = 0;
seyhmus.cacina 0:ac4dea3e2894 470 }
seyhmus.cacina 0:ac4dea3e2894 471 } else {
seyhmus.cacina 0:ac4dea3e2894 472 // Single buffered
seyhmus.cacina 0:ac4dea3e2894 473 bf = 0;
seyhmus.cacina 0:ac4dea3e2894 474 }
seyhmus.cacina 0:ac4dea3e2894 475
seyhmus.cacina 0:ac4dea3e2894 476 // Check if endpoint still active
seyhmus.cacina 0:ac4dea3e2894 477 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
seyhmus.cacina 0:ac4dea3e2894 478 return EP_PENDING;
seyhmus.cacina 0:ac4dea3e2894 479 }
seyhmus.cacina 0:ac4dea3e2894 480
seyhmus.cacina 0:ac4dea3e2894 481 // Check if stalled
seyhmus.cacina 0:ac4dea3e2894 482 if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
seyhmus.cacina 0:ac4dea3e2894 483 return EP_STALLED;
seyhmus.cacina 0:ac4dea3e2894 484 }
seyhmus.cacina 0:ac4dea3e2894 485
seyhmus.cacina 0:ac4dea3e2894 486 return EP_COMPLETED;
seyhmus.cacina 0:ac4dea3e2894 487 }
seyhmus.cacina 0:ac4dea3e2894 488
seyhmus.cacina 0:ac4dea3e2894 489 void USBHAL::stallEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 490
seyhmus.cacina 0:ac4dea3e2894 491 // FIX: should this clear active bit?
seyhmus.cacina 0:ac4dea3e2894 492 if (IN_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 493 ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
seyhmus.cacina 0:ac4dea3e2894 494 ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
seyhmus.cacina 0:ac4dea3e2894 495 } else {
seyhmus.cacina 0:ac4dea3e2894 496 ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
seyhmus.cacina 0:ac4dea3e2894 497 ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
seyhmus.cacina 0:ac4dea3e2894 498 }
seyhmus.cacina 0:ac4dea3e2894 499 }
seyhmus.cacina 0:ac4dea3e2894 500
seyhmus.cacina 0:ac4dea3e2894 501 void USBHAL::unstallEndpoint(uint8_t endpoint) {
seyhmus.cacina 0:ac4dea3e2894 502 if (LPC_USB->EPBUFCFG & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 503 // Double buffered
seyhmus.cacina 0:ac4dea3e2894 504 if (IN_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 505 ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
seyhmus.cacina 0:ac4dea3e2894 506 ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
seyhmus.cacina 0:ac4dea3e2894 507
seyhmus.cacina 0:ac4dea3e2894 508 if (LPC_USB->EPINUSE & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 509 ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
seyhmus.cacina 0:ac4dea3e2894 510 } else {
seyhmus.cacina 0:ac4dea3e2894 511 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
seyhmus.cacina 0:ac4dea3e2894 512 }
seyhmus.cacina 0:ac4dea3e2894 513 } else {
seyhmus.cacina 0:ac4dea3e2894 514 ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
seyhmus.cacina 0:ac4dea3e2894 515 ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
seyhmus.cacina 0:ac4dea3e2894 516
seyhmus.cacina 0:ac4dea3e2894 517 if (LPC_USB->EPINUSE & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 518 ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
seyhmus.cacina 0:ac4dea3e2894 519 } else {
seyhmus.cacina 0:ac4dea3e2894 520 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
seyhmus.cacina 0:ac4dea3e2894 521 }
seyhmus.cacina 0:ac4dea3e2894 522 }
seyhmus.cacina 0:ac4dea3e2894 523 } else {
seyhmus.cacina 0:ac4dea3e2894 524 // Single buffered
seyhmus.cacina 0:ac4dea3e2894 525 if (IN_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 526 ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
seyhmus.cacina 0:ac4dea3e2894 527 } else {
seyhmus.cacina 0:ac4dea3e2894 528 ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
seyhmus.cacina 0:ac4dea3e2894 529 }
seyhmus.cacina 0:ac4dea3e2894 530 }
seyhmus.cacina 0:ac4dea3e2894 531 }
seyhmus.cacina 0:ac4dea3e2894 532
seyhmus.cacina 0:ac4dea3e2894 533 bool USBHAL::getEndpointStallState(unsigned char endpoint) {
seyhmus.cacina 0:ac4dea3e2894 534 if (IN_EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 535 if (LPC_USB->EPINUSE & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 536 if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
seyhmus.cacina 0:ac4dea3e2894 537 return true;
seyhmus.cacina 0:ac4dea3e2894 538 }
seyhmus.cacina 0:ac4dea3e2894 539 } else {
seyhmus.cacina 0:ac4dea3e2894 540 if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
seyhmus.cacina 0:ac4dea3e2894 541 return true;
seyhmus.cacina 0:ac4dea3e2894 542 }
seyhmus.cacina 0:ac4dea3e2894 543 }
seyhmus.cacina 0:ac4dea3e2894 544 } else {
seyhmus.cacina 0:ac4dea3e2894 545 if (LPC_USB->EPINUSE & EP(endpoint)) {
seyhmus.cacina 0:ac4dea3e2894 546 if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
seyhmus.cacina 0:ac4dea3e2894 547 return true;
seyhmus.cacina 0:ac4dea3e2894 548 }
seyhmus.cacina 0:ac4dea3e2894 549 } else {
seyhmus.cacina 0:ac4dea3e2894 550 if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
seyhmus.cacina 0:ac4dea3e2894 551 return true;
seyhmus.cacina 0:ac4dea3e2894 552 }
seyhmus.cacina 0:ac4dea3e2894 553 }
seyhmus.cacina 0:ac4dea3e2894 554 }
seyhmus.cacina 0:ac4dea3e2894 555
seyhmus.cacina 0:ac4dea3e2894 556 return false;
seyhmus.cacina 0:ac4dea3e2894 557 }
seyhmus.cacina 0:ac4dea3e2894 558
seyhmus.cacina 0:ac4dea3e2894 559 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
seyhmus.cacina 0:ac4dea3e2894 560 uint32_t tmpEpRamPtr;
seyhmus.cacina 0:ac4dea3e2894 561
seyhmus.cacina 0:ac4dea3e2894 562 if (endpoint > LAST_PHYSICAL_ENDPOINT) {
seyhmus.cacina 0:ac4dea3e2894 563 return false;
seyhmus.cacina 0:ac4dea3e2894 564 }
seyhmus.cacina 0:ac4dea3e2894 565
seyhmus.cacina 0:ac4dea3e2894 566 // Not applicable to the control endpoints
seyhmus.cacina 0:ac4dea3e2894 567 if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
seyhmus.cacina 0:ac4dea3e2894 568 return false;
seyhmus.cacina 0:ac4dea3e2894 569 }
seyhmus.cacina 0:ac4dea3e2894 570
seyhmus.cacina 0:ac4dea3e2894 571 // Allocate buffers in USB RAM
seyhmus.cacina 0:ac4dea3e2894 572 tmpEpRamPtr = epRamPtr;
seyhmus.cacina 0:ac4dea3e2894 573
seyhmus.cacina 0:ac4dea3e2894 574 // Must be 64 byte aligned
seyhmus.cacina 0:ac4dea3e2894 575 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
seyhmus.cacina 0:ac4dea3e2894 576
seyhmus.cacina 0:ac4dea3e2894 577 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
seyhmus.cacina 0:ac4dea3e2894 578 // Out of memory
seyhmus.cacina 0:ac4dea3e2894 579 return false;
seyhmus.cacina 0:ac4dea3e2894 580 }
seyhmus.cacina 0:ac4dea3e2894 581
seyhmus.cacina 0:ac4dea3e2894 582 // Allocate first buffer
seyhmus.cacina 0:ac4dea3e2894 583 endpointState[endpoint].buffer[0] = tmpEpRamPtr;
seyhmus.cacina 0:ac4dea3e2894 584 tmpEpRamPtr += maxPacket;
seyhmus.cacina 0:ac4dea3e2894 585
seyhmus.cacina 0:ac4dea3e2894 586 if (!(options & SINGLE_BUFFERED)) {
seyhmus.cacina 0:ac4dea3e2894 587 // Must be 64 byte aligned
seyhmus.cacina 0:ac4dea3e2894 588 tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
seyhmus.cacina 0:ac4dea3e2894 589
seyhmus.cacina 0:ac4dea3e2894 590 if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
seyhmus.cacina 0:ac4dea3e2894 591 // Out of memory
seyhmus.cacina 0:ac4dea3e2894 592 return false;
seyhmus.cacina 0:ac4dea3e2894 593 }
seyhmus.cacina 0:ac4dea3e2894 594
seyhmus.cacina 0:ac4dea3e2894 595 // Allocate second buffer
seyhmus.cacina 0:ac4dea3e2894 596 endpointState[endpoint].buffer[1] = tmpEpRamPtr;
seyhmus.cacina 0:ac4dea3e2894 597 tmpEpRamPtr += maxPacket;
seyhmus.cacina 0:ac4dea3e2894 598 }
seyhmus.cacina 0:ac4dea3e2894 599
seyhmus.cacina 0:ac4dea3e2894 600 // Commit to this USB RAM allocation
seyhmus.cacina 0:ac4dea3e2894 601 epRamPtr = tmpEpRamPtr;
seyhmus.cacina 0:ac4dea3e2894 602
seyhmus.cacina 0:ac4dea3e2894 603 // Remaining endpoint state values
seyhmus.cacina 0:ac4dea3e2894 604 endpointState[endpoint].maxPacket = maxPacket;
seyhmus.cacina 0:ac4dea3e2894 605 endpointState[endpoint].options = options;
seyhmus.cacina 0:ac4dea3e2894 606
seyhmus.cacina 0:ac4dea3e2894 607 // Enable double buffering if required
seyhmus.cacina 0:ac4dea3e2894 608 if (options & SINGLE_BUFFERED) {
seyhmus.cacina 0:ac4dea3e2894 609 LPC_USB->EPBUFCFG &= ~EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 610 } else {
seyhmus.cacina 0:ac4dea3e2894 611 // Double buffered
seyhmus.cacina 0:ac4dea3e2894 612 LPC_USB->EPBUFCFG |= EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 613 }
seyhmus.cacina 0:ac4dea3e2894 614
seyhmus.cacina 0:ac4dea3e2894 615 // Enable interrupt
seyhmus.cacina 0:ac4dea3e2894 616 LPC_USB->INTEN |= EP(endpoint);
seyhmus.cacina 0:ac4dea3e2894 617
seyhmus.cacina 0:ac4dea3e2894 618 // Enable endpoint
seyhmus.cacina 0:ac4dea3e2894 619 unstallEndpoint(endpoint);
seyhmus.cacina 0:ac4dea3e2894 620 return true;
seyhmus.cacina 0:ac4dea3e2894 621 }
seyhmus.cacina 0:ac4dea3e2894 622
seyhmus.cacina 0:ac4dea3e2894 623 void USBHAL::remoteWakeup(void) {
seyhmus.cacina 0:ac4dea3e2894 624 // Clearing DSUS bit initiates a remote wakeup if the
seyhmus.cacina 0:ac4dea3e2894 625 // device is currently enabled and suspended - otherwise
seyhmus.cacina 0:ac4dea3e2894 626 // it has no effect.
seyhmus.cacina 0:ac4dea3e2894 627 LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
seyhmus.cacina 0:ac4dea3e2894 628 }
seyhmus.cacina 0:ac4dea3e2894 629
seyhmus.cacina 0:ac4dea3e2894 630
seyhmus.cacina 0:ac4dea3e2894 631 static void disableEndpoints(void) {
seyhmus.cacina 0:ac4dea3e2894 632 uint32_t logEp;
seyhmus.cacina 0:ac4dea3e2894 633
seyhmus.cacina 0:ac4dea3e2894 634 // Ref. Table 158 "When a bus reset is received, software
seyhmus.cacina 0:ac4dea3e2894 635 // must set the disable bit of all endpoints to 1".
seyhmus.cacina 0:ac4dea3e2894 636
seyhmus.cacina 0:ac4dea3e2894 637 for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
seyhmus.cacina 0:ac4dea3e2894 638 ep[logEp].out[0] = CMDSTS_D;
seyhmus.cacina 0:ac4dea3e2894 639 ep[logEp].out[1] = CMDSTS_D;
seyhmus.cacina 0:ac4dea3e2894 640 ep[logEp].in[0] = CMDSTS_D;
seyhmus.cacina 0:ac4dea3e2894 641 ep[logEp].in[1] = CMDSTS_D;
seyhmus.cacina 0:ac4dea3e2894 642 }
seyhmus.cacina 0:ac4dea3e2894 643
seyhmus.cacina 0:ac4dea3e2894 644 // Start of USB RAM for endpoints > 0
seyhmus.cacina 0:ac4dea3e2894 645 epRamPtr = usbRamPtr;
seyhmus.cacina 0:ac4dea3e2894 646 }
seyhmus.cacina 0:ac4dea3e2894 647
seyhmus.cacina 0:ac4dea3e2894 648
seyhmus.cacina 0:ac4dea3e2894 649
seyhmus.cacina 0:ac4dea3e2894 650 void USBHAL::_usbisr(void) {
seyhmus.cacina 0:ac4dea3e2894 651 instance->usbisr();
seyhmus.cacina 0:ac4dea3e2894 652 }
seyhmus.cacina 0:ac4dea3e2894 653
seyhmus.cacina 0:ac4dea3e2894 654 void USBHAL::usbisr(void) {
seyhmus.cacina 0:ac4dea3e2894 655 // Start of frame
seyhmus.cacina 0:ac4dea3e2894 656 if (LPC_USB->INTSTAT & FRAME_INT) {
seyhmus.cacina 0:ac4dea3e2894 657 // Clear SOF interrupt
seyhmus.cacina 0:ac4dea3e2894 658 LPC_USB->INTSTAT = FRAME_INT;
seyhmus.cacina 0:ac4dea3e2894 659
seyhmus.cacina 0:ac4dea3e2894 660 // SOF event, read frame number
seyhmus.cacina 0:ac4dea3e2894 661 SOF(FRAME_NR(LPC_USB->INFO));
seyhmus.cacina 0:ac4dea3e2894 662 }
seyhmus.cacina 0:ac4dea3e2894 663
seyhmus.cacina 0:ac4dea3e2894 664 // Device state
seyhmus.cacina 0:ac4dea3e2894 665 if (LPC_USB->INTSTAT & DEV_INT) {
seyhmus.cacina 0:ac4dea3e2894 666 LPC_USB->INTSTAT = DEV_INT;
seyhmus.cacina 0:ac4dea3e2894 667
seyhmus.cacina 0:ac4dea3e2894 668 if (LPC_USB->DEVCMDSTAT & DSUS_C) {
seyhmus.cacina 0:ac4dea3e2894 669 // Suspend status changed
seyhmus.cacina 0:ac4dea3e2894 670 LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
seyhmus.cacina 0:ac4dea3e2894 671 if (LPC_USB->DEVCMDSTAT & DSUS) {
seyhmus.cacina 0:ac4dea3e2894 672 suspendStateChanged(1);
seyhmus.cacina 0:ac4dea3e2894 673 } else {
seyhmus.cacina 0:ac4dea3e2894 674 suspendStateChanged(0);
seyhmus.cacina 0:ac4dea3e2894 675 }
seyhmus.cacina 0:ac4dea3e2894 676 }
seyhmus.cacina 0:ac4dea3e2894 677
seyhmus.cacina 0:ac4dea3e2894 678 if (LPC_USB->DEVCMDSTAT & DRES_C) {
seyhmus.cacina 0:ac4dea3e2894 679 // Bus reset
seyhmus.cacina 0:ac4dea3e2894 680 LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
seyhmus.cacina 0:ac4dea3e2894 681
seyhmus.cacina 0:ac4dea3e2894 682 // Disable endpoints > 0
seyhmus.cacina 0:ac4dea3e2894 683 disableEndpoints();
seyhmus.cacina 0:ac4dea3e2894 684
seyhmus.cacina 0:ac4dea3e2894 685 // Bus reset event
seyhmus.cacina 0:ac4dea3e2894 686 busReset();
seyhmus.cacina 0:ac4dea3e2894 687 }
seyhmus.cacina 0:ac4dea3e2894 688 }
seyhmus.cacina 0:ac4dea3e2894 689
seyhmus.cacina 0:ac4dea3e2894 690 // Endpoint 0
seyhmus.cacina 0:ac4dea3e2894 691 if (LPC_USB->INTSTAT & EP(EP0OUT)) {
seyhmus.cacina 0:ac4dea3e2894 692 // Clear EP0OUT/SETUP interrupt
seyhmus.cacina 0:ac4dea3e2894 693 LPC_USB->INTSTAT = EP(EP0OUT);
seyhmus.cacina 0:ac4dea3e2894 694
seyhmus.cacina 0:ac4dea3e2894 695 // Check if SETUP
seyhmus.cacina 0:ac4dea3e2894 696 if (LPC_USB->DEVCMDSTAT & SETUP) {
seyhmus.cacina 0:ac4dea3e2894 697 // Clear Active and Stall bits for EP0
seyhmus.cacina 0:ac4dea3e2894 698 // Documentation does not make it clear if we must use the
seyhmus.cacina 0:ac4dea3e2894 699 // EPSKIP register to achieve this, Fig. 16 and NXP reference
seyhmus.cacina 0:ac4dea3e2894 700 // code suggests we can just clear the Active bits - check with
seyhmus.cacina 0:ac4dea3e2894 701 // NXP to be sure.
seyhmus.cacina 0:ac4dea3e2894 702 ep[0].in[0] = 0;
seyhmus.cacina 0:ac4dea3e2894 703 ep[0].out[0] = 0;
seyhmus.cacina 0:ac4dea3e2894 704
seyhmus.cacina 0:ac4dea3e2894 705 // Clear EP0IN interrupt
seyhmus.cacina 0:ac4dea3e2894 706 LPC_USB->INTSTAT = EP(EP0IN);
seyhmus.cacina 0:ac4dea3e2894 707
seyhmus.cacina 0:ac4dea3e2894 708 // Clear SETUP (and INTONNAK_CI/O) in device status register
seyhmus.cacina 0:ac4dea3e2894 709 LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
seyhmus.cacina 0:ac4dea3e2894 710
seyhmus.cacina 0:ac4dea3e2894 711 // EP0 SETUP event (SETUP data received)
seyhmus.cacina 0:ac4dea3e2894 712 EP0setupCallback();
seyhmus.cacina 0:ac4dea3e2894 713 } else {
seyhmus.cacina 0:ac4dea3e2894 714 // EP0OUT ACK event (OUT data received)
seyhmus.cacina 0:ac4dea3e2894 715 EP0out();
seyhmus.cacina 0:ac4dea3e2894 716 }
seyhmus.cacina 0:ac4dea3e2894 717 }
seyhmus.cacina 0:ac4dea3e2894 718
seyhmus.cacina 0:ac4dea3e2894 719 if (LPC_USB->INTSTAT & EP(EP0IN)) {
seyhmus.cacina 0:ac4dea3e2894 720 // Clear EP0IN interrupt
seyhmus.cacina 0:ac4dea3e2894 721 LPC_USB->INTSTAT = EP(EP0IN);
seyhmus.cacina 0:ac4dea3e2894 722
seyhmus.cacina 0:ac4dea3e2894 723 // EP0IN ACK event (IN data sent)
seyhmus.cacina 0:ac4dea3e2894 724 EP0in();
seyhmus.cacina 0:ac4dea3e2894 725 }
seyhmus.cacina 0:ac4dea3e2894 726
seyhmus.cacina 0:ac4dea3e2894 727 for (uint8_t num = 2; num < 5*2; num++) {
seyhmus.cacina 0:ac4dea3e2894 728 if (LPC_USB->INTSTAT & EP(num)) {
seyhmus.cacina 0:ac4dea3e2894 729 LPC_USB->INTSTAT = EP(num);
seyhmus.cacina 0:ac4dea3e2894 730 epComplete |= EP(num);
seyhmus.cacina 0:ac4dea3e2894 731 if ((instance->*(epCallback[num - 2]))()) {
seyhmus.cacina 0:ac4dea3e2894 732 epComplete &= ~EP(num);
seyhmus.cacina 0:ac4dea3e2894 733 }
seyhmus.cacina 0:ac4dea3e2894 734 }
seyhmus.cacina 0:ac4dea3e2894 735 }
seyhmus.cacina 0:ac4dea3e2894 736 }
seyhmus.cacina 0:ac4dea3e2894 737
seyhmus.cacina 0:ac4dea3e2894 738 #endif