Bradley Scott / STM32_USBDevice

USBDevice with support for STM32F3

Fork of F042K6_USBDevice by Norimasa Okamoto

USBDevice/USBHAL_STM32F4.cpp@16:4f6df64750bd, 2013-12-05 (annotated)

Committer:
mbed_official
Date:
Thu Dec 05 13:00:15 2013 +0000
Revision:
16:4f6df64750bd
Child:
25:7c72828865f3
Synchronized with git revision fa451a0f0ae4ea99e333083931cc5bfc77b27b42



Full URL: https://github.com/mbedmicro/mbed/commit/fa451a0f0ae4ea99e333083931cc5bfc77b27b42/



Add initial USB Device support for STM32F4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 16:4f6df64750bd 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
mbed_official 16:4f6df64750bd 2 *
mbed_official 16:4f6df64750bd 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
mbed_official 16:4f6df64750bd 4 * and associated documentation files (the "Software"), to deal in the Software without
mbed_official 16:4f6df64750bd 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
mbed_official 16:4f6df64750bd 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
mbed_official 16:4f6df64750bd 7 * Software is furnished to do so, subject to the following conditions:
mbed_official 16:4f6df64750bd 8 *
mbed_official 16:4f6df64750bd 9 * The above copyright notice and this permission notice shall be included in all copies or
mbed_official 16:4f6df64750bd 10 * substantial portions of the Software.
mbed_official 16:4f6df64750bd 11 *
mbed_official 16:4f6df64750bd 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
mbed_official 16:4f6df64750bd 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
mbed_official 16:4f6df64750bd 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
mbed_official 16:4f6df64750bd 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
mbed_official 16:4f6df64750bd 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
mbed_official 16:4f6df64750bd 17 */
mbed_official 16:4f6df64750bd 18
mbed_official 16:4f6df64750bd 19 #if defined(TARGET_STM32F4XX)
mbed_official 16:4f6df64750bd 20
mbed_official 16:4f6df64750bd 21 #include "USBHAL.h"
mbed_official 16:4f6df64750bd 22 #include "USBRegs_STM32.h"
mbed_official 16:4f6df64750bd 23 #include "pinmap.h"
mbed_official 16:4f6df64750bd 24
mbed_official 16:4f6df64750bd 25 USBHAL * USBHAL::instance;
mbed_official 16:4f6df64750bd 26
mbed_official 16:4f6df64750bd 27 static volatile int epComplete = 0;
mbed_official 16:4f6df64750bd 28
mbed_official 16:4f6df64750bd 29 static uint32_t bufferEnd = 0;
mbed_official 16:4f6df64750bd 30 static const uint32_t rxFifoSize = 512;
mbed_official 16:4f6df64750bd 31 static uint32_t rxFifoCount = 0;
mbed_official 16:4f6df64750bd 32
mbed_official 16:4f6df64750bd 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
mbed_official 16:4f6df64750bd 34
mbed_official 16:4f6df64750bd 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
mbed_official 16:4f6df64750bd 36 return 0;
mbed_official 16:4f6df64750bd 37 }
mbed_official 16:4f6df64750bd 38
mbed_official 16:4f6df64750bd 39 USBHAL::USBHAL(void) {
mbed_official 16:4f6df64750bd 40 NVIC_DisableIRQ(OTG_FS_IRQn);
mbed_official 16:4f6df64750bd 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
mbed_official 16:4f6df64750bd 42 epCallback[1] = &USBHAL::EP1_IN_callback;
mbed_official 16:4f6df64750bd 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
mbed_official 16:4f6df64750bd 44 epCallback[3] = &USBHAL::EP2_IN_callback;
mbed_official 16:4f6df64750bd 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
mbed_official 16:4f6df64750bd 46 epCallback[5] = &USBHAL::EP3_IN_callback;
mbed_official 16:4f6df64750bd 47
mbed_official 16:4f6df64750bd 48 // Enable power and clocking
mbed_official 16:4f6df64750bd 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
mbed_official 16:4f6df64750bd 50
mbed_official 16:4f6df64750bd 51 pin_function(PA_8, STM_PIN_DATA(2, 10));
mbed_official 16:4f6df64750bd 52 pin_function(PA_9, STM_PIN_DATA(0, 0));
mbed_official 16:4f6df64750bd 53 pin_function(PA_10, STM_PIN_DATA(2, 10));
mbed_official 16:4f6df64750bd 54 pin_function(PA_11, STM_PIN_DATA(2, 10));
mbed_official 16:4f6df64750bd 55 pin_function(PA_12, STM_PIN_DATA(2, 10));
mbed_official 16:4f6df64750bd 56
mbed_official 16:4f6df64750bd 57 // Set ID pin to open drain with pull-up resistor
mbed_official 16:4f6df64750bd 58 pin_mode(PA_10, OpenDrain);
mbed_official 16:4f6df64750bd 59 GPIOA->PUPDR &= ~(0x3 << 20);
mbed_official 16:4f6df64750bd 60 GPIOA->PUPDR |= 1 << 20;
mbed_official 16:4f6df64750bd 61
mbed_official 16:4f6df64750bd 62 // Set VBUS pin to open drain
mbed_official 16:4f6df64750bd 63 pin_mode(PA_9, OpenDrain);
mbed_official 16:4f6df64750bd 64
mbed_official 16:4f6df64750bd 65 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
mbed_official 16:4f6df64750bd 66
mbed_official 16:4f6df64750bd 67 // Enable interrupts
mbed_official 16:4f6df64750bd 68 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
mbed_official 16:4f6df64750bd 69
mbed_official 16:4f6df64750bd 70 // Turnaround time to maximum value - too small causes packet loss
mbed_official 16:4f6df64750bd 71 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
mbed_official 16:4f6df64750bd 72
mbed_official 16:4f6df64750bd 73 // Unmask global interrupts
mbed_official 16:4f6df64750bd 74 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
mbed_official 16:4f6df64750bd 75 (1 << 4) | // RX FIFO not empty
mbed_official 16:4f6df64750bd 76 (1 << 12); // USB reset
mbed_official 16:4f6df64750bd 77
mbed_official 16:4f6df64750bd 78 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
mbed_official 16:4f6df64750bd 79 (1 << 2); // Non-zero-length status OUT handshake
mbed_official 16:4f6df64750bd 80
mbed_official 16:4f6df64750bd 81 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
mbed_official 16:4f6df64750bd 82 (1 << 16); // Power Up
mbed_official 16:4f6df64750bd 83
mbed_official 16:4f6df64750bd 84 instance = this;
mbed_official 16:4f6df64750bd 85 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
mbed_official 16:4f6df64750bd 86 NVIC_SetPriority(OTG_FS_IRQn, 1);
mbed_official 16:4f6df64750bd 87 }
mbed_official 16:4f6df64750bd 88
mbed_official 16:4f6df64750bd 89 USBHAL::~USBHAL(void) {
mbed_official 16:4f6df64750bd 90 }
mbed_official 16:4f6df64750bd 91
mbed_official 16:4f6df64750bd 92 void USBHAL::connect(void) {
mbed_official 16:4f6df64750bd 93 NVIC_EnableIRQ(OTG_FS_IRQn);
mbed_official 16:4f6df64750bd 94 }
mbed_official 16:4f6df64750bd 95
mbed_official 16:4f6df64750bd 96 void USBHAL::disconnect(void) {
mbed_official 16:4f6df64750bd 97 NVIC_DisableIRQ(OTG_FS_IRQn);
mbed_official 16:4f6df64750bd 98 }
mbed_official 16:4f6df64750bd 99
mbed_official 16:4f6df64750bd 100 void USBHAL::configureDevice(void) {
mbed_official 16:4f6df64750bd 101 // Not needed
mbed_official 16:4f6df64750bd 102 }
mbed_official 16:4f6df64750bd 103
mbed_official 16:4f6df64750bd 104 void USBHAL::unconfigureDevice(void) {
mbed_official 16:4f6df64750bd 105 // Not needed
mbed_official 16:4f6df64750bd 106 }
mbed_official 16:4f6df64750bd 107
mbed_official 16:4f6df64750bd 108 void USBHAL::setAddress(uint8_t address) {
mbed_official 16:4f6df64750bd 109 OTG_FS->DREGS.DCFG |= (address << 4);
mbed_official 16:4f6df64750bd 110 EP0write(0, 0);
mbed_official 16:4f6df64750bd 111 }
mbed_official 16:4f6df64750bd 112
mbed_official 16:4f6df64750bd 113 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
mbed_official 16:4f6df64750bd 114 uint32_t flags) {
mbed_official 16:4f6df64750bd 115 uint32_t epIndex = endpoint >> 1;
mbed_official 16:4f6df64750bd 116
mbed_official 16:4f6df64750bd 117 uint32_t type;
mbed_official 16:4f6df64750bd 118 switch (endpoint) {
mbed_official 16:4f6df64750bd 119 case EP0IN:
mbed_official 16:4f6df64750bd 120 case EP0OUT:
mbed_official 16:4f6df64750bd 121 type = 0;
mbed_official 16:4f6df64750bd 122 break;
mbed_official 16:4f6df64750bd 123 case EPISO_IN:
mbed_official 16:4f6df64750bd 124 case EPISO_OUT:
mbed_official 16:4f6df64750bd 125 type = 1;
mbed_official 16:4f6df64750bd 126 case EPBULK_IN:
mbed_official 16:4f6df64750bd 127 case EPBULK_OUT:
mbed_official 16:4f6df64750bd 128 type = 2;
mbed_official 16:4f6df64750bd 129 break;
mbed_official 16:4f6df64750bd 130 case EPINT_IN:
mbed_official 16:4f6df64750bd 131 case EPINT_OUT:
mbed_official 16:4f6df64750bd 132 type = 3;
mbed_official 16:4f6df64750bd 133 break;
mbed_official 16:4f6df64750bd 134 }
mbed_official 16:4f6df64750bd 135
mbed_official 16:4f6df64750bd 136 // Generic in or out EP controls
mbed_official 16:4f6df64750bd 137 uint32_t control = (maxPacket << 0) | // Packet size
mbed_official 16:4f6df64750bd 138 (1 << 15) | // Active endpoint
mbed_official 16:4f6df64750bd 139 (type << 18); // Endpoint type
mbed_official 16:4f6df64750bd 140
mbed_official 16:4f6df64750bd 141 if (endpoint & 0x1) { // In Endpoint
mbed_official 16:4f6df64750bd 142 // Set up the Tx FIFO
mbed_official 16:4f6df64750bd 143 if (endpoint == EP0IN) {
mbed_official 16:4f6df64750bd 144 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
mbed_official 16:4f6df64750bd 145 (bufferEnd << 0);
mbed_official 16:4f6df64750bd 146 }
mbed_official 16:4f6df64750bd 147 else {
mbed_official 16:4f6df64750bd 148 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
mbed_official 16:4f6df64750bd 149 (bufferEnd << 0);
mbed_official 16:4f6df64750bd 150 }
mbed_official 16:4f6df64750bd 151 bufferEnd += maxPacket >> 2;
mbed_official 16:4f6df64750bd 152
mbed_official 16:4f6df64750bd 153 // Set the In EP specific control settings
mbed_official 16:4f6df64750bd 154 if (endpoint != EP0IN) {
mbed_official 16:4f6df64750bd 155 control |= (1 << 28); // SD0PID
mbed_official 16:4f6df64750bd 156 }
mbed_official 16:4f6df64750bd 157
mbed_official 16:4f6df64750bd 158 control |= (epIndex << 22) | // TxFIFO index
mbed_official 16:4f6df64750bd 159 (1 << 27); // SNAK
mbed_official 16:4f6df64750bd 160 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
mbed_official 16:4f6df64750bd 161
mbed_official 16:4f6df64750bd 162 // Unmask the interrupt
mbed_official 16:4f6df64750bd 163 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
mbed_official 16:4f6df64750bd 164 }
mbed_official 16:4f6df64750bd 165 else { // Out endpoint
mbed_official 16:4f6df64750bd 166 // Set the out EP specific control settings
mbed_official 16:4f6df64750bd 167 control |= (1 << 26); // CNAK
mbed_official 16:4f6df64750bd 168 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
mbed_official 16:4f6df64750bd 169
mbed_official 16:4f6df64750bd 170 // Unmask the interrupt
mbed_official 16:4f6df64750bd 171 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
mbed_official 16:4f6df64750bd 172 }
mbed_official 16:4f6df64750bd 173 return true;
mbed_official 16:4f6df64750bd 174 }
mbed_official 16:4f6df64750bd 175
mbed_official 16:4f6df64750bd 176 // read setup packet
mbed_official 16:4f6df64750bd 177 void USBHAL::EP0setup(uint8_t *buffer) {
mbed_official 16:4f6df64750bd 178 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
mbed_official 16:4f6df64750bd 179 }
mbed_official 16:4f6df64750bd 180
mbed_official 16:4f6df64750bd 181 void USBHAL::EP0readStage(void) {
mbed_official 16:4f6df64750bd 182 }
mbed_official 16:4f6df64750bd 183
mbed_official 16:4f6df64750bd 184 void USBHAL::EP0read(void) {
mbed_official 16:4f6df64750bd 185 }
mbed_official 16:4f6df64750bd 186
mbed_official 16:4f6df64750bd 187 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
mbed_official 16:4f6df64750bd 188 uint32_t* buffer32 = (uint32_t *) buffer;
mbed_official 16:4f6df64750bd 189 uint32_t length = rxFifoCount;
mbed_official 16:4f6df64750bd 190 for (uint32_t i = 0; i < length; i += 4) {
mbed_official 16:4f6df64750bd 191 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
mbed_official 16:4f6df64750bd 192 }
mbed_official 16:4f6df64750bd 193
mbed_official 16:4f6df64750bd 194 rxFifoCount = 0;
mbed_official 16:4f6df64750bd 195 return length;
mbed_official 16:4f6df64750bd 196 }
mbed_official 16:4f6df64750bd 197
mbed_official 16:4f6df64750bd 198 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
mbed_official 16:4f6df64750bd 199 endpointWrite(0, buffer, size);
mbed_official 16:4f6df64750bd 200 }
mbed_official 16:4f6df64750bd 201
mbed_official 16:4f6df64750bd 202 void USBHAL::EP0getWriteResult(void) {
mbed_official 16:4f6df64750bd 203 }
mbed_official 16:4f6df64750bd 204
mbed_official 16:4f6df64750bd 205 void USBHAL::EP0stall(void) {
mbed_official 16:4f6df64750bd 206 // If we stall the out endpoint here then we have problems transferring
mbed_official 16:4f6df64750bd 207 // and setup requests after the (stalled) get device qualifier requests.
mbed_official 16:4f6df64750bd 208 // TODO: Find out if this is correct behavior, or whether we are doing
mbed_official 16:4f6df64750bd 209 // something else wrong
mbed_official 16:4f6df64750bd 210 stallEndpoint(EP0IN);
mbed_official 16:4f6df64750bd 211 // stallEndpoint(EP0OUT);
mbed_official 16:4f6df64750bd 212 }
mbed_official 16:4f6df64750bd 213
mbed_official 16:4f6df64750bd 214 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
mbed_official 16:4f6df64750bd 215 uint32_t epIndex = endpoint >> 1;
mbed_official 16:4f6df64750bd 216 uint32_t size = (1 << 19) | // 1 packet
mbed_official 16:4f6df64750bd 217 (maximumSize << 0); // Packet size
mbed_official 16:4f6df64750bd 218 // if (endpoint == EP0OUT) {
mbed_official 16:4f6df64750bd 219 size |= (1 << 29); // 1 setup packet
mbed_official 16:4f6df64750bd 220 // }
mbed_official 16:4f6df64750bd 221 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
mbed_official 16:4f6df64750bd 222 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
mbed_official 16:4f6df64750bd 223 (1 << 26); // Clear NAK
mbed_official 16:4f6df64750bd 224
mbed_official 16:4f6df64750bd 225 epComplete &= ~(1 << endpoint);
mbed_official 16:4f6df64750bd 226 return EP_PENDING;
mbed_official 16:4f6df64750bd 227 }
mbed_official 16:4f6df64750bd 228
mbed_official 16:4f6df64750bd 229 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
mbed_official 16:4f6df64750bd 230 if (!(epComplete & (1 << endpoint))) {
mbed_official 16:4f6df64750bd 231 return EP_PENDING;
mbed_official 16:4f6df64750bd 232 }
mbed_official 16:4f6df64750bd 233
mbed_official 16:4f6df64750bd 234 uint32_t* buffer32 = (uint32_t *) buffer;
mbed_official 16:4f6df64750bd 235 uint32_t length = rxFifoCount;
mbed_official 16:4f6df64750bd 236 for (uint32_t i = 0; i < length; i += 4) {
mbed_official 16:4f6df64750bd 237 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
mbed_official 16:4f6df64750bd 238 }
mbed_official 16:4f6df64750bd 239 rxFifoCount = 0;
mbed_official 16:4f6df64750bd 240 *bytesRead = length;
mbed_official 16:4f6df64750bd 241 return EP_COMPLETED;
mbed_official 16:4f6df64750bd 242 }
mbed_official 16:4f6df64750bd 243
mbed_official 16:4f6df64750bd 244 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
mbed_official 16:4f6df64750bd 245 uint32_t epIndex = endpoint >> 1;
mbed_official 16:4f6df64750bd 246 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
mbed_official 16:4f6df64750bd 247 (size << 0); // Size of packet
mbed_official 16:4f6df64750bd 248 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
mbed_official 16:4f6df64750bd 249 (1 << 26); // CNAK
mbed_official 16:4f6df64750bd 250 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
mbed_official 16:4f6df64750bd 251
mbed_official 16:4f6df64750bd 252 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
mbed_official 16:4f6df64750bd 253
mbed_official 16:4f6df64750bd 254 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
mbed_official 16:4f6df64750bd 255 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
mbed_official 16:4f6df64750bd 256 }
mbed_official 16:4f6df64750bd 257
mbed_official 16:4f6df64750bd 258 epComplete &= ~(1 << endpoint);
mbed_official 16:4f6df64750bd 259
mbed_official 16:4f6df64750bd 260 return EP_PENDING;
mbed_official 16:4f6df64750bd 261 }
mbed_official 16:4f6df64750bd 262
mbed_official 16:4f6df64750bd 263 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
mbed_official 16:4f6df64750bd 264 if (epComplete & (1 << endpoint)) {
mbed_official 16:4f6df64750bd 265 epComplete &= ~(1 << endpoint);
mbed_official 16:4f6df64750bd 266 return EP_COMPLETED;
mbed_official 16:4f6df64750bd 267 }
mbed_official 16:4f6df64750bd 268
mbed_official 16:4f6df64750bd 269 return EP_PENDING;
mbed_official 16:4f6df64750bd 270 }
mbed_official 16:4f6df64750bd 271
mbed_official 16:4f6df64750bd 272 void USBHAL::stallEndpoint(uint8_t endpoint) {
mbed_official 16:4f6df64750bd 273 if (endpoint & 0x1) { // In EP
mbed_official 16:4f6df64750bd 274 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
mbed_official 16:4f6df64750bd 275 (1 << 21); // Stall
mbed_official 16:4f6df64750bd 276 }
mbed_official 16:4f6df64750bd 277 else { // Out EP
mbed_official 16:4f6df64750bd 278 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
mbed_official 16:4f6df64750bd 279 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
mbed_official 16:4f6df64750bd 280 (1 << 21); // Stall
mbed_official 16:4f6df64750bd 281 }
mbed_official 16:4f6df64750bd 282 }
mbed_official 16:4f6df64750bd 283
mbed_official 16:4f6df64750bd 284 void USBHAL::unstallEndpoint(uint8_t endpoint) {
mbed_official 16:4f6df64750bd 285
mbed_official 16:4f6df64750bd 286 }
mbed_official 16:4f6df64750bd 287
mbed_official 16:4f6df64750bd 288 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
mbed_official 16:4f6df64750bd 289 return false;
mbed_official 16:4f6df64750bd 290 }
mbed_official 16:4f6df64750bd 291
mbed_official 16:4f6df64750bd 292 void USBHAL::remoteWakeup(void) {
mbed_official 16:4f6df64750bd 293 }
mbed_official 16:4f6df64750bd 294
mbed_official 16:4f6df64750bd 295
mbed_official 16:4f6df64750bd 296 void USBHAL::_usbisr(void) {
mbed_official 16:4f6df64750bd 297 instance->usbisr();
mbed_official 16:4f6df64750bd 298 }
mbed_official 16:4f6df64750bd 299
mbed_official 16:4f6df64750bd 300
mbed_official 16:4f6df64750bd 301 void USBHAL::usbisr(void) {
mbed_official 16:4f6df64750bd 302 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
mbed_official 16:4f6df64750bd 303 // Set SNAK bits
mbed_official 16:4f6df64750bd 304 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
mbed_official 16:4f6df64750bd 305 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
mbed_official 16:4f6df64750bd 306 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
mbed_official 16:4f6df64750bd 307 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
mbed_official 16:4f6df64750bd 308
mbed_official 16:4f6df64750bd 309 OTG_FS->DREGS.DIEPMSK = (1 << 0);
mbed_official 16:4f6df64750bd 310
mbed_official 16:4f6df64750bd 311 bufferEnd = 0;
mbed_official 16:4f6df64750bd 312
mbed_official 16:4f6df64750bd 313 // Set the receive FIFO size
mbed_official 16:4f6df64750bd 314 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
mbed_official 16:4f6df64750bd 315 bufferEnd += rxFifoSize >> 2;
mbed_official 16:4f6df64750bd 316
mbed_official 16:4f6df64750bd 317 // Create the endpoints, and wait for setup packets on out EP0
mbed_official 16:4f6df64750bd 318 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
mbed_official 16:4f6df64750bd 319 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
mbed_official 16:4f6df64750bd 320 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
mbed_official 16:4f6df64750bd 321
mbed_official 16:4f6df64750bd 322 OTG_FS->GREGS.GINTSTS = (1 << 12);
mbed_official 16:4f6df64750bd 323 }
mbed_official 16:4f6df64750bd 324
mbed_official 16:4f6df64750bd 325 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
mbed_official 16:4f6df64750bd 326 uint32_t status = OTG_FS->GREGS.GRXSTSP;
mbed_official 16:4f6df64750bd 327
mbed_official 16:4f6df64750bd 328 uint32_t endpoint = (status & 0xF) << 1;
mbed_official 16:4f6df64750bd 329 uint32_t length = (status >> 4) & 0x7FF;
mbed_official 16:4f6df64750bd 330 uint32_t type = (status >> 17) & 0xF;
mbed_official 16:4f6df64750bd 331
mbed_official 16:4f6df64750bd 332 rxFifoCount = length;
mbed_official 16:4f6df64750bd 333
mbed_official 16:4f6df64750bd 334 if (type == 0x6) {
mbed_official 16:4f6df64750bd 335 // Setup packet
mbed_official 16:4f6df64750bd 336 for (uint32_t i=0; i<length; i+=4) {
mbed_official 16:4f6df64750bd 337 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
mbed_official 16:4f6df64750bd 338 }
mbed_official 16:4f6df64750bd 339 rxFifoCount = 0;
mbed_official 16:4f6df64750bd 340 }
mbed_official 16:4f6df64750bd 341
mbed_official 16:4f6df64750bd 342 if (type == 0x4) {
mbed_official 16:4f6df64750bd 343 // Setup complete
mbed_official 16:4f6df64750bd 344 EP0setupCallback();
mbed_official 16:4f6df64750bd 345 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
mbed_official 16:4f6df64750bd 346 }
mbed_official 16:4f6df64750bd 347
mbed_official 16:4f6df64750bd 348 if (type == 0x2) {
mbed_official 16:4f6df64750bd 349 // Out packet
mbed_official 16:4f6df64750bd 350 if (endpoint == EP0OUT) {
mbed_official 16:4f6df64750bd 351 EP0out();
mbed_official 16:4f6df64750bd 352 }
mbed_official 16:4f6df64750bd 353 else {
mbed_official 16:4f6df64750bd 354 epComplete |= (1 << endpoint);
mbed_official 16:4f6df64750bd 355 if ((instance->*(epCallback[endpoint - 2]))()) {
mbed_official 16:4f6df64750bd 356 epComplete &= (1 << endpoint);
mbed_official 16:4f6df64750bd 357 }
mbed_official 16:4f6df64750bd 358 }
mbed_official 16:4f6df64750bd 359 }
mbed_official 16:4f6df64750bd 360
mbed_official 16:4f6df64750bd 361 for (uint32_t i=0; i<rxFifoCount; i+=4) {
mbed_official 16:4f6df64750bd 362 (void) OTG_FS->FIFO[0][0];
mbed_official 16:4f6df64750bd 363 }
mbed_official 16:4f6df64750bd 364 OTG_FS->GREGS.GINTSTS = (1 << 4);
mbed_official 16:4f6df64750bd 365 }
mbed_official 16:4f6df64750bd 366
mbed_official 16:4f6df64750bd 367 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
mbed_official 16:4f6df64750bd 368 // Loop through the in endpoints
mbed_official 16:4f6df64750bd 369 for (uint32_t i=0; i<4; i++) {
mbed_official 16:4f6df64750bd 370 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
mbed_official 16:4f6df64750bd 371
mbed_official 16:4f6df64750bd 372 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
mbed_official 16:4f6df64750bd 373 // If the Tx FIFO is empty on EP0 we need to send a further
mbed_official 16:4f6df64750bd 374 // packet, so call EP0in()
mbed_official 16:4f6df64750bd 375 if (i == 0) {
mbed_official 16:4f6df64750bd 376 EP0in();
mbed_official 16:4f6df64750bd 377 }
mbed_official 16:4f6df64750bd 378 // Clear the interrupt
mbed_official 16:4f6df64750bd 379 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
mbed_official 16:4f6df64750bd 380 // Stop firing Tx empty interrupts
mbed_official 16:4f6df64750bd 381 // Will get turned on again if another write is called
mbed_official 16:4f6df64750bd 382 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
mbed_official 16:4f6df64750bd 383 }
mbed_official 16:4f6df64750bd 384
mbed_official 16:4f6df64750bd 385 // If the transfer is complete
mbed_official 16:4f6df64750bd 386 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
mbed_official 16:4f6df64750bd 387 epComplete |= (1 << (1 + (i << 1)));
mbed_official 16:4f6df64750bd 388 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
mbed_official 16:4f6df64750bd 389 }
mbed_official 16:4f6df64750bd 390 }
mbed_official 16:4f6df64750bd 391 }
mbed_official 16:4f6df64750bd 392 OTG_FS->GREGS.GINTSTS = (1 << 18);
mbed_official 16:4f6df64750bd 393 }
mbed_official 16:4f6df64750bd 394
mbed_official 16:4f6df64750bd 395 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
mbed_official 16:4f6df64750bd 396 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
mbed_official 16:4f6df64750bd 397 OTG_FS->GREGS.GINTSTS = (1 << 3);
mbed_official 16:4f6df64750bd 398 }
mbed_official 16:4f6df64750bd 399 }
mbed_official 16:4f6df64750bd 400
mbed_official 16:4f6df64750bd 401
mbed_official 16:4f6df64750bd 402 #endif