Ned Konz / Mbed 2 deprecated Multi_WS2811_test

Test program for my Multi_WS2811 library that started out as a fork of heroic/WS2811. My library uses hardware DMA on the FRDM-KL25Z to drive up to 16 strings of WS2811 or WS2812 LEDs in parallel.

Dependencies:   Multi_WS2811 mbed MMA8451Q

Fork of WS2811 by Heroic Robotics

NOTE: I have accidentally pushed changes for another fork of this program that I used in the recent Georgetown Carnival Power Tool Races. When I get some time, I will restore the test program to its original glory.

You can see my power tool racer (Nevermore's Revenge) here

/media/uploads/bikeNomad/img_0482.jpg

This tests my FRDM-KL25Z multi-string WS2811/WS2812 library. It uses the accelerometer to change the rainbow phase on two strings of LEDs as well as the touch sense to change brightness.

A video of this program in operation is here.

Here is the library that I developed to run the LEDs:

Import libraryMulti_WS2811

Library allowing up to 16 strings of 60 WS2811 or WS2812 LEDs to be driven from a single FRDM-KL25Z board. Uses hardware DMA to do a full 800 KHz rate without much CPU burden.

Last commit 13 Jun 2015 by Ned Konz

WS2811.cpp@30:52e9205a8059, 2014-01-04 (annotated)

Committer:
bikeNomad
Date:
Sat Jan 04 00:32:16 2014 +0000
Revision:
30:52e9205a8059
Parent:
29:a76075c853ee 
used TPM0 to time guard time at end of DMA.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bikeNomad 23:33df42ff2541 1 // 800 KHz WS2811 driver driving potentially many LED strings.
bikeNomad 23:33df42ff2541 2 // Uses 3-phase DMA
bikeNomad 23:33df42ff2541 3 // 16K SRAM less stack, etc.
bikeNomad 23:33df42ff2541 4 //
bikeNomad 23:33df42ff2541 5 // Per LED: 3 bytes (malloc'd) for RGB data
bikeNomad 23:33df42ff2541 6 //
bikeNomad 23:33df42ff2541 7 // Per LED strip / per LED
bikeNomad 23:33df42ff2541 8 // 96 bytes (static) for bit data
bikeNomad 23:33df42ff2541 9 // + 96 bytes (static) for ones data
bikeNomad 23:33df42ff2541 10 // = 192 bytes
bikeNomad 23:33df42ff2541 11 //
bikeNomad 23:33df42ff2541 12 // 40 LEDs max per string = 7680 bytes static
bikeNomad 23:33df42ff2541 13 //
bikeNomad 23:33df42ff2541 14 // 40 LEDs: 7680 + 40*3 = 7800 bytes
bikeNomad 23:33df42ff2541 15 // 80 LEDs: 7680 + 80*3 = 7920 bytes
bikeNomad 23:33df42ff2541 16
bikeNomad 23:33df42ff2541 17 #include "MKL25Z4.h"
bikeNomad 23:33df42ff2541 18 #include "LedStrip.h"
bikeNomad 23:33df42ff2541 19 #include "WS2811.h"
bikeNomad 23:33df42ff2541 20
bikeNomad 23:33df42ff2541 21 //
bikeNomad 23:33df42ff2541 22 // Configuration
bikeNomad 23:33df42ff2541 23 //
bikeNomad 23:33df42ff2541 24
bikeNomad 23:33df42ff2541 25 // Define MONITOR_TPM0_PWM as non-zero to monitor PWM timing on PTD0 and PTD1
bikeNomad 23:33df42ff2541 26 // PTD0 TPM0/CH0 PWM_1 J2/06
bikeNomad 23:33df42ff2541 27 // PTD1 TPM0/CH1 PWM_2 J2/12 (also LED_BLUE)
bikeNomad 23:33df42ff2541 28 #define MONITOR_TPM0_PWM 0
bikeNomad 23:33df42ff2541 29
bikeNomad 23:33df42ff2541 30 // define DEBUG_PIN to identify a pin in PORTD used for debug output
bikeNomad 30:52e9205a8059 31 // #define DEBUG_PIN 4 /* PTD4 debugOut */
bikeNomad 23:33df42ff2541 32
bikeNomad 23:33df42ff2541 33 #ifdef DEBUG_PIN
bikeNomad 23:33df42ff2541 34 #define DEBUG 1
bikeNomad 23:33df42ff2541 35 #endif
bikeNomad 23:33df42ff2541 36
bikeNomad 23:33df42ff2541 37 #if DEBUG
bikeNomad 23:33df42ff2541 38 #define DEBUG_MASK (1<<DEBUG_PIN)
bikeNomad 23:33df42ff2541 39 #define RESET_DEBUG (IO_GPIO->PDOR &= ~DEBUG_MASK)
bikeNomad 23:33df42ff2541 40 #define SET_DEBUG (IO_GPIO->PDOR |= DEBUG_MASK)
bikeNomad 23:33df42ff2541 41 #else
bikeNomad 23:33df42ff2541 42 #define DEBUG_MASK 0
bikeNomad 23:33df42ff2541 43 #define RESET_DEBUG (void)0
bikeNomad 23:33df42ff2541 44 #define SET_DEBUG (void)0
bikeNomad 23:33df42ff2541 45 #endif
bikeNomad 23:33df42ff2541 46
bikeNomad 23:33df42ff2541 47 static PORT_Type volatile * const IO_PORT = PORTD;
bikeNomad 23:33df42ff2541 48 static GPIO_Type volatile * const IO_GPIO = PTD;
bikeNomad 23:33df42ff2541 49
bikeNomad 23:33df42ff2541 50 // 48 MHz clock, no prescaling.
bikeNomad 23:33df42ff2541 51 #define NSEC_TO_TICKS(nsec) ((nsec)*48/1000)
bikeNomad 30:52e9205a8059 52 #define USEC_TO_TICKS(usec) ((usec)*48)
bikeNomad 23:33df42ff2541 53 static const uint32_t CLK_NSEC = 1250;
bikeNomad 23:33df42ff2541 54 static const uint32_t tpm_period = NSEC_TO_TICKS(CLK_NSEC);
bikeNomad 29:a76075c853ee 55 static const uint32_t tpm_p0_period = NSEC_TO_TICKS(250);
bikeNomad 29:a76075c853ee 56 static const uint32_t tpm_p1_period = NSEC_TO_TICKS(650);
bikeNomad 30:52e9205a8059 57 static const uint32_t guardtime_period = USEC_TO_TICKS(55); // guardtime minimum 50 usec.
bikeNomad 23:33df42ff2541 58
bikeNomad 25:751c89f7e654 59 enum DMA_MUX_SRC {
bikeNomad 23:33df42ff2541 60 DMA_MUX_SRC_TPM0_CH_0 = 24,
bikeNomad 23:33df42ff2541 61 DMA_MUX_SRC_TPM0_CH_1,
bikeNomad 23:33df42ff2541 62 DMA_MUX_SRC_TPM0_Overflow = 54,
bikeNomad 23:33df42ff2541 63 };
bikeNomad 23:33df42ff2541 64
bikeNomad 25:751c89f7e654 65 enum DMA_CHAN {
bikeNomad 23:33df42ff2541 66 DMA_CHAN_START = 0,
bikeNomad 23:33df42ff2541 67 DMA_CHAN_0_LOW = 1,
bikeNomad 23:33df42ff2541 68 DMA_CHAN_1_LOW = 2,
bikeNomad 23:33df42ff2541 69 N_DMA_CHANNELS
bikeNomad 23:33df42ff2541 70 };
bikeNomad 23:33df42ff2541 71
bikeNomad 30:52e9205a8059 72 volatile bool WS2811::dma_done = true;
bikeNomad 23:33df42ff2541 73
bikeNomad 23:33df42ff2541 74 // class static
bikeNomad 23:33df42ff2541 75 bool WS2811::initialized = false;
bikeNomad 23:33df42ff2541 76
bikeNomad 23:33df42ff2541 77 // class static
bikeNomad 23:33df42ff2541 78 uint32_t WS2811::enabledPins = 0;
bikeNomad 23:33df42ff2541 79
bikeNomad 23:33df42ff2541 80 #define WORD_ALIGNED __attribute__ ((aligned(4)))
bikeNomad 23:33df42ff2541 81
bikeNomad 23:33df42ff2541 82 #define DMA_LEADING_ZEROS 2
bikeNomad 23:33df42ff2541 83 #define BITS_PER_RGB 24
bikeNomad 23:33df42ff2541 84 #define DMA_TRAILING_ZEROS 1
bikeNomad 23:33df42ff2541 85
bikeNomad 25:751c89f7e654 86 static struct {
bikeNomad 23:33df42ff2541 87 uint32_t start_t1_low[ DMA_LEADING_ZEROS ];
bikeNomad 23:33df42ff2541 88 uint32_t dmaWords[ BITS_PER_RGB * MAX_LEDS_PER_STRIP ];
bikeNomad 23:33df42ff2541 89 uint32_t trailing_zeros_1[ DMA_TRAILING_ZEROS ];
bikeNomad 23:33df42ff2541 90
bikeNomad 23:33df42ff2541 91 uint32_t start_t0_high[ DMA_LEADING_ZEROS - 1 ];
bikeNomad 23:33df42ff2541 92 uint32_t allOnes[ BITS_PER_RGB * MAX_LEDS_PER_STRIP ];
bikeNomad 23:33df42ff2541 93 uint32_t trailing_zeros_2[ DMA_TRAILING_ZEROS + 1 ];
bikeNomad 23:33df42ff2541 94 } dmaData WORD_ALIGNED;
bikeNomad 23:33df42ff2541 95
bikeNomad 25:751c89f7e654 96 // class static
bikeNomad 23:33df42ff2541 97 void WS2811::hw_init()
bikeNomad 23:33df42ff2541 98 {
bikeNomad 23:33df42ff2541 99 if (initialized) return;
bikeNomad 23:33df42ff2541 100
bikeNomad 23:33df42ff2541 101 dma_data_init();
bikeNomad 23:33df42ff2541 102 clock_init();
bikeNomad 23:33df42ff2541 103 dma_init();
bikeNomad 23:33df42ff2541 104 io_init();
bikeNomad 23:33df42ff2541 105 tpm_init();
bikeNomad 23:33df42ff2541 106
bikeNomad 23:33df42ff2541 107 initialized = true;
bikeNomad 30:52e9205a8059 108
bikeNomad 30:52e9205a8059 109 SET_DEBUG;
bikeNomad 30:52e9205a8059 110 RESET_DEBUG;
bikeNomad 23:33df42ff2541 111 }
bikeNomad 23:33df42ff2541 112
bikeNomad 23:33df42ff2541 113 // class static
bikeNomad 23:33df42ff2541 114 void WS2811::dma_data_init()
bikeNomad 23:33df42ff2541 115 {
bikeNomad 23:33df42ff2541 116 memset(dmaData.allOnes, 0xFF, sizeof(dmaData.allOnes));
bikeNomad 23:33df42ff2541 117
bikeNomad 23:33df42ff2541 118 #if DEBUG
bikeNomad 23:33df42ff2541 119 for (unsigned i = 0; i < BITS_PER_RGB * MAX_LEDS_PER_STRIP; i++)
bikeNomad 23:33df42ff2541 120 dmaData.dmaWords[i] = DEBUG_MASK;
bikeNomad 23:33df42ff2541 121 #endif
bikeNomad 23:33df42ff2541 122 }
bikeNomad 23:33df42ff2541 123
bikeNomad 23:33df42ff2541 124 // class static
bikeNomad 23:33df42ff2541 125
bikeNomad 23:33df42ff2541 126 /// Enable PORTD, DMA and TPM0 clocking
bikeNomad 23:33df42ff2541 127 void WS2811::clock_init()
bikeNomad 23:33df42ff2541 128 {
bikeNomad 23:33df42ff2541 129 SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
bikeNomad 23:33df42ff2541 130 SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK | SIM_SCGC6_TPM0_MASK; // Enable clock to DMA mux and TPM0
bikeNomad 23:33df42ff2541 131 SIM->SCGC7 |= SIM_SCGC7_DMA_MASK; // Enable clock to DMA
bikeNomad 23:33df42ff2541 132
bikeNomad 23:33df42ff2541 133 SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
bikeNomad 23:33df42ff2541 134 }
bikeNomad 23:33df42ff2541 135
bikeNomad 23:33df42ff2541 136 // class static
bikeNomad 23:33df42ff2541 137
bikeNomad 23:33df42ff2541 138 /// Configure GPIO output pins
bikeNomad 23:33df42ff2541 139 void WS2811::io_init()
bikeNomad 23:33df42ff2541 140 {
bikeNomad 23:33df42ff2541 141 uint32_t m = 1;
bikeNomad 25:751c89f7e654 142 for (uint32_t i = 0; i < 32; i++) {
bikeNomad 23:33df42ff2541 143 // set up each pin
bikeNomad 25:751c89f7e654 144 if (m & enabledPins) {
bikeNomad 23:33df42ff2541 145 IO_PORT->PCR[i] = PORT_PCR_MUX(1) // GPIO
bikeNomad 23:33df42ff2541 146 | PORT_PCR_DSE_MASK; // high drive strength
bikeNomad 23:33df42ff2541 147 }
bikeNomad 23:33df42ff2541 148 m <<= 1;
bikeNomad 23:33df42ff2541 149 }
bikeNomad 23:33df42ff2541 150
bikeNomad 23:33df42ff2541 151 IO_GPIO->PDDR |= enabledPins; // set as outputs
bikeNomad 23:33df42ff2541 152
bikeNomad 23:33df42ff2541 153 #if MONITOR_TPM0_PWM
bikeNomad 23:33df42ff2541 154 // PTD0 CH0 monitor: TPM0, high drive strength
bikeNomad 23:33df42ff2541 155 IO_PORT->PCR[0] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
bikeNomad 23:33df42ff2541 156 // PTD1 CH1 monitor: TPM0, high drive strength
bikeNomad 23:33df42ff2541 157 IO_PORT->PCR[1] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
bikeNomad 23:33df42ff2541 158 IO_GPIO->PDDR |= 3; // set as outputs
bikeNomad 23:33df42ff2541 159 IO_GPIO->PDOR &= ~(enabledPins | 3); // initially low
bikeNomad 23:33df42ff2541 160 #else
bikeNomad 23:33df42ff2541 161 IO_GPIO->PDOR &= ~enabledPins; // initially low
bikeNomad 23:33df42ff2541 162 #endif
bikeNomad 23:33df42ff2541 163
bikeNomad 23:33df42ff2541 164 #if DEBUG
bikeNomad 23:33df42ff2541 165 IO_PORT->PCR[DEBUG_PIN] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
bikeNomad 23:33df42ff2541 166 IO_GPIO->PDDR |= DEBUG_MASK;
bikeNomad 23:33df42ff2541 167 IO_GPIO->PDOR &= ~DEBUG_MASK;
bikeNomad 23:33df42ff2541 168 #endif
bikeNomad 23:33df42ff2541 169 }
bikeNomad 23:33df42ff2541 170
bikeNomad 23:33df42ff2541 171 // class static
bikeNomad 23:33df42ff2541 172
bikeNomad 23:33df42ff2541 173 /// Configure DMA and DMAMUX
bikeNomad 23:33df42ff2541 174 void WS2811::dma_init()
bikeNomad 23:33df42ff2541 175 {
bikeNomad 23:33df42ff2541 176 // reset DMAMUX
bikeNomad 23:33df42ff2541 177 DMAMUX0->CHCFG[DMA_CHAN_START] = 0;
bikeNomad 23:33df42ff2541 178 DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = 0;
bikeNomad 23:33df42ff2541 179 DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = 0;
bikeNomad 23:33df42ff2541 180
bikeNomad 23:33df42ff2541 181 // wire our DMA event sources into the first three DMA channels
bikeNomad 23:33df42ff2541 182 // t=0: all enabled outputs go high on TPM0 overflow
bikeNomad 23:33df42ff2541 183 DMAMUX0->CHCFG[DMA_CHAN_START] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_Overflow);
bikeNomad 23:33df42ff2541 184 // t=tpm_p0_period: all of the 0 bits go low.
bikeNomad 23:33df42ff2541 185 DMAMUX0->CHCFG[DMA_CHAN_0_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_0);
bikeNomad 23:33df42ff2541 186 // t=tpm_p1_period: all outputs go low.
bikeNomad 23:33df42ff2541 187 DMAMUX0->CHCFG[DMA_CHAN_1_LOW] = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(DMA_MUX_SRC_TPM0_CH_1);
bikeNomad 20:b9d76e567637 188
bikeNomad 30:52e9205a8059 189 NVIC_SetVector(DMA0_IRQn, (uint32_t)&DMA0_IRQHandler);
bikeNomad 23:33df42ff2541 190 NVIC_EnableIRQ(DMA0_IRQn);
bikeNomad 23:33df42ff2541 191 }
bikeNomad 23:33df42ff2541 192
bikeNomad 23:33df42ff2541 193 // class static
bikeNomad 23:33df42ff2541 194
bikeNomad 23:33df42ff2541 195 /// Configure TPM0 to do two different PWM periods at 800kHz rate
bikeNomad 23:33df42ff2541 196 void WS2811::tpm_init()
bikeNomad 23:33df42ff2541 197 {
bikeNomad 23:33df42ff2541 198 // set up TPM0 for proper period (800 kHz = 1.25 usec ±600nsec)
bikeNomad 23:33df42ff2541 199 TPM_Type volatile *tpm = TPM0;
bikeNomad 23:33df42ff2541 200 tpm->SC = TPM_SC_DMA_MASK // enable DMA
bikeNomad 30:52e9205a8059 201 | TPM_SC_TOF_MASK // reset TOF flag if set
bikeNomad 23:33df42ff2541 202 | TPM_SC_CMOD(0) // disable clocks
bikeNomad 23:33df42ff2541 203 | TPM_SC_PS(0); // 48MHz / 1 = 48MHz clock
bikeNomad 23:33df42ff2541 204 tpm->MOD = tpm_period - 1; // 48MHz / 800kHz
bikeNomad 23:33df42ff2541 205
bikeNomad 23:33df42ff2541 206 // No Interrupts; High True pulses on Edge Aligned PWM
bikeNomad 23:33df42ff2541 207 tpm->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
bikeNomad 23:33df42ff2541 208 tpm->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK | TPM_CnSC_DMA_MASK;
bikeNomad 23:33df42ff2541 209
bikeNomad 30:52e9205a8059 210 // set TPM0 channel 0 for 0.35 usec (±150nsec) (0 code)
bikeNomad 23:33df42ff2541 211 // 1.25 usec * 1/3 = 417 nsec
bikeNomad 23:33df42ff2541 212 tpm->CONTROLS[0].CnV = tpm_p0_period;
bikeNomad 23:33df42ff2541 213
bikeNomad 30:52e9205a8059 214 // set TPM0 channel 1 for 0.7 usec (±150nsec) (1 code)
bikeNomad 23:33df42ff2541 215 // 1.25 usec * 2/3 = 833 nsec
bikeNomad 23:33df42ff2541 216 tpm->CONTROLS[1].CnV = tpm_p1_period;
bikeNomad 30:52e9205a8059 217
bikeNomad 30:52e9205a8059 218 NVIC_SetVector(TPM0_IRQn, (uint32_t)&TPM0_IRQHandler);
bikeNomad 30:52e9205a8059 219 NVIC_EnableIRQ(TPM0_IRQn);
bikeNomad 23:33df42ff2541 220 }
bikeNomad 23:33df42ff2541 221
bikeNomad 23:33df42ff2541 222 WS2811::WS2811(unsigned n, unsigned pinNumber)
bikeNomad 23:33df42ff2541 223 : LedStrip(n)
bikeNomad 23:33df42ff2541 224 , pinMask(1U << pinNumber)
bikeNomad 23:33df42ff2541 225 {
bikeNomad 23:33df42ff2541 226 enabledPins |= pinMask;
bikeNomad 30:52e9205a8059 227 initialized = false;
bikeNomad 23:33df42ff2541 228 }
bikeNomad 23:33df42ff2541 229
bikeNomad 23:33df42ff2541 230 // class static
bikeNomad 23:33df42ff2541 231 void WS2811::startDMA()
bikeNomad 23:33df42ff2541 232 {
bikeNomad 25:751c89f7e654 233 hw_init();
bikeNomad 30:52e9205a8059 234
bikeNomad 30:52e9205a8059 235 wait_for_dma_done();
bikeNomad 30:52e9205a8059 236 dma_done = false;
bikeNomad 25:751c89f7e654 237
bikeNomad 23:33df42ff2541 238 DMA_Type volatile * dma = DMA0;
bikeNomad 23:33df42ff2541 239 TPM_Type volatile *tpm = TPM0;
bikeNomad 23:33df42ff2541 240 uint32_t nBytes = sizeof(dmaData.start_t1_low)
bikeNomad 25:751c89f7e654 241 + sizeof(dmaData.dmaWords)
bikeNomad 25:751c89f7e654 242 + sizeof(dmaData.trailing_zeros_1);
bikeNomad 23:33df42ff2541 243
bikeNomad 30:52e9205a8059 244 tpm->SC = TPM_SC_DMA_MASK // enable DMA
bikeNomad 30:52e9205a8059 245 | TPM_SC_TOF_MASK // reset TOF flag if set
bikeNomad 30:52e9205a8059 246 | TPM_SC_CMOD(0) // disable clocks
bikeNomad 30:52e9205a8059 247 | TPM_SC_PS(0); // 48MHz / 1 = 48MHz clock
bikeNomad 30:52e9205a8059 248 tpm->MOD = tpm_period - 1; // 48MHz / 800kHz
bikeNomad 30:52e9205a8059 249
bikeNomad 23:33df42ff2541 250 tpm->CNT = tpm_p0_period - 2 ;
bikeNomad 23:33df42ff2541 251 tpm->STATUS = 0xFFFFFFFF;
bikeNomad 23:33df42ff2541 252
bikeNomad 23:33df42ff2541 253 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 23:33df42ff2541 254 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 23:33df42ff2541 255 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 23:33df42ff2541 256
bikeNomad 23:33df42ff2541 257 // t=0: all outputs go high
bikeNomad 23:33df42ff2541 258 // triggered by TPM0_Overflow
bikeNomad 23:33df42ff2541 259 // source is one word of 0 then 24 x 0xffffffff, then another 0 word
bikeNomad 23:33df42ff2541 260 dma->DMA[DMA_CHAN_START].SAR = (uint32_t)(void*)dmaData.start_t0_high;
bikeNomad 23:33df42ff2541 261 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 23:33df42ff2541 262
bikeNomad 23:33df42ff2541 263 // t=tpm_p0_period: some outputs (the 0 bits) go low.
bikeNomad 23:33df42ff2541 264 // Triggered by TPM0_CH0
bikeNomad 23:33df42ff2541 265 // Start 2 words before the actual data to avoid garbage pulses.
bikeNomad 23:33df42ff2541 266 dma->DMA[DMA_CHAN_0_LOW].SAR = (uint32_t)(void*)dmaData.start_t1_low; // set source address
bikeNomad 23:33df42ff2541 267 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 23:33df42ff2541 268
bikeNomad 23:33df42ff2541 269 // t=tpm_p1_period: all outputs go low.
bikeNomad 23:33df42ff2541 270 // Triggered by TPM0_CH1
bikeNomad 23:33df42ff2541 271 // source is constant 0x00000000 (first word of dmaWords)
bikeNomad 23:33df42ff2541 272 dma->DMA[DMA_CHAN_1_LOW].SAR = (uint32_t)(void*)dmaData.start_t1_low; // set source address
bikeNomad 23:33df42ff2541 273 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_BCR_MASK & nBytes; // length of transfer in bytes
bikeNomad 23:33df42ff2541 274
bikeNomad 25:751c89f7e654 275 dma->DMA[DMA_CHAN_0_LOW].DAR
bikeNomad 25:751c89f7e654 276 = dma->DMA[DMA_CHAN_1_LOW].DAR
bikeNomad 25:751c89f7e654 277 = dma->DMA[DMA_CHAN_START].DAR
bikeNomad 23:33df42ff2541 278 = (uint32_t)(void*)&IO_GPIO->PDOR;
bikeNomad 23:33df42ff2541 279
bikeNomad 23:33df42ff2541 280 SET_DEBUG;
bikeNomad 23:33df42ff2541 281
bikeNomad 23:33df42ff2541 282 dma->DMA[DMA_CHAN_0_LOW].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 23:33df42ff2541 283 | DMA_DCR_ERQ_MASK
bikeNomad 23:33df42ff2541 284 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 23:33df42ff2541 285 | DMA_DCR_SINC_MASK // increment source each transfer
bikeNomad 23:33df42ff2541 286 | DMA_DCR_CS_MASK
bikeNomad 23:33df42ff2541 287 | DMA_DCR_SSIZE(0) // 32-bit source transfers
bikeNomad 23:33df42ff2541 288 | DMA_DCR_DSIZE(0); // 32-bit destination transfers
bikeNomad 23:33df42ff2541 289
bikeNomad 23:33df42ff2541 290 dma->DMA[DMA_CHAN_1_LOW].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 23:33df42ff2541 291 | DMA_DCR_ERQ_MASK
bikeNomad 23:33df42ff2541 292 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 23:33df42ff2541 293 | DMA_DCR_CS_MASK
bikeNomad 23:33df42ff2541 294 | DMA_DCR_SSIZE(0) // 32-bit source transfers
bikeNomad 23:33df42ff2541 295 | DMA_DCR_DSIZE(0); // 32-bit destination transfers
bikeNomad 23:33df42ff2541 296
bikeNomad 23:33df42ff2541 297 dma->DMA[DMA_CHAN_START].DCR = DMA_DCR_EINT_MASK // enable interrupt on end of transfer
bikeNomad 23:33df42ff2541 298 | DMA_DCR_ERQ_MASK
bikeNomad 23:33df42ff2541 299 | DMA_DCR_D_REQ_MASK // clear ERQ on end of transfer
bikeNomad 23:33df42ff2541 300 | DMA_DCR_SINC_MASK // increment source each transfer
bikeNomad 23:33df42ff2541 301 | DMA_DCR_CS_MASK
bikeNomad 23:33df42ff2541 302 | DMA_DCR_SSIZE(0) // 32-bit source transfers
bikeNomad 23:33df42ff2541 303 | DMA_DCR_DSIZE(0);
bikeNomad 23:33df42ff2541 304
bikeNomad 23:33df42ff2541 305 tpm->SC |= TPM_SC_CMOD(1); // enable internal clocking
bikeNomad 23:33df42ff2541 306 }
bikeNomad 23:33df42ff2541 307
bikeNomad 23:33df42ff2541 308 void WS2811::writePixel(unsigned n, uint8_t *p)
bikeNomad 23:33df42ff2541 309 {
bikeNomad 23:33df42ff2541 310 uint32_t *dest = dmaData.dmaWords + n * BITS_PER_RGB;
bikeNomad 23:33df42ff2541 311 writeByte(*p++, pinMask, dest + 0); // G
bikeNomad 23:33df42ff2541 312 writeByte(*p++, pinMask, dest + 8); // R
bikeNomad 23:33df42ff2541 313 writeByte(*p, pinMask, dest + 16); // B
bikeNomad 23:33df42ff2541 314 }
bikeNomad 23:33df42ff2541 315
bikeNomad 23:33df42ff2541 316 // class static
bikeNomad 23:33df42ff2541 317 void WS2811::writeByte(uint8_t byte, uint32_t mask, uint32_t *dest)
bikeNomad 23:33df42ff2541 318 {
bikeNomad 25:751c89f7e654 319 for (uint8_t bm = 0x80; bm; bm >>= 1) {
bikeNomad 23:33df42ff2541 320 // MSBit first
bikeNomad 23:33df42ff2541 321 if (byte & bm)
bikeNomad 23:33df42ff2541 322 *dest |= mask;
bikeNomad 23:33df42ff2541 323 else
bikeNomad 23:33df42ff2541 324 *dest &= ~mask;
bikeNomad 23:33df42ff2541 325 dest++;
bikeNomad 23:33df42ff2541 326 }
bikeNomad 23:33df42ff2541 327 }
bikeNomad 23:33df42ff2541 328
bikeNomad 23:33df42ff2541 329 void WS2811::begin()
bikeNomad 23:33df42ff2541 330 {
bikeNomad 23:33df42ff2541 331 blank();
bikeNomad 23:33df42ff2541 332 show();
bikeNomad 23:33df42ff2541 333 }
bikeNomad 23:33df42ff2541 334
bikeNomad 23:33df42ff2541 335 void WS2811::blank()
bikeNomad 23:33df42ff2541 336 {
bikeNomad 23:33df42ff2541 337 memset(pixels, 0x00, numPixelBytes());
bikeNomad 23:33df42ff2541 338
bikeNomad 23:33df42ff2541 339 #if DEBUG
bikeNomad 23:33df42ff2541 340 for (unsigned i = DMA_LEADING_ZEROS; i < DMA_LEADING_ZEROS + BITS_PER_RGB; i++)
bikeNomad 25:751c89f7e654 341 dmaData.dmaWords[i] = DEBUG_MASK;
bikeNomad 23:33df42ff2541 342 #else
bikeNomad 23:33df42ff2541 343 memset(dmaData.dmaWords, 0x00, sizeof(dmaData.dmaWords));
bikeNomad 23:33df42ff2541 344 #endif
bikeNomad 23:33df42ff2541 345 }
bikeNomad 23:33df42ff2541 346
bikeNomad 23:33df42ff2541 347 void WS2811::show()
bikeNomad 23:33df42ff2541 348 {
bikeNomad 23:33df42ff2541 349
bikeNomad 23:33df42ff2541 350 uint16_t i, n = numPixels(); // 3 bytes per LED
bikeNomad 23:33df42ff2541 351 uint8_t *p = pixels;
bikeNomad 23:33df42ff2541 352
bikeNomad 25:751c89f7e654 353 for (i=0; i<n; i++ ) {
bikeNomad 23:33df42ff2541 354 writePixel(i, p);
bikeNomad 23:33df42ff2541 355 p += 3;
bikeNomad 23:33df42ff2541 356 }
bikeNomad 23:33df42ff2541 357 }
bikeNomad 23:33df42ff2541 358
bikeNomad 23:33df42ff2541 359 extern "C" void DMA0_IRQHandler()
bikeNomad 23:33df42ff2541 360 {
bikeNomad 30:52e9205a8059 361 DMA_Type volatile *dma = DMA0;
bikeNomad 30:52e9205a8059 362 TPM_Type volatile *tpm = TPM0;
bikeNomad 23:33df42ff2541 363
bikeNomad 30:52e9205a8059 364 uint32_t db;
bikeNomad 23:33df42ff2541 365
bikeNomad 23:33df42ff2541 366 db = dma->DMA[DMA_CHAN_0_LOW].DSR_BCR;
bikeNomad 25:751c89f7e654 367 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 30:52e9205a8059 368 dma->DMA[DMA_CHAN_0_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 23:33df42ff2541 369 }
bikeNomad 23:33df42ff2541 370
bikeNomad 23:33df42ff2541 371 db = dma->DMA[DMA_CHAN_1_LOW].DSR_BCR;
bikeNomad 25:751c89f7e654 372 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 23:33df42ff2541 373 dma->DMA[DMA_CHAN_1_LOW].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 30:52e9205a8059 374 }
bikeNomad 30:52e9205a8059 375
bikeNomad 30:52e9205a8059 376 db = dma->DMA[DMA_CHAN_START].DSR_BCR;
bikeNomad 30:52e9205a8059 377 if (db & DMA_DSR_BCR_DONE_MASK) {
bikeNomad 30:52e9205a8059 378 dma->DMA[DMA_CHAN_START].DSR_BCR = DMA_DSR_BCR_DONE_MASK; // clear/reset DMA status
bikeNomad 23:33df42ff2541 379 }
bikeNomad 30:52e9205a8059 380
bikeNomad 30:52e9205a8059 381 tpm->SC = TPM_SC_TOF_MASK; // reset TOF flag; disable internal clocking
bikeNomad 30:52e9205a8059 382
bikeNomad 30:52e9205a8059 383 SET_DEBUG;
bikeNomad 30:52e9205a8059 384
bikeNomad 30:52e9205a8059 385 // set TPM0 to interrrupt after guardtime
bikeNomad 30:52e9205a8059 386 tpm->MOD = guardtime_period - 1; // 48MHz * 55 usec
bikeNomad 30:52e9205a8059 387 tpm->CNT = 0;
bikeNomad 30:52e9205a8059 388 tpm->SC = TPM_SC_PS(0) // 48MHz / 1 = 48MHz clock
bikeNomad 30:52e9205a8059 389 | TPM_SC_TOIE_MASK // enable interrupts
bikeNomad 30:52e9205a8059 390 | TPM_SC_CMOD(1); // and internal clocking
bikeNomad 23:33df42ff2541 391 }
bikeNomad 23:33df42ff2541 392
bikeNomad 30:52e9205a8059 393 extern "C" void TPM0_IRQHandler()
bikeNomad 30:52e9205a8059 394 {
bikeNomad 30:52e9205a8059 395 TPM0->SC = 0; // disable internal clocking
bikeNomad 30:52e9205a8059 396 TPM0->SC = TPM_SC_TOF_MASK;
bikeNomad 30:52e9205a8059 397 RESET_DEBUG;
bikeNomad 30:52e9205a8059 398 WS2811::dma_done = true;
bikeNomad 30:52e9205a8059 399 }