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core_cm7.h
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00001 /**************************************************************************//** 00002 * @file core_cm7.h 00003 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 00004 * @version V5.0.2 00005 * @date 13. February 2017 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM7_H_GENERIC 00032 #define __CORE_CM7_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M7 00060 @{ 00061 */ 00062 00063 /* CMSIS CM7 definitions */ 00064 #define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ 00065 #define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ 00066 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ 00067 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00068 00069 #define __CORTEX_M (7U) /*!< Cortex-M Core */ 00070 00071 /** __FPU_USED indicates whether an FPU is used or not. 00072 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00073 */ 00074 #if defined ( __CC_ARM ) 00075 #if defined __TARGET_FPU_VFP 00076 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00077 #define __FPU_USED 1U 00078 #else 00079 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00080 #define __FPU_USED 0U 00081 #endif 00082 #else 00083 #define __FPU_USED 0U 00084 #endif 00085 00086 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00087 #if defined __ARM_PCS_VFP 00088 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00089 #define __FPU_USED 1U 00090 #else 00091 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00092 #define __FPU_USED 0U 00093 #endif 00094 #else 00095 #define __FPU_USED 0U 00096 #endif 00097 00098 #elif defined ( __GNUC__ ) 00099 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00101 #define __FPU_USED 1U 00102 #else 00103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00104 #define __FPU_USED 0U 00105 #endif 00106 #else 00107 #define __FPU_USED 0U 00108 #endif 00109 00110 #elif defined ( __ICCARM__ ) 00111 #if defined __ARMVFP__ 00112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00113 #define __FPU_USED 1U 00114 #else 00115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00116 #define __FPU_USED 0U 00117 #endif 00118 #else 00119 #define __FPU_USED 0U 00120 #endif 00121 00122 #elif defined ( __TI_ARM__ ) 00123 #if defined __TI_VFP_SUPPORT__ 00124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00125 #define __FPU_USED 1U 00126 #else 00127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00128 #define __FPU_USED 0U 00129 #endif 00130 #else 00131 #define __FPU_USED 0U 00132 #endif 00133 00134 #elif defined ( __TASKING__ ) 00135 #if defined __FPU_VFP__ 00136 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00137 #define __FPU_USED 1U 00138 #else 00139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00140 #define __FPU_USED 0U 00141 #endif 00142 #else 00143 #define __FPU_USED 0U 00144 #endif 00145 00146 #elif defined ( __CSMC__ ) 00147 #if ( __CSMC__ & 0x400U) 00148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00149 #define __FPU_USED 1U 00150 #else 00151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00152 #define __FPU_USED 0U 00153 #endif 00154 #else 00155 #define __FPU_USED 0U 00156 #endif 00157 00158 #endif 00159 00160 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00161 00162 00163 #ifdef __cplusplus 00164 } 00165 #endif 00166 00167 #endif /* __CORE_CM7_H_GENERIC */ 00168 00169 #ifndef __CMSIS_GENERIC 00170 00171 #ifndef __CORE_CM7_H_DEPENDANT 00172 #define __CORE_CM7_H_DEPENDANT 00173 00174 #ifdef __cplusplus 00175 extern "C" { 00176 #endif 00177 00178 /* check device defines and use defaults */ 00179 #if defined __CHECK_DEVICE_DEFINES 00180 #ifndef __CM7_REV 00181 #define __CM7_REV 0x0000U 00182 #warning "__CM7_REV not defined in device header file; using default!" 00183 #endif 00184 00185 #ifndef __FPU_PRESENT 00186 #define __FPU_PRESENT 0U 00187 #warning "__FPU_PRESENT not defined in device header file; using default!" 00188 #endif 00189 00190 #ifndef __MPU_PRESENT 00191 #define __MPU_PRESENT 0U 00192 #warning "__MPU_PRESENT not defined in device header file; using default!" 00193 #endif 00194 00195 #ifndef __ICACHE_PRESENT 00196 #define __ICACHE_PRESENT 0U 00197 #warning "__ICACHE_PRESENT not defined in device header file; using default!" 00198 #endif 00199 00200 #ifndef __DCACHE_PRESENT 00201 #define __DCACHE_PRESENT 0U 00202 #warning "__DCACHE_PRESENT not defined in device header file; using default!" 00203 #endif 00204 00205 #ifndef __DTCM_PRESENT 00206 #define __DTCM_PRESENT 0U 00207 #warning "__DTCM_PRESENT not defined in device header file; using default!" 00208 #endif 00209 00210 #ifndef __NVIC_PRIO_BITS 00211 #define __NVIC_PRIO_BITS 3U 00212 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00213 #endif 00214 00215 #ifndef __Vendor_SysTickConfig 00216 #define __Vendor_SysTickConfig 0U 00217 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00218 #endif 00219 #endif 00220 00221 /* IO definitions (access restrictions to peripheral registers) */ 00222 /** 00223 \defgroup CMSIS_glob_defs CMSIS Global Defines 00224 00225 <strong>IO Type Qualifiers</strong> are used 00226 \li to specify the access to peripheral variables. 00227 \li for automatic generation of peripheral register debug information. 00228 */ 00229 #ifdef __cplusplus 00230 #define __I volatile /*!< Defines 'read only' permissions */ 00231 #else 00232 #define __I volatile const /*!< Defines 'read only' permissions */ 00233 #endif 00234 #define __O volatile /*!< Defines 'write only' permissions */ 00235 #define __IO volatile /*!< Defines 'read / write' permissions */ 00236 00237 /* following defines should be used for structure members */ 00238 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00239 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00240 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00241 00242 /*@} end of group Cortex_M7 */ 00243 00244 00245 00246 /******************************************************************************* 00247 * Register Abstraction 00248 Core Register contain: 00249 - Core Register 00250 - Core NVIC Register 00251 - Core SCB Register 00252 - Core SysTick Register 00253 - Core Debug Register 00254 - Core MPU Register 00255 - Core FPU Register 00256 ******************************************************************************/ 00257 /** 00258 \defgroup CMSIS_core_register Defines and Type Definitions 00259 \brief Type definitions and defines for Cortex-M processor based devices. 00260 */ 00261 00262 /** 00263 \ingroup CMSIS_core_register 00264 \defgroup CMSIS_CORE Status and Control Registers 00265 \brief Core Register type definitions. 00266 @{ 00267 */ 00268 00269 /** 00270 \brief Union type to access the Application Program Status Register (APSR). 00271 */ 00272 typedef union 00273 { 00274 struct 00275 { 00276 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00277 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00278 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00279 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00280 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00281 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00282 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00283 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00284 } b; /*!< Structure used for bit access */ 00285 uint32_t w; /*!< Type used for word access */ 00286 } APSR_Type; 00287 00288 /* APSR Register Definitions */ 00289 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00290 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00291 00292 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00293 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00294 00295 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00296 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00297 00298 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00299 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00300 00301 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00302 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00303 00304 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 00305 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00306 00307 00308 /** 00309 \brief Union type to access the Interrupt Program Status Register (IPSR). 00310 */ 00311 typedef union 00312 { 00313 struct 00314 { 00315 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00316 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00317 } b; /*!< Structure used for bit access */ 00318 uint32_t w; /*!< Type used for word access */ 00319 } IPSR_Type; 00320 00321 /* IPSR Register Definitions */ 00322 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00323 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00324 00325 00326 /** 00327 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00328 */ 00329 typedef union 00330 { 00331 struct 00332 { 00333 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00334 uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 00335 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 00336 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00337 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00338 uint32_t T:1; /*!< bit: 24 Thumb bit */ 00339 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 00340 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00341 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00342 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00343 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00344 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00345 } b; /*!< Structure used for bit access */ 00346 uint32_t w; /*!< Type used for word access */ 00347 } xPSR_Type; 00348 00349 /* xPSR Register Definitions */ 00350 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00351 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00352 00353 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00354 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00355 00356 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00357 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00358 00359 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00360 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00361 00362 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00363 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00364 00365 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 00366 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 00367 00368 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00369 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00370 00371 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 00372 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00373 00374 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 00375 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 00376 00377 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00378 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00379 00380 00381 /** 00382 \brief Union type to access the Control Registers (CONTROL). 00383 */ 00384 typedef union 00385 { 00386 struct 00387 { 00388 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00389 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00390 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00391 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00392 } b; /*!< Structure used for bit access */ 00393 uint32_t w; /*!< Type used for word access */ 00394 } CONTROL_Type; 00395 00396 /* CONTROL Register Definitions */ 00397 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 00398 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00399 00400 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00401 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00402 00403 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00404 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00405 00406 /*@} end of group CMSIS_CORE */ 00407 00408 00409 /** 00410 \ingroup CMSIS_core_register 00411 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00412 \brief Type definitions for the NVIC Registers 00413 @{ 00414 */ 00415 00416 /** 00417 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00418 */ 00419 typedef struct 00420 { 00421 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00422 uint32_t RESERVED0[24U]; 00423 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00424 uint32_t RSERVED1[24U]; 00425 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00426 uint32_t RESERVED2[24U]; 00427 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00428 uint32_t RESERVED3[24U]; 00429 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00430 uint32_t RESERVED4[56U]; 00431 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00432 uint32_t RESERVED5[644U]; 00433 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00434 } NVIC_Type; 00435 00436 /* Software Triggered Interrupt Register Definitions */ 00437 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00438 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00439 00440 /*@} end of group CMSIS_NVIC */ 00441 00442 00443 /** 00444 \ingroup CMSIS_core_register 00445 \defgroup CMSIS_SCB System Control Block (SCB) 00446 \brief Type definitions for the System Control Block Registers 00447 @{ 00448 */ 00449 00450 /** 00451 \brief Structure type to access the System Control Block (SCB). 00452 */ 00453 typedef struct 00454 { 00455 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00456 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00457 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00458 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00459 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00460 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00461 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00462 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00463 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00464 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00465 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00466 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00467 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00468 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00469 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00470 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00471 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00472 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00473 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00474 uint32_t RESERVED0[1U]; 00475 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 00476 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 00477 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 00478 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 00479 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00480 uint32_t RESERVED3[93U]; 00481 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 00482 uint32_t RESERVED4[15U]; 00483 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 00484 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 00485 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ 00486 uint32_t RESERVED5[1U]; 00487 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 00488 uint32_t RESERVED6[1U]; 00489 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 00490 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 00491 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 00492 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 00493 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 00494 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 00495 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 00496 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 00497 uint32_t RESERVED7[6U]; 00498 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ 00499 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ 00500 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 00501 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 00502 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 00503 uint32_t RESERVED8[1U]; 00504 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ 00505 } SCB_Type; 00506 00507 /* SCB CPUID Register Definitions */ 00508 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00509 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00510 00511 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00512 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00513 00514 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00515 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00516 00517 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00518 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00519 00520 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00521 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00522 00523 /* SCB Interrupt Control State Register Definitions */ 00524 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00525 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00526 00527 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00528 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00529 00530 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00531 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00532 00533 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00534 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00535 00536 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00537 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00538 00539 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00540 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00541 00542 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00543 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00544 00545 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00546 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00547 00548 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00549 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00550 00551 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00552 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00553 00554 /* SCB Vector Table Offset Register Definitions */ 00555 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00556 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00557 00558 /* SCB Application Interrupt and Reset Control Register Definitions */ 00559 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00560 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00561 00562 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00563 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00564 00565 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00566 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00567 00568 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00569 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00570 00571 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00572 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00573 00574 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00575 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00576 00577 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 00578 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 00579 00580 /* SCB System Control Register Definitions */ 00581 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00582 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00583 00584 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00585 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00586 00587 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00588 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00589 00590 /* SCB Configuration Control Register Definitions */ 00591 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ 00592 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ 00593 00594 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ 00595 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ 00596 00597 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ 00598 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ 00599 00600 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00601 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00602 00603 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00604 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00605 00606 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00607 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00608 00609 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00610 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00611 00612 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00613 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00614 00615 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 00616 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 00617 00618 /* SCB System Handler Control and State Register Definitions */ 00619 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00620 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00621 00622 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00623 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00624 00625 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00626 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00627 00628 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00629 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00630 00631 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00632 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00633 00634 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00635 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00636 00637 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00638 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00639 00640 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00641 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00642 00643 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00644 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00645 00646 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00647 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00648 00649 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00650 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00651 00652 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00653 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00654 00655 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00656 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00657 00658 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00659 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00660 00661 /* SCB Configurable Fault Status Register Definitions */ 00662 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00663 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00664 00665 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00666 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00667 00668 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00669 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00670 00671 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00672 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00673 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00674 00675 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 00676 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 00677 00678 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00679 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00680 00681 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00682 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00683 00684 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00685 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00686 00687 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00688 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00689 00690 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00691 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00692 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00693 00694 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 00695 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 00696 00697 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00698 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00699 00700 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00701 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00702 00703 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00704 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00705 00706 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00707 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00708 00709 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00710 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00711 00712 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00713 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00714 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00715 00716 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00717 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00718 00719 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00720 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00721 00722 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00723 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00724 00725 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00726 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00727 00728 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00729 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00730 00731 /* SCB Hard Fault Status Register Definitions */ 00732 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00733 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00734 00735 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00736 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00737 00738 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00739 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00740 00741 /* SCB Debug Fault Status Register Definitions */ 00742 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00743 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00744 00745 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00746 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00747 00748 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00749 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00750 00751 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00752 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00753 00754 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00755 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00756 00757 /* SCB Cache Level ID Register Definitions */ 00758 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ 00759 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 00760 00761 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ 00762 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ 00763 00764 /* SCB Cache Type Register Definitions */ 00765 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ 00766 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 00767 00768 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ 00769 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 00770 00771 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ 00772 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 00773 00774 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ 00775 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 00776 00777 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ 00778 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 00779 00780 /* SCB Cache Size ID Register Definitions */ 00781 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 00782 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 00783 00784 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 00785 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 00786 00787 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 00788 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 00789 00790 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 00791 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 00792 00793 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ 00794 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 00795 00796 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ 00797 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 00798 00799 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ 00800 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 00801 00802 /* SCB Cache Size Selection Register Definitions */ 00803 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ 00804 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 00805 00806 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ 00807 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 00808 00809 /* SCB Software Triggered Interrupt Register Definitions */ 00810 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ 00811 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 00812 00813 /* SCB D-Cache Invalidate by Set-way Register Definitions */ 00814 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ 00815 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ 00816 00817 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ 00818 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ 00819 00820 /* SCB D-Cache Clean by Set-way Register Definitions */ 00821 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ 00822 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ 00823 00824 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ 00825 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ 00826 00827 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 00828 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ 00829 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ 00830 00831 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ 00832 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ 00833 00834 /* Instruction Tightly-Coupled Memory Control Register Definitions */ 00835 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ 00836 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ 00837 00838 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ 00839 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ 00840 00841 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ 00842 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ 00843 00844 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ 00845 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ 00846 00847 /* Data Tightly-Coupled Memory Control Register Definitions */ 00848 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ 00849 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ 00850 00851 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ 00852 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ 00853 00854 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ 00855 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ 00856 00857 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ 00858 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ 00859 00860 /* AHBP Control Register Definitions */ 00861 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ 00862 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ 00863 00864 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ 00865 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ 00866 00867 /* L1 Cache Control Register Definitions */ 00868 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ 00869 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ 00870 00871 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ 00872 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ 00873 00874 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ 00875 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ 00876 00877 /* AHBS Control Register Definitions */ 00878 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ 00879 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ 00880 00881 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ 00882 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ 00883 00884 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ 00885 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ 00886 00887 /* Auxiliary Bus Fault Status Register Definitions */ 00888 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ 00889 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ 00890 00891 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ 00892 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ 00893 00894 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ 00895 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ 00896 00897 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ 00898 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ 00899 00900 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ 00901 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ 00902 00903 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ 00904 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ 00905 00906 /*@} end of group CMSIS_SCB */ 00907 00908 00909 /** 00910 \ingroup CMSIS_core_register 00911 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00912 \brief Type definitions for the System Control and ID Register not in the SCB 00913 @{ 00914 */ 00915 00916 /** 00917 \brief Structure type to access the System Control and ID Register not in the SCB. 00918 */ 00919 typedef struct 00920 { 00921 uint32_t RESERVED0[1U]; 00922 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00923 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00924 } SCnSCB_Type; 00925 00926 /* Interrupt Controller Type Register Definitions */ 00927 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 00928 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00929 00930 /* Auxiliary Control Register Definitions */ 00931 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ 00932 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ 00933 00934 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ 00935 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ 00936 00937 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ 00938 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ 00939 00940 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 00941 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00942 00943 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 00944 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00945 00946 /*@} end of group CMSIS_SCnotSCB */ 00947 00948 00949 /** 00950 \ingroup CMSIS_core_register 00951 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00952 \brief Type definitions for the System Timer Registers. 00953 @{ 00954 */ 00955 00956 /** 00957 \brief Structure type to access the System Timer (SysTick). 00958 */ 00959 typedef struct 00960 { 00961 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00962 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00963 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00964 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00965 } SysTick_Type; 00966 00967 /* SysTick Control / Status Register Definitions */ 00968 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00969 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00970 00971 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00972 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00973 00974 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00975 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00976 00977 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00978 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00979 00980 /* SysTick Reload Register Definitions */ 00981 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00982 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00983 00984 /* SysTick Current Register Definitions */ 00985 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00986 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00987 00988 /* SysTick Calibration Register Definitions */ 00989 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00990 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00991 00992 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00993 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00994 00995 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00996 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00997 00998 /*@} end of group CMSIS_SysTick */ 00999 01000 01001 /** 01002 \ingroup CMSIS_core_register 01003 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 01004 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 01005 @{ 01006 */ 01007 01008 /** 01009 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 01010 */ 01011 typedef struct 01012 { 01013 __OM union 01014 { 01015 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 01016 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 01017 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 01018 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 01019 uint32_t RESERVED0[864U]; 01020 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 01021 uint32_t RESERVED1[15U]; 01022 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 01023 uint32_t RESERVED2[15U]; 01024 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 01025 uint32_t RESERVED3[29U]; 01026 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 01027 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 01028 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 01029 uint32_t RESERVED4[43U]; 01030 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 01031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 01032 uint32_t RESERVED5[6U]; 01033 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 01034 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 01035 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 01036 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 01037 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 01038 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 01039 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 01040 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 01041 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 01042 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 01043 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 01044 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 01045 } ITM_Type; 01046 01047 /* ITM Trace Privilege Register Definitions */ 01048 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 01049 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 01050 01051 /* ITM Trace Control Register Definitions */ 01052 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 01053 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 01054 01055 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 01056 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 01057 01058 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 01059 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 01060 01061 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 01062 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 01063 01064 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 01065 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 01066 01067 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 01068 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 01069 01070 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 01071 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 01072 01073 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 01074 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 01075 01076 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 01077 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 01078 01079 /* ITM Integration Write Register Definitions */ 01080 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 01081 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 01082 01083 /* ITM Integration Read Register Definitions */ 01084 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 01085 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 01086 01087 /* ITM Integration Mode Control Register Definitions */ 01088 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 01089 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 01090 01091 /* ITM Lock Status Register Definitions */ 01092 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 01093 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 01094 01095 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 01096 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 01097 01098 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 01099 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 01100 01101 /*@}*/ /* end of group CMSIS_ITM */ 01102 01103 01104 /** 01105 \ingroup CMSIS_core_register 01106 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 01107 \brief Type definitions for the Data Watchpoint and Trace (DWT) 01108 @{ 01109 */ 01110 01111 /** 01112 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 01113 */ 01114 typedef struct 01115 { 01116 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 01117 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 01118 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 01119 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 01120 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 01121 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 01122 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 01123 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 01124 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 01125 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 01126 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 01127 uint32_t RESERVED0[1U]; 01128 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 01129 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 01130 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 01131 uint32_t RESERVED1[1U]; 01132 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 01133 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 01134 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 01135 uint32_t RESERVED2[1U]; 01136 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 01137 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 01138 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 01139 uint32_t RESERVED3[981U]; 01140 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 01141 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 01142 } DWT_Type; 01143 01144 /* DWT Control Register Definitions */ 01145 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 01146 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 01147 01148 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 01149 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 01150 01151 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 01152 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 01153 01154 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 01155 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 01156 01157 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 01158 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 01159 01160 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 01161 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 01162 01163 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 01164 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 01165 01166 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 01167 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 01168 01169 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 01170 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 01171 01172 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 01173 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 01174 01175 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 01176 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 01177 01178 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 01179 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 01180 01181 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 01182 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 01183 01184 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 01185 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 01186 01187 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 01188 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 01189 01190 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 01191 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 01192 01193 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 01194 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 01195 01196 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 01197 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 01198 01199 /* DWT CPI Count Register Definitions */ 01200 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 01201 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 01202 01203 /* DWT Exception Overhead Count Register Definitions */ 01204 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 01205 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 01206 01207 /* DWT Sleep Count Register Definitions */ 01208 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 01209 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 01210 01211 /* DWT LSU Count Register Definitions */ 01212 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 01213 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 01214 01215 /* DWT Folded-instruction Count Register Definitions */ 01216 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 01217 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01218 01219 /* DWT Comparator Mask Register Definitions */ 01220 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 01221 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 01222 01223 /* DWT Comparator Function Register Definitions */ 01224 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 01225 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01226 01227 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 01228 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 01229 01230 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 01231 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 01232 01233 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 01234 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01235 01236 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 01237 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 01238 01239 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 01240 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 01241 01242 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 01243 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 01244 01245 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 01246 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 01247 01248 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 01249 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 01250 01251 /*@}*/ /* end of group CMSIS_DWT */ 01252 01253 01254 /** 01255 \ingroup CMSIS_core_register 01256 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01257 \brief Type definitions for the Trace Port Interface (TPI) 01258 @{ 01259 */ 01260 01261 /** 01262 \brief Structure type to access the Trace Port Interface Register (TPI). 01263 */ 01264 typedef struct 01265 { 01266 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01267 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01268 uint32_t RESERVED0[2U]; 01269 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01270 uint32_t RESERVED1[55U]; 01271 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01272 uint32_t RESERVED2[131U]; 01273 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01274 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01275 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01276 uint32_t RESERVED3[759U]; 01277 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 01278 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01279 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01280 uint32_t RESERVED4[1U]; 01281 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01282 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01283 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01284 uint32_t RESERVED5[39U]; 01285 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01286 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01287 uint32_t RESERVED7[8U]; 01288 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01289 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01290 } TPI_Type; 01291 01292 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01293 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 01294 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01295 01296 /* TPI Selected Pin Protocol Register Definitions */ 01297 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01298 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01299 01300 /* TPI Formatter and Flush Status Register Definitions */ 01301 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01302 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01303 01304 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01305 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01306 01307 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01308 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01309 01310 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01311 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01312 01313 /* TPI Formatter and Flush Control Register Definitions */ 01314 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01315 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01316 01317 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 01318 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01319 01320 /* TPI TRIGGER Register Definitions */ 01321 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 01322 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01323 01324 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01325 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 01326 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01327 01328 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 01329 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01330 01331 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 01332 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01333 01334 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 01335 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01336 01337 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 01338 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01339 01340 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 01341 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01342 01343 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 01344 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01345 01346 /* TPI ITATBCTR2 Register Definitions */ 01347 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ 01348 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 01349 01350 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01351 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 01352 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01353 01354 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 01355 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01356 01357 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 01358 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01359 01360 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 01361 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01362 01363 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 01364 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01365 01366 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 01367 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01368 01369 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 01370 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01371 01372 /* TPI ITATBCTR0 Register Definitions */ 01373 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ 01374 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 01375 01376 /* TPI Integration Mode Control Register Definitions */ 01377 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 01378 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01379 01380 /* TPI DEVID Register Definitions */ 01381 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01382 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01383 01384 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01385 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01386 01387 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01388 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01389 01390 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 01391 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01392 01393 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 01394 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01395 01396 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 01397 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01398 01399 /* TPI DEVTYPE Register Definitions */ 01400 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ 01401 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01402 01403 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ 01404 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01405 01406 /*@}*/ /* end of group CMSIS_TPI */ 01407 01408 01409 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01410 /** 01411 \ingroup CMSIS_core_register 01412 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01413 \brief Type definitions for the Memory Protection Unit (MPU) 01414 @{ 01415 */ 01416 01417 /** 01418 \brief Structure type to access the Memory Protection Unit (MPU). 01419 */ 01420 typedef struct 01421 { 01422 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01423 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01424 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01425 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01426 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01427 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01428 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01429 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01430 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01431 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01432 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01433 } MPU_Type; 01434 01435 /* MPU Type Register Definitions */ 01436 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01437 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01438 01439 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01440 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01441 01442 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01443 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01444 01445 /* MPU Control Register Definitions */ 01446 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01447 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01448 01449 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01450 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01451 01452 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01453 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01454 01455 /* MPU Region Number Register Definitions */ 01456 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01457 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01458 01459 /* MPU Region Base Address Register Definitions */ 01460 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 01461 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01462 01463 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 01464 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01465 01466 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 01467 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 01468 01469 /* MPU Region Attribute and Size Register Definitions */ 01470 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 01471 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01472 01473 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 01474 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01475 01476 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 01477 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01478 01479 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 01480 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01481 01482 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 01483 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01484 01485 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 01486 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01487 01488 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 01489 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01490 01491 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 01492 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01493 01494 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 01495 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01496 01497 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 01498 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 01499 01500 /*@} end of group CMSIS_MPU */ 01501 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 01502 01503 01504 /** 01505 \ingroup CMSIS_core_register 01506 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01507 \brief Type definitions for the Floating Point Unit (FPU) 01508 @{ 01509 */ 01510 01511 /** 01512 \brief Structure type to access the Floating Point Unit (FPU). 01513 */ 01514 typedef struct 01515 { 01516 uint32_t RESERVED0[1U]; 01517 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01518 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01519 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01520 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01521 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01522 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ 01523 } FPU_Type; 01524 01525 /* Floating-Point Context Control Register Definitions */ 01526 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 01527 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01528 01529 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 01530 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01531 01532 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 01533 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01534 01535 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 01536 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01537 01538 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 01539 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01540 01541 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 01542 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01543 01544 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 01545 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01546 01547 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 01548 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01549 01550 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 01551 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01552 01553 /* Floating-Point Context Address Register Definitions */ 01554 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 01555 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01556 01557 /* Floating-Point Default Status Control Register Definitions */ 01558 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 01559 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01560 01561 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 01562 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01563 01564 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 01565 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01566 01567 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 01568 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01569 01570 /* Media and FP Feature Register 0 Definitions */ 01571 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 01572 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01573 01574 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 01575 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01576 01577 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 01578 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01579 01580 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 01581 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01582 01583 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 01584 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01585 01586 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 01587 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01588 01589 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 01590 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01591 01592 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 01593 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 01594 01595 /* Media and FP Feature Register 1 Definitions */ 01596 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 01597 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01598 01599 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 01600 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01601 01602 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 01603 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01604 01605 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 01606 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 01607 01608 /* Media and FP Feature Register 2 Definitions */ 01609 01610 /*@} end of group CMSIS_FPU */ 01611 01612 01613 /** 01614 \ingroup CMSIS_core_register 01615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01616 \brief Type definitions for the Core Debug Registers 01617 @{ 01618 */ 01619 01620 /** 01621 \brief Structure type to access the Core Debug Register (CoreDebug). 01622 */ 01623 typedef struct 01624 { 01625 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01626 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01627 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01628 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01629 } CoreDebug_Type; 01630 01631 /* Debug Halting Control and Status Register Definitions */ 01632 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01633 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01634 01635 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01636 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01637 01638 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01639 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01640 01641 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01642 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01643 01644 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01645 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01646 01647 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01648 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01649 01650 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01651 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01652 01653 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01654 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01655 01656 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01657 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01658 01659 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01660 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01661 01662 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01663 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01664 01665 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01666 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01667 01668 /* Debug Core Register Selector Register Definitions */ 01669 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01670 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01671 01672 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01673 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01674 01675 /* Debug Exception and Monitor Control Register Definitions */ 01676 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01677 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01678 01679 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01680 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01681 01682 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01683 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01684 01685 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01686 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01687 01688 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01689 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01690 01691 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01692 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01693 01694 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01695 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01696 01697 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01698 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01699 01700 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01701 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01702 01703 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01704 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01705 01706 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01707 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01708 01709 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01710 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01711 01712 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01713 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01714 01715 /*@} end of group CMSIS_CoreDebug */ 01716 01717 01718 /** 01719 \ingroup CMSIS_core_register 01720 \defgroup CMSIS_core_bitfield Core register bit field macros 01721 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01722 @{ 01723 */ 01724 01725 /** 01726 \brief Mask and shift a bit field value for use in a register bit range. 01727 \param[in] field Name of the register bit field. 01728 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01729 \return Masked and shifted value. 01730 */ 01731 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01732 01733 /** 01734 \brief Mask and shift a register value to extract a bit filed value. 01735 \param[in] field Name of the register bit field. 01736 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01737 \return Masked and shifted bit field value. 01738 */ 01739 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01740 01741 /*@} end of group CMSIS_core_bitfield */ 01742 01743 01744 /** 01745 \ingroup CMSIS_core_register 01746 \defgroup CMSIS_core_base Core Definitions 01747 \brief Definitions for base addresses, unions, and structures. 01748 @{ 01749 */ 01750 01751 /* Memory mapping of Core Hardware */ 01752 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01753 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01754 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01755 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01756 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01757 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01758 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01759 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01760 01761 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01762 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01763 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01764 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01765 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01766 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01767 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01768 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01769 01770 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01771 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01772 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01773 #endif 01774 01775 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 01776 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 01777 01778 /*@} */ 01779 01780 01781 01782 /******************************************************************************* 01783 * Hardware Abstraction Layer 01784 Core Function Interface contains: 01785 - Core NVIC Functions 01786 - Core SysTick Functions 01787 - Core Debug Functions 01788 - Core Register Access Functions 01789 ******************************************************************************/ 01790 /** 01791 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01792 */ 01793 01794 01795 01796 /* ########################## NVIC functions #################################### */ 01797 /** 01798 \ingroup CMSIS_Core_FunctionInterface 01799 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01800 \brief Functions that manage interrupts and exceptions via the NVIC. 01801 @{ 01802 */ 01803 01804 #ifdef CMSIS_NVIC_VIRTUAL 01805 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01806 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01807 #endif 01808 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01809 #else 01810 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 01811 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 01812 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01813 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01814 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01815 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01816 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01817 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01818 #define NVIC_GetActive __NVIC_GetActive 01819 #define NVIC_SetPriority __NVIC_SetPriority 01820 #define NVIC_GetPriority __NVIC_GetPriority 01821 #define NVIC_SystemReset __NVIC_SystemReset 01822 #endif /* CMSIS_NVIC_VIRTUAL */ 01823 01824 #ifdef CMSIS_VECTAB_VIRTUAL 01825 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01826 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01827 #endif 01828 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01829 #else 01830 #define NVIC_SetVector __NVIC_SetVector 01831 #define NVIC_GetVector __NVIC_GetVector 01832 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01833 01834 #define NVIC_USER_IRQ_OFFSET 16 01835 01836 01837 01838 /** 01839 \brief Set Priority Grouping 01840 \details Sets the priority grouping field using the required unlock sequence. 01841 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01842 Only values from 0..7 are used. 01843 In case of a conflict between priority grouping and available 01844 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01845 \param [in] PriorityGroup Priority grouping field. 01846 */ 01847 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01848 { 01849 uint32_t reg_value; 01850 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01851 01852 reg_value = SCB->AIRCR; /* read old register configuration */ 01853 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 01854 reg_value = (reg_value | 01855 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01856 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 01857 SCB->AIRCR = reg_value; 01858 } 01859 01860 01861 /** 01862 \brief Get Priority Grouping 01863 \details Reads the priority grouping field from the NVIC Interrupt Controller. 01864 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01865 */ 01866 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 01867 { 01868 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 01869 } 01870 01871 01872 /** 01873 \brief Enable Interrupt 01874 \details Enables a device specific interrupt in the NVIC interrupt controller. 01875 \param [in] IRQn Device specific interrupt number. 01876 \note IRQn must not be negative. 01877 */ 01878 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01879 { 01880 if ((int32_t)(IRQn) >= 0) 01881 { 01882 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01883 } 01884 } 01885 01886 01887 /** 01888 \brief Get Interrupt Enable status 01889 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01890 \param [in] IRQn Device specific interrupt number. 01891 \return 0 Interrupt is not enabled. 01892 \return 1 Interrupt is enabled. 01893 \note IRQn must not be negative. 01894 */ 01895 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01896 { 01897 if ((int32_t)(IRQn) >= 0) 01898 { 01899 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01900 } 01901 else 01902 { 01903 return(0U); 01904 } 01905 } 01906 01907 01908 /** 01909 \brief Disable Interrupt 01910 \details Disables a device specific interrupt in the NVIC interrupt controller. 01911 \param [in] IRQn Device specific interrupt number. 01912 \note IRQn must not be negative. 01913 */ 01914 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01915 { 01916 if ((int32_t)(IRQn) >= 0) 01917 { 01918 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01919 __DSB(); 01920 __ISB(); 01921 } 01922 } 01923 01924 01925 /** 01926 \brief Get Pending Interrupt 01927 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01928 \param [in] IRQn Device specific interrupt number. 01929 \return 0 Interrupt status is not pending. 01930 \return 1 Interrupt status is pending. 01931 \note IRQn must not be negative. 01932 */ 01933 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01934 { 01935 if ((int32_t)(IRQn) >= 0) 01936 { 01937 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01938 } 01939 else 01940 { 01941 return(0U); 01942 } 01943 } 01944 01945 01946 /** 01947 \brief Set Pending Interrupt 01948 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01949 \param [in] IRQn Device specific interrupt number. 01950 \note IRQn must not be negative. 01951 */ 01952 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01953 { 01954 if ((int32_t)(IRQn) >= 0) 01955 { 01956 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01957 } 01958 } 01959 01960 01961 /** 01962 \brief Clear Pending Interrupt 01963 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01964 \param [in] IRQn Device specific interrupt number. 01965 \note IRQn must not be negative. 01966 */ 01967 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01968 { 01969 if ((int32_t)(IRQn) >= 0) 01970 { 01971 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01972 } 01973 } 01974 01975 01976 /** 01977 \brief Get Active Interrupt 01978 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01979 \param [in] IRQn Device specific interrupt number. 01980 \return 0 Interrupt status is not active. 01981 \return 1 Interrupt status is active. 01982 \note IRQn must not be negative. 01983 */ 01984 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01985 { 01986 if ((int32_t)(IRQn) >= 0) 01987 { 01988 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01989 } 01990 else 01991 { 01992 return(0U); 01993 } 01994 } 01995 01996 01997 /** 01998 \brief Set Interrupt Priority 01999 \details Sets the priority of a device specific interrupt or a processor exception. 02000 The interrupt number can be positive to specify a device specific interrupt, 02001 or negative to specify a processor exception. 02002 \param [in] IRQn Interrupt number. 02003 \param [in] priority Priority to set. 02004 \note The priority cannot be set for every processor exception. 02005 */ 02006 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 02007 { 02008 if ((int32_t)(IRQn) >= 0) 02009 { 02010 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02011 } 02012 else 02013 { 02014 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 02015 } 02016 } 02017 02018 02019 /** 02020 \brief Get Interrupt Priority 02021 \details Reads the priority of a device specific interrupt or a processor exception. 02022 The interrupt number can be positive to specify a device specific interrupt, 02023 or negative to specify a processor exception. 02024 \param [in] IRQn Interrupt number. 02025 \return Interrupt Priority. 02026 Value is aligned automatically to the implemented priority bits of the microcontroller. 02027 */ 02028 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 02029 { 02030 02031 if ((int32_t)(IRQn) >= 0) 02032 { 02033 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 02034 } 02035 else 02036 { 02037 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 02038 } 02039 } 02040 02041 02042 /** 02043 \brief Encode Priority 02044 \details Encodes the priority for an interrupt with the given priority group, 02045 preemptive priority value, and subpriority value. 02046 In case of a conflict between priority grouping and available 02047 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 02048 \param [in] PriorityGroup Used priority group. 02049 \param [in] PreemptPriority Preemptive priority value (starting from 0). 02050 \param [in] SubPriority Subpriority value (starting from 0). 02051 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 02052 */ 02053 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 02054 { 02055 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02056 uint32_t PreemptPriorityBits; 02057 uint32_t SubPriorityBits; 02058 02059 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02060 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02061 02062 return ( 02063 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 02064 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 02065 ); 02066 } 02067 02068 02069 /** 02070 \brief Decode Priority 02071 \details Decodes an interrupt priority value with a given priority group to 02072 preemptive priority value and subpriority value. 02073 In case of a conflict between priority grouping and available 02074 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 02075 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 02076 \param [in] PriorityGroup Used priority group. 02077 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 02078 \param [out] pSubPriority Subpriority value (starting from 0). 02079 */ 02080 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 02081 { 02082 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 02083 uint32_t PreemptPriorityBits; 02084 uint32_t SubPriorityBits; 02085 02086 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 02087 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 02088 02089 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 02090 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 02091 } 02092 02093 02094 /** 02095 \brief Set Interrupt Vector 02096 \details Sets an interrupt vector in SRAM based interrupt vector table. 02097 The interrupt number can be positive to specify a device specific interrupt, 02098 or negative to specify a processor exception. 02099 VTOR must been relocated to SRAM before. 02100 \param [in] IRQn Interrupt number 02101 \param [in] vector Address of interrupt handler function 02102 */ 02103 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 02104 { 02105 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02106 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 02107 } 02108 02109 02110 /** 02111 \brief Get Interrupt Vector 02112 \details Reads an interrupt vector from interrupt vector table. 02113 The interrupt number can be positive to specify a device specific interrupt, 02114 or negative to specify a processor exception. 02115 \param [in] IRQn Interrupt number. 02116 \return Address of interrupt handler function 02117 */ 02118 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 02119 { 02120 uint32_t *vectors = (uint32_t *)SCB->VTOR; 02121 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 02122 } 02123 02124 02125 /** 02126 \brief System Reset 02127 \details Initiates a system reset request to reset the MCU. 02128 */ 02129 __STATIC_INLINE void __NVIC_SystemReset(void) 02130 { 02131 __DSB(); /* Ensure all outstanding memory accesses included 02132 buffered write are completed before reset */ 02133 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 02134 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 02135 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 02136 __DSB(); /* Ensure completion of memory access */ 02137 02138 for(;;) /* wait until reset */ 02139 { 02140 __NOP(); 02141 } 02142 } 02143 02144 /*@} end of CMSIS_Core_NVICFunctions */ 02145 02146 02147 /* ########################## FPU functions #################################### */ 02148 /** 02149 \ingroup CMSIS_Core_FunctionInterface 02150 \defgroup CMSIS_Core_FpuFunctions FPU Functions 02151 \brief Function that provides FPU type. 02152 @{ 02153 */ 02154 02155 /** 02156 \brief get FPU type 02157 \details returns the FPU type 02158 \returns 02159 - \b 0: No FPU 02160 - \b 1: Single precision FPU 02161 - \b 2: Double + Single precision FPU 02162 */ 02163 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 02164 { 02165 uint32_t mvfr0; 02166 02167 mvfr0 = SCB->MVFR0; 02168 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) 02169 { 02170 return 2U; /* Double + Single precision FPU */ 02171 } 02172 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) 02173 { 02174 return 1U; /* Single precision FPU */ 02175 } 02176 else 02177 { 02178 return 0U; /* No FPU */ 02179 } 02180 } 02181 02182 02183 /*@} end of CMSIS_Core_FpuFunctions */ 02184 02185 02186 02187 /* ########################## Cache functions #################################### */ 02188 /** 02189 \ingroup CMSIS_Core_FunctionInterface 02190 \defgroup CMSIS_Core_CacheFunctions Cache Functions 02191 \brief Functions that configure Instruction and Data cache. 02192 @{ 02193 */ 02194 02195 /* Cache Size ID Register Macros */ 02196 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) 02197 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) 02198 02199 02200 /** 02201 \brief Enable I-Cache 02202 \details Turns on I-Cache 02203 */ 02204 __STATIC_INLINE void SCB_EnableICache (void) 02205 { 02206 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 02207 __DSB(); 02208 __ISB(); 02209 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 02210 __DSB(); 02211 __ISB(); 02212 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 02213 __DSB(); 02214 __ISB(); 02215 #endif 02216 } 02217 02218 02219 /** 02220 \brief Disable I-Cache 02221 \details Turns off I-Cache 02222 */ 02223 __STATIC_INLINE void SCB_DisableICache (void) 02224 { 02225 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 02226 __DSB(); 02227 __ISB(); 02228 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ 02229 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 02230 __DSB(); 02231 __ISB(); 02232 #endif 02233 } 02234 02235 02236 /** 02237 \brief Invalidate I-Cache 02238 \details Invalidates I-Cache 02239 */ 02240 __STATIC_INLINE void SCB_InvalidateICache (void) 02241 { 02242 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 02243 __DSB(); 02244 __ISB(); 02245 SCB->ICIALLU = 0UL; 02246 __DSB(); 02247 __ISB(); 02248 #endif 02249 } 02250 02251 02252 /** 02253 \brief Enable D-Cache 02254 \details Turns on D-Cache 02255 */ 02256 __STATIC_INLINE void SCB_EnableDCache (void) 02257 { 02258 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02259 uint32_t ccsidr; 02260 uint32_t sets; 02261 uint32_t ways; 02262 02263 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 02264 __DSB(); 02265 02266 ccsidr = SCB->CCSIDR; 02267 02268 /* invalidate D-Cache */ 02269 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02270 do { 02271 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02272 do { 02273 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 02274 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 02275 #if defined ( __CC_ARM ) 02276 __schedule_barrier(); 02277 #endif 02278 } while (ways-- != 0U); 02279 } while(sets-- != 0U); 02280 __DSB(); 02281 02282 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 02283 02284 __DSB(); 02285 __ISB(); 02286 #endif 02287 } 02288 02289 02290 /** 02291 \brief Disable D-Cache 02292 \details Turns off D-Cache 02293 */ 02294 __STATIC_INLINE void SCB_DisableDCache (void) 02295 { 02296 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02297 register uint32_t ccsidr; 02298 register uint32_t sets; 02299 register uint32_t ways; 02300 02301 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 02302 __DSB(); 02303 02304 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ 02305 __DSB(); 02306 02307 ccsidr = SCB->CCSIDR; 02308 02309 /* clean & invalidate D-Cache */ 02310 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02311 do { 02312 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02313 do { 02314 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | 02315 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); 02316 #if defined ( __CC_ARM ) 02317 __schedule_barrier(); 02318 #endif 02319 } while (ways-- != 0U); 02320 } while(sets-- != 0U); 02321 02322 __DSB(); 02323 __ISB(); 02324 #endif 02325 } 02326 02327 02328 /** 02329 \brief Invalidate D-Cache 02330 \details Invalidates D-Cache 02331 */ 02332 __STATIC_INLINE void SCB_InvalidateDCache (void) 02333 { 02334 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02335 uint32_t ccsidr; 02336 uint32_t sets; 02337 uint32_t ways; 02338 02339 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 02340 __DSB(); 02341 02342 ccsidr = SCB->CCSIDR; 02343 02344 /* invalidate D-Cache */ 02345 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02346 do { 02347 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02348 do { 02349 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 02350 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 02351 #if defined ( __CC_ARM ) 02352 __schedule_barrier(); 02353 #endif 02354 } while (ways-- != 0U); 02355 } while(sets-- != 0U); 02356 02357 __DSB(); 02358 __ISB(); 02359 #endif 02360 } 02361 02362 02363 /** 02364 \brief Clean D-Cache 02365 \details Cleans D-Cache 02366 */ 02367 __STATIC_INLINE void SCB_CleanDCache (void) 02368 { 02369 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02370 uint32_t ccsidr; 02371 uint32_t sets; 02372 uint32_t ways; 02373 02374 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 02375 __DSB(); 02376 02377 ccsidr = SCB->CCSIDR; 02378 02379 /* clean D-Cache */ 02380 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02381 do { 02382 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02383 do { 02384 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | 02385 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); 02386 #if defined ( __CC_ARM ) 02387 __schedule_barrier(); 02388 #endif 02389 } while (ways-- != 0U); 02390 } while(sets-- != 0U); 02391 02392 __DSB(); 02393 __ISB(); 02394 #endif 02395 } 02396 02397 02398 /** 02399 \brief Clean & Invalidate D-Cache 02400 \details Cleans and Invalidates D-Cache 02401 */ 02402 __STATIC_INLINE void SCB_CleanInvalidateDCache (void) 02403 { 02404 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02405 uint32_t ccsidr; 02406 uint32_t sets; 02407 uint32_t ways; 02408 02409 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 02410 __DSB(); 02411 02412 ccsidr = SCB->CCSIDR; 02413 02414 /* clean & invalidate D-Cache */ 02415 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 02416 do { 02417 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 02418 do { 02419 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | 02420 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); 02421 #if defined ( __CC_ARM ) 02422 __schedule_barrier(); 02423 #endif 02424 } while (ways-- != 0U); 02425 } while(sets-- != 0U); 02426 02427 __DSB(); 02428 __ISB(); 02429 #endif 02430 } 02431 02432 02433 /** 02434 \brief D-Cache Invalidate by address 02435 \details Invalidates D-Cache for the given address 02436 \param[in] addr address (aligned to 32-byte boundary) 02437 \param[in] dsize size of memory block (in number of bytes) 02438 */ 02439 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) 02440 { 02441 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02442 int32_t op_size = dsize; 02443 uint32_t op_addr = (uint32_t)addr; 02444 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ 02445 02446 __DSB(); 02447 02448 while (op_size > 0) { 02449 SCB->DCIMVAC = op_addr; 02450 op_addr += (uint32_t)linesize; 02451 op_size -= linesize; 02452 } 02453 02454 __DSB(); 02455 __ISB(); 02456 #endif 02457 } 02458 02459 02460 /** 02461 \brief D-Cache Clean by address 02462 \details Cleans D-Cache for the given address 02463 \param[in] addr address (aligned to 32-byte boundary) 02464 \param[in] dsize size of memory block (in number of bytes) 02465 */ 02466 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) 02467 { 02468 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02469 int32_t op_size = dsize; 02470 uint32_t op_addr = (uint32_t) addr; 02471 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ 02472 02473 __DSB(); 02474 02475 while (op_size > 0) { 02476 SCB->DCCMVAC = op_addr; 02477 op_addr += (uint32_t)linesize; 02478 op_size -= linesize; 02479 } 02480 02481 __DSB(); 02482 __ISB(); 02483 #endif 02484 } 02485 02486 02487 /** 02488 \brief D-Cache Clean and Invalidate by address 02489 \details Cleans and invalidates D_Cache for the given address 02490 \param[in] addr address (aligned to 32-byte boundary) 02491 \param[in] dsize size of memory block (in number of bytes) 02492 */ 02493 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) 02494 { 02495 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 02496 int32_t op_size = dsize; 02497 uint32_t op_addr = (uint32_t) addr; 02498 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ 02499 02500 __DSB(); 02501 02502 while (op_size > 0) { 02503 SCB->DCCIMVAC = op_addr; 02504 op_addr += (uint32_t)linesize; 02505 op_size -= linesize; 02506 } 02507 02508 __DSB(); 02509 __ISB(); 02510 #endif 02511 } 02512 02513 02514 /*@} end of CMSIS_Core_CacheFunctions */ 02515 02516 02517 02518 /* ################################## SysTick function ############################################ */ 02519 /** 02520 \ingroup CMSIS_Core_FunctionInterface 02521 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 02522 \brief Functions that configure the System. 02523 @{ 02524 */ 02525 02526 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 02527 02528 /** 02529 \brief System Tick Configuration 02530 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 02531 Counter is in free running mode to generate periodic interrupts. 02532 \param [in] ticks Number of ticks between two interrupts. 02533 \return 0 Function succeeded. 02534 \return 1 Function failed. 02535 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 02536 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 02537 must contain a vendor-specific implementation of this function. 02538 */ 02539 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 02540 { 02541 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 02542 { 02543 return (1UL); /* Reload value impossible */ 02544 } 02545 02546 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02547 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02548 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 02549 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02550 SysTick_CTRL_TICKINT_Msk | 02551 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02552 return (0UL); /* Function successful */ 02553 } 02554 02555 #endif 02556 02557 /*@} end of CMSIS_Core_SysTickFunctions */ 02558 02559 02560 02561 /* ##################################### Debug In/Output function ########################################### */ 02562 /** 02563 \ingroup CMSIS_Core_FunctionInterface 02564 \defgroup CMSIS_core_DebugFunctions ITM Functions 02565 \brief Functions that access the ITM debug interface. 02566 @{ 02567 */ 02568 02569 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02570 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02571 02572 02573 /** 02574 \brief ITM Send Character 02575 \details Transmits a character via the ITM channel 0, and 02576 \li Just returns when no debugger is connected that has booked the output. 02577 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02578 \param [in] ch Character to transmit. 02579 \returns Character to transmit. 02580 */ 02581 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02582 { 02583 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 02584 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 02585 { 02586 while (ITM->PORT[0U].u32 == 0UL) 02587 { 02588 __NOP(); 02589 } 02590 ITM->PORT[0U].u8 = (uint8_t)ch; 02591 } 02592 return (ch); 02593 } 02594 02595 02596 /** 02597 \brief ITM Receive Character 02598 \details Inputs a character via the external variable \ref ITM_RxBuffer. 02599 \return Received character. 02600 \return -1 No character pending. 02601 */ 02602 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 02603 { 02604 int32_t ch = -1; /* no character available */ 02605 02606 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 02607 { 02608 ch = ITM_RxBuffer; 02609 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02610 } 02611 02612 return (ch); 02613 } 02614 02615 02616 /** 02617 \brief ITM Check Character 02618 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02619 \return 0 No character available. 02620 \return 1 Character available. 02621 */ 02622 __STATIC_INLINE int32_t ITM_CheckChar (void) 02623 { 02624 02625 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 02626 { 02627 return (0); /* no character available */ 02628 } 02629 else 02630 { 02631 return (1); /* character available */ 02632 } 02633 } 02634 02635 /*@} end of CMSIS_core_DebugFunctions */ 02636 02637 02638 02639 02640 #ifdef __cplusplus 02641 } 02642 #endif 02643 02644 #endif /* __CORE_CM7_H_DEPENDANT */ 02645 02646 #endif /* __CMSIS_GENERIC */
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