core_cm0.h

00001 /**************************************************************************//**
00002  * @file     core_cm0.h
00003  * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
00004  * @version  V5.0.2
00005  * @date     13. February 2017
00006  ******************************************************************************/
00007 /*
00008  * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
00009  *
00010  * SPDX-License-Identifier: Apache-2.0
00011  *
00012  * Licensed under the Apache License, Version 2.0 (the License); you may
00013  * not use this file except in compliance with the License.
00014  * You may obtain a copy of the License at
00015  *
00016  * www.apache.org/licenses/LICENSE-2.0
00017  *
00018  * Unless required by applicable law or agreed to in writing, software
00019  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00020  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00021  * See the License for the specific language governing permissions and
00022  * limitations under the License.
00023  */
00024 
00025 #if   defined ( __ICCARM__ )
00026  #pragma system_include         /* treat file as system include file for MISRA check */
00027 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
00028   #pragma clang system_header   /* treat file as system include file */
00029 #endif
00030 
00031 #ifndef __CORE_CM0_H_GENERIC
00032 #define __CORE_CM0_H_GENERIC
00033 
00034 #include <stdint.h>
00035 
00036 #ifdef __cplusplus
00037  extern "C" {
00038 #endif
00039 
00040 /**
00041   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00042   CMSIS violates the following MISRA-C:2004 rules:
00043 
00044    \li Required Rule 8.5, object/function definition in header file.<br>
00045      Function definitions in header files are used to allow 'inlining'.
00046 
00047    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00048      Unions are used for effective representation of core registers.
00049 
00050    \li Advisory Rule 19.7, Function-like macro defined.<br>
00051      Function-like macros are used to allow more efficient code.
00052  */
00053 
00054 
00055 /*******************************************************************************
00056  *                 CMSIS definitions
00057  ******************************************************************************/
00058 /**
00059   \ingroup Cortex_M0
00060   @{
00061  */
00062 
00063 /*  CMSIS CM0 definitions */
00064 #define __CM0_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
00065 #define __CM0_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
00066 #define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
00067                                     __CM0_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
00068 
00069 #define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
00070 
00071 /** __FPU_USED indicates whether an FPU is used or not.
00072     This core does not support an FPU at all
00073 */
00074 #define __FPU_USED       0U
00075 
00076 #if defined ( __CC_ARM )
00077   #if defined __TARGET_FPU_VFP
00078     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00079   #endif
00080 
00081 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
00082   #if defined __ARM_PCS_VFP
00083     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00084   #endif
00085 
00086 #elif defined ( __GNUC__ )
00087   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00088     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00089   #endif
00090 
00091 #elif defined ( __ICCARM__ )
00092   #if defined __ARMVFP__
00093     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00094   #endif
00095 
00096 #elif defined ( __TI_ARM__ )
00097   #if defined __TI_VFP_SUPPORT__
00098     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00099   #endif
00100 
00101 #elif defined ( __TASKING__ )
00102   #if defined __FPU_VFP__
00103     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00104   #endif
00105 
00106 #elif defined ( __CSMC__ )
00107   #if ( __CSMC__ & 0x400U)
00108     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00109   #endif
00110 
00111 #endif
00112 
00113 #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
00114 
00115 
00116 #ifdef __cplusplus
00117 }
00118 #endif
00119 
00120 #endif /* __CORE_CM0_H_GENERIC */
00121 
00122 #ifndef __CMSIS_GENERIC
00123 
00124 #ifndef __CORE_CM0_H_DEPENDANT
00125 #define __CORE_CM0_H_DEPENDANT
00126 
00127 #ifdef __cplusplus
00128  extern "C" {
00129 #endif
00130 
00131 /* check device defines and use defaults */
00132 #if defined __CHECK_DEVICE_DEFINES
00133   #ifndef __CM0_REV
00134     #define __CM0_REV               0x0000U
00135     #warning "__CM0_REV not defined in device header file; using default!"
00136   #endif
00137 
00138   #ifndef __NVIC_PRIO_BITS
00139     #define __NVIC_PRIO_BITS          2U
00140     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00141   #endif
00142 
00143   #ifndef __Vendor_SysTickConfig
00144     #define __Vendor_SysTickConfig    0U
00145     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00146   #endif
00147 #endif
00148 
00149 /* IO definitions (access restrictions to peripheral registers) */
00150 /**
00151     \defgroup CMSIS_glob_defs CMSIS Global Defines
00152 
00153     <strong>IO Type Qualifiers</strong> are used
00154     \li to specify the access to peripheral variables.
00155     \li for automatic generation of peripheral register debug information.
00156 */
00157 #ifdef __cplusplus
00158   #define   __I     volatile             /*!< Defines 'read only' permissions */
00159 #else
00160   #define   __I     volatile const       /*!< Defines 'read only' permissions */
00161 #endif
00162 #define     __O     volatile             /*!< Defines 'write only' permissions */
00163 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
00164 
00165 /* following defines should be used for structure members */
00166 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
00167 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
00168 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
00169 
00170 /*@} end of group Cortex_M0 */
00171 
00172 
00173 
00174 /*******************************************************************************
00175  *                 Register Abstraction
00176   Core Register contain:
00177   - Core Register
00178   - Core NVIC Register
00179   - Core SCB Register
00180   - Core SysTick Register
00181  ******************************************************************************/
00182 /**
00183   \defgroup CMSIS_core_register Defines and Type Definitions
00184   \brief Type definitions and defines for Cortex-M processor based devices.
00185 */
00186 
00187 /**
00188   \ingroup    CMSIS_core_register
00189   \defgroup   CMSIS_CORE  Status and Control Registers
00190   \brief      Core Register type definitions.
00191   @{
00192  */
00193 
00194 /**
00195   \brief  Union type to access the Application Program Status Register (APSR).
00196  */
00197 typedef union
00198 {
00199   struct
00200   {
00201     uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
00202     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
00203     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
00204     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
00205     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
00206   } b;                                   /*!< Structure used for bit  access */
00207   uint32_t w;                            /*!< Type      used for word access */
00208 } APSR_Type;
00209 
00210 /* APSR Register Definitions */
00211 #define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
00212 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
00213 
00214 #define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
00215 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
00216 
00217 #define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
00218 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
00219 
00220 #define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
00221 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
00222 
00223 
00224 /**
00225   \brief  Union type to access the Interrupt Program Status Register (IPSR).
00226  */
00227 typedef union
00228 {
00229   struct
00230   {
00231     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
00232     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
00233   } b;                                   /*!< Structure used for bit  access */
00234   uint32_t w;                            /*!< Type      used for word access */
00235 } IPSR_Type;
00236 
00237 /* IPSR Register Definitions */
00238 #define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
00239 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
00240 
00241 
00242 /**
00243   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00244  */
00245 typedef union
00246 {
00247   struct
00248   {
00249     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
00250     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
00251     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
00252     uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
00253     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
00254     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
00255     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
00256     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
00257   } b;                                   /*!< Structure used for bit  access */
00258   uint32_t w;                            /*!< Type      used for word access */
00259 } xPSR_Type;
00260 
00261 /* xPSR Register Definitions */
00262 #define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
00263 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
00264 
00265 #define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
00266 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
00267 
00268 #define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
00269 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
00270 
00271 #define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
00272 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
00273 
00274 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
00275 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
00276 
00277 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
00278 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
00279 
00280 
00281 /**
00282   \brief  Union type to access the Control Registers (CONTROL).
00283  */
00284 typedef union
00285 {
00286   struct
00287   {
00288     uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
00289     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
00290     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
00291   } b;                                   /*!< Structure used for bit  access */
00292   uint32_t w;                            /*!< Type      used for word access */
00293 } CONTROL_Type;
00294 
00295 /* CONTROL Register Definitions */
00296 #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
00297 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
00298 
00299 /*@} end of group CMSIS_CORE */
00300 
00301 
00302 /**
00303   \ingroup    CMSIS_core_register
00304   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00305   \brief      Type definitions for the NVIC Registers
00306   @{
00307  */
00308 
00309 /**
00310   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00311  */
00312 typedef struct
00313 {
00314   __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
00315         uint32_t RESERVED0[31U];
00316   __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
00317         uint32_t RSERVED1[31U];
00318   __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
00319         uint32_t RESERVED2[31U];
00320   __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
00321         uint32_t RESERVED3[31U];
00322         uint32_t RESERVED4[64U];
00323   __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
00324 }  NVIC_Type;
00325 
00326 /*@} end of group CMSIS_NVIC */
00327 
00328 
00329 /**
00330   \ingroup  CMSIS_core_register
00331   \defgroup CMSIS_SCB     System Control Block (SCB)
00332   \brief    Type definitions for the System Control Block Registers
00333   @{
00334  */
00335 
00336 /**
00337   \brief  Structure type to access the System Control Block (SCB).
00338  */
00339 typedef struct
00340 {
00341   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
00342   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
00343         uint32_t RESERVED0;
00344   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
00345   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
00346   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
00347         uint32_t RESERVED1;
00348   __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
00349   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
00350 } SCB_Type;
00351 
00352 /* SCB CPUID Register Definitions */
00353 #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
00354 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00355 
00356 #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
00357 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00358 
00359 #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
00360 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00361 
00362 #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
00363 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00364 
00365 #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
00366 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
00367 
00368 /* SCB Interrupt Control State Register Definitions */
00369 #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
00370 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00371 
00372 #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
00373 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00374 
00375 #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
00376 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00377 
00378 #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
00379 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00380 
00381 #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
00382 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00383 
00384 #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
00385 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00386 
00387 #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
00388 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00389 
00390 #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
00391 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00392 
00393 #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
00394 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
00395 
00396 /* SCB Application Interrupt and Reset Control Register Definitions */
00397 #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
00398 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00399 
00400 #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
00401 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00402 
00403 #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
00404 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00405 
00406 #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
00407 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00408 
00409 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
00410 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00411 
00412 /* SCB System Control Register Definitions */
00413 #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
00414 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00415 
00416 #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
00417 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00418 
00419 #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
00420 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00421 
00422 /* SCB Configuration Control Register Definitions */
00423 #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
00424 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00425 
00426 #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
00427 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00428 
00429 /* SCB System Handler Control and State Register Definitions */
00430 #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
00431 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00432 
00433 /*@} end of group CMSIS_SCB */
00434 
00435 
00436 /**
00437   \ingroup  CMSIS_core_register
00438   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00439   \brief    Type definitions for the System Timer Registers.
00440   @{
00441  */
00442 
00443 /**
00444   \brief  Structure type to access the System Timer (SysTick).
00445  */
00446 typedef struct
00447 {
00448   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00449   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
00450   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
00451   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
00452 } SysTick_Type;
00453 
00454 /* SysTick Control / Status Register Definitions */
00455 #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
00456 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00457 
00458 #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
00459 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00460 
00461 #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
00462 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00463 
00464 #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
00465 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
00466 
00467 /* SysTick Reload Register Definitions */
00468 #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
00469 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
00470 
00471 /* SysTick Current Register Definitions */
00472 #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
00473 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
00474 
00475 /* SysTick Calibration Register Definitions */
00476 #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
00477 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00478 
00479 #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
00480 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00481 
00482 #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
00483 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
00484 
00485 /*@} end of group CMSIS_SysTick */
00486 
00487 
00488 /**
00489   \ingroup  CMSIS_core_register
00490   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
00491   \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
00492             Therefore they are not covered by the Cortex-M0 header file.
00493   @{
00494  */
00495 /*@} end of group CMSIS_CoreDebug */
00496 
00497 
00498 /**
00499   \ingroup    CMSIS_core_register
00500   \defgroup   CMSIS_core_bitfield     Core register bit field macros
00501   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
00502   @{
00503  */
00504 
00505 /**
00506   \brief   Mask and shift a bit field value for use in a register bit range.
00507   \param[in] field  Name of the register bit field.
00508   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
00509   \return           Masked and shifted value.
00510 */
00511 #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
00512 
00513 /**
00514   \brief     Mask and shift a register value to extract a bit filed value.
00515   \param[in] field  Name of the register bit field.
00516   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
00517   \return           Masked and shifted bit field value.
00518 */
00519 #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
00520 
00521 /*@} end of group CMSIS_core_bitfield */
00522 
00523 
00524 /**
00525   \ingroup    CMSIS_core_register
00526   \defgroup   CMSIS_core_base     Core Definitions
00527   \brief      Definitions for base addresses, unions, and structures.
00528   @{
00529  */
00530 
00531 /* Memory mapping of Core Hardware */
00532 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
00533 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
00534 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
00535 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
00536 
00537 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
00538 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
00539 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
00540 
00541 
00542 /*@} */
00543 
00544 
00545 
00546 /*******************************************************************************
00547  *                Hardware Abstraction Layer
00548   Core Function Interface contains:
00549   - Core NVIC Functions
00550   - Core SysTick Functions
00551   - Core Register Access Functions
00552  ******************************************************************************/
00553 /**
00554   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
00555 */
00556 
00557 
00558 
00559 /* ##########################   NVIC functions  #################################### */
00560 /**
00561   \ingroup  CMSIS_Core_FunctionInterface
00562   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
00563   \brief    Functions that manage interrupts and exceptions via the NVIC.
00564   @{
00565  */
00566 
00567 #ifdef CMSIS_NVIC_VIRTUAL
00568   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
00569     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
00570   #endif
00571   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
00572 #else
00573 /*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M0 */
00574 /*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M0 */
00575   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
00576   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
00577   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
00578   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
00579   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
00580   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
00581 /*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
00582   #define NVIC_SetPriority            __NVIC_SetPriority
00583   #define NVIC_GetPriority            __NVIC_GetPriority
00584   #define NVIC_SystemReset            __NVIC_SystemReset
00585 #endif /* CMSIS_NVIC_VIRTUAL */
00586 
00587 #ifdef CMSIS_VECTAB_VIRTUAL
00588   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
00589     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
00590   #endif
00591   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
00592 #else
00593   #define NVIC_SetVector              __NVIC_SetVector
00594   #define NVIC_GetVector              __NVIC_GetVector
00595 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
00596 
00597 #define NVIC_USER_IRQ_OFFSET          16
00598 
00599 
00600 /* Interrupt Priorities are WORD accessible only under ARMv6M                   */
00601 /* The following MACROS handle generation of the register offset and byte masks */
00602 #define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
00603 #define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
00604 #define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
00605 
00606 
00607 /**
00608   \brief   Enable Interrupt
00609   \details Enables a device specific interrupt in the NVIC interrupt controller.
00610   \param [in]      IRQn  Device specific interrupt number.
00611   \note    IRQn must not be negative.
00612  */
00613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
00614 {
00615   if ((int32_t)(IRQn) >= 0)
00616   {
00617     NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
00618   }
00619 }
00620 
00621 
00622 /**
00623   \brief   Get Interrupt Enable status
00624   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
00625   \param [in]      IRQn  Device specific interrupt number.
00626   \return             0  Interrupt is not enabled.
00627   \return             1  Interrupt is enabled.
00628   \note    IRQn must not be negative.
00629  */
00630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
00631 {
00632   if ((int32_t)(IRQn) >= 0)
00633   {
00634     return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
00635   }
00636   else
00637   {
00638     return(0U);
00639   }
00640 }
00641 
00642 
00643 /**
00644   \brief   Disable Interrupt
00645   \details Disables a device specific interrupt in the NVIC interrupt controller.
00646   \param [in]      IRQn  Device specific interrupt number.
00647   \note    IRQn must not be negative.
00648  */
00649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
00650 {
00651   if ((int32_t)(IRQn) >= 0)
00652   {
00653     NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
00654     __DSB();
00655     __ISB();
00656   }
00657 }
00658 
00659 
00660 /**
00661   \brief   Get Pending Interrupt
00662   \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
00663   \param [in]      IRQn  Device specific interrupt number.
00664   \return             0  Interrupt status is not pending.
00665   \return             1  Interrupt status is pending.
00666   \note    IRQn must not be negative.
00667  */
00668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
00669 {
00670   if ((int32_t)(IRQn) >= 0)
00671   {
00672     return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
00673   }
00674   else
00675   {
00676     return(0U);
00677   }
00678 }
00679 
00680 
00681 /**
00682   \brief   Set Pending Interrupt
00683   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
00684   \param [in]      IRQn  Device specific interrupt number.
00685   \note    IRQn must not be negative.
00686  */
00687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
00688 {
00689   if ((int32_t)(IRQn) >= 0)
00690   {
00691     NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
00692   }
00693 }
00694 
00695 
00696 /**
00697   \brief   Clear Pending Interrupt
00698   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
00699   \param [in]      IRQn  Device specific interrupt number.
00700   \note    IRQn must not be negative.
00701  */
00702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
00703 {
00704   if ((int32_t)(IRQn) >= 0)
00705   {
00706     NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
00707   }
00708 }
00709 
00710 
00711 /**
00712   \brief   Set Interrupt Priority
00713   \details Sets the priority of a device specific interrupt or a processor exception.
00714            The interrupt number can be positive to specify a device specific interrupt,
00715            or negative to specify a processor exception.
00716   \param [in]      IRQn  Interrupt number.
00717   \param [in]  priority  Priority to set.
00718   \note    The priority cannot be set for every processor exception.
00719  */
00720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
00721 {
00722   if ((int32_t)(IRQn) >= 0)
00723   {
00724     NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
00725        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
00726   }
00727   else
00728   {
00729     SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
00730        (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
00731   }
00732 }
00733 
00734 
00735 /**
00736   \brief   Get Interrupt Priority
00737   \details Reads the priority of a device specific interrupt or a processor exception.
00738            The interrupt number can be positive to specify a device specific interrupt,
00739            or negative to specify a processor exception.
00740   \param [in]   IRQn  Interrupt number.
00741   \return             Interrupt Priority.
00742                       Value is aligned automatically to the implemented priority bits of the microcontroller.
00743  */
00744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
00745 {
00746 
00747   if ((int32_t)(IRQn) >= 0)
00748   {
00749     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
00750   }
00751   else
00752   {
00753     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
00754   }
00755 }
00756 
00757 
00758 /**
00759   \brief   Set Interrupt Vector
00760   \details Sets an interrupt vector in SRAM based interrupt vector table.
00761            The interrupt number can be positive to specify a device specific interrupt,
00762            or negative to specify a processor exception.
00763            Address 0 must be mapped to SRAM.
00764   \param [in]   IRQn      Interrupt number
00765   \param [in]   vector    Address of interrupt handler function
00766  */
00767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
00768 {
00769   uint32_t *vectors = (uint32_t *)0x0U;
00770   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
00771 }
00772 
00773 
00774 /**
00775   \brief   Get Interrupt Vector
00776   \details Reads an interrupt vector from interrupt vector table.
00777            The interrupt number can be positive to specify a device specific interrupt,
00778            or negative to specify a processor exception.
00779   \param [in]   IRQn      Interrupt number.
00780   \return                 Address of interrupt handler function
00781  */
00782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
00783 {
00784   uint32_t *vectors = (uint32_t *)0x0U;
00785   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
00786 }
00787 
00788 
00789 /**
00790   \brief   System Reset
00791   \details Initiates a system reset request to reset the MCU.
00792  */
00793 __STATIC_INLINE void __NVIC_SystemReset(void)
00794 {
00795   __DSB();                                                          /* Ensure all outstanding memory accesses included
00796                                                                        buffered write are completed before reset */
00797   SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
00798                  SCB_AIRCR_SYSRESETREQ_Msk);
00799   __DSB();                                                          /* Ensure completion of memory access */
00800 
00801   for(;;)                                                           /* wait until reset */
00802   {
00803     __NOP();
00804   }
00805 }
00806 
00807 /*@} end of CMSIS_Core_NVICFunctions */
00808 
00809 
00810 /* ##########################  FPU functions  #################################### */
00811 /**
00812   \ingroup  CMSIS_Core_FunctionInterface
00813   \defgroup CMSIS_Core_FpuFunctions FPU Functions
00814   \brief    Function that provides FPU type.
00815   @{
00816  */
00817 
00818 /**
00819   \brief   get FPU type
00820   \details returns the FPU type
00821   \returns
00822    - \b  0: No FPU
00823    - \b  1: Single precision FPU
00824    - \b  2: Double + Single precision FPU
00825  */
00826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
00827 {
00828     return 0U;           /* No FPU */
00829 }
00830 
00831 
00832 /*@} end of CMSIS_Core_FpuFunctions */
00833 
00834 
00835 
00836 /* ##################################    SysTick function  ############################################ */
00837 /**
00838   \ingroup  CMSIS_Core_FunctionInterface
00839   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
00840   \brief    Functions that configure the System.
00841   @{
00842  */
00843 
00844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
00845 
00846 /**
00847   \brief   System Tick Configuration
00848   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
00849            Counter is in free running mode to generate periodic interrupts.
00850   \param [in]  ticks  Number of ticks between two interrupts.
00851   \return          0  Function succeeded.
00852   \return          1  Function failed.
00853   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
00854            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
00855            must contain a vendor-specific implementation of this function.
00856  */
00857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
00858 {
00859   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
00860   {
00861     return (1UL);                                                   /* Reload value impossible */
00862   }
00863 
00864   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
00865   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
00866   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
00867   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
00868                    SysTick_CTRL_TICKINT_Msk   |
00869                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
00870   return (0UL);                                                     /* Function successful */
00871 }
00872 
00873 #endif
00874 
00875 /*@} end of CMSIS_Core_SysTickFunctions */
00876 
00877 
00878 
00879 
00880 #ifdef __cplusplus
00881 }
00882 #endif
00883 
00884 #endif /* __CORE_CM0_H_DEPENDANT */
00885 
00886 #endif /* __CMSIS_GENERIC */