Ben Katz / mbed-dev-f303

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c@181:36facd806e4a, 2018-07-30 (annotated)

Committer:
benkatz
Date:
Mon Jul 30 20:31:44 2018 +0000
Revision:
181:36facd806e4a
Parent:
175:af195413fb11 
going on the robot.  fixed a dumb bug in float_to_uint

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
AnnaBridge 175:af195413fb11 2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 175:af195413fb11 3 * Copyright 2016-2017 NXP
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
AnnaBridge 175:af195413fb11 15 * o Neither the name of the copyright holder nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_sai.h"
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 /*******************************************************************************
<> 154:37f96f9d4de2 34 * Definitations
<> 154:37f96f9d4de2 35 ******************************************************************************/
<> 154:37f96f9d4de2 36 enum _sai_transfer_state
<> 154:37f96f9d4de2 37 {
<> 154:37f96f9d4de2 38 kSAI_Busy = 0x0U, /*!< SAI is busy */
<> 154:37f96f9d4de2 39 kSAI_Idle, /*!< Transfer is done. */
<> 154:37f96f9d4de2 40 kSAI_Error /*!< Transfer error occured. */
<> 154:37f96f9d4de2 41 };
<> 154:37f96f9d4de2 42
<> 154:37f96f9d4de2 43 /*! @brief Typedef for sai tx interrupt handler. */
<> 154:37f96f9d4de2 44 typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
<> 154:37f96f9d4de2 45
<> 154:37f96f9d4de2 46 /*! @brief Typedef for sai rx interrupt handler. */
<> 154:37f96f9d4de2 47 typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle);
<> 154:37f96f9d4de2 48
<> 154:37f96f9d4de2 49 /*******************************************************************************
<> 154:37f96f9d4de2 50 * Prototypes
<> 154:37f96f9d4de2 51 ******************************************************************************/
<> 154:37f96f9d4de2 52 #if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
<> 154:37f96f9d4de2 53
<> 154:37f96f9d4de2 54 /*!
<> 154:37f96f9d4de2 55 * @brief Set the master clock divider.
<> 154:37f96f9d4de2 56 *
<> 154:37f96f9d4de2 57 * This API will compute the master clock divider according to master clock frequency and master
<> 154:37f96f9d4de2 58 * clock source clock source frequency.
<> 154:37f96f9d4de2 59 *
<> 154:37f96f9d4de2 60 * @param base SAI base pointer.
<> 154:37f96f9d4de2 61 * @param mclk_Hz Mater clock frequency in Hz.
<> 154:37f96f9d4de2 62 * @param mclkSrcClock_Hz Master clock source frequency in Hz.
<> 154:37f96f9d4de2 63 */
<> 154:37f96f9d4de2 64 static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz);
<> 154:37f96f9d4de2 65 #endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 /*!
<> 154:37f96f9d4de2 68 * @brief Get the instance number for SAI.
<> 154:37f96f9d4de2 69 *
<> 154:37f96f9d4de2 70 * @param base SAI base pointer.
<> 154:37f96f9d4de2 71 */
<> 154:37f96f9d4de2 72 uint32_t SAI_GetInstance(I2S_Type *base);
<> 154:37f96f9d4de2 73
<> 154:37f96f9d4de2 74 /*!
<> 154:37f96f9d4de2 75 * @brief sends a piece of data in non-blocking way.
<> 154:37f96f9d4de2 76 *
<> 154:37f96f9d4de2 77 * @param base SAI base pointer
<> 154:37f96f9d4de2 78 * @param channel Data channel used.
<> 154:37f96f9d4de2 79 * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
<> 154:37f96f9d4de2 80 * @param buffer Pointer to the data to be written.
<> 154:37f96f9d4de2 81 * @param size Bytes to be written.
<> 154:37f96f9d4de2 82 */
<> 154:37f96f9d4de2 83 static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
<> 154:37f96f9d4de2 84
<> 154:37f96f9d4de2 85 /*!
<> 154:37f96f9d4de2 86 * @brief Receive a piece of data in non-blocking way.
<> 154:37f96f9d4de2 87 *
<> 154:37f96f9d4de2 88 * @param base SAI base pointer
<> 154:37f96f9d4de2 89 * @param channel Data channel used.
<> 154:37f96f9d4de2 90 * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
<> 154:37f96f9d4de2 91 * @param buffer Pointer to the data to be read.
<> 154:37f96f9d4de2 92 * @param size Bytes to be read.
<> 154:37f96f9d4de2 93 */
<> 154:37f96f9d4de2 94 static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
<> 154:37f96f9d4de2 95 /*******************************************************************************
<> 154:37f96f9d4de2 96 * Variables
<> 154:37f96f9d4de2 97 ******************************************************************************/
<> 154:37f96f9d4de2 98 /* Base pointer array */
<> 154:37f96f9d4de2 99 static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS;
AnnaBridge 175:af195413fb11 100 /*!@brief SAI handle pointer */
AnnaBridge 175:af195413fb11 101 sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2];
<> 154:37f96f9d4de2 102 /* IRQ number array */
<> 154:37f96f9d4de2 103 static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS;
<> 154:37f96f9d4de2 104 static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
AnnaBridge 175:af195413fb11 105 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 106 /* Clock name array */
<> 154:37f96f9d4de2 107 static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS;
AnnaBridge 175:af195413fb11 108 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 109 /*! @brief Pointer to tx IRQ handler for each instance. */
<> 154:37f96f9d4de2 110 static sai_tx_isr_t s_saiTxIsr;
<> 154:37f96f9d4de2 111 /*! @brief Pointer to tx IRQ handler for each instance. */
<> 154:37f96f9d4de2 112 static sai_rx_isr_t s_saiRxIsr;
<> 154:37f96f9d4de2 113
<> 154:37f96f9d4de2 114 /*******************************************************************************
<> 154:37f96f9d4de2 115 * Code
<> 154:37f96f9d4de2 116 ******************************************************************************/
<> 154:37f96f9d4de2 117 #if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
<> 154:37f96f9d4de2 118 static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz)
<> 154:37f96f9d4de2 119 {
<> 154:37f96f9d4de2 120 uint32_t freq = mclkSrcClock_Hz;
<> 154:37f96f9d4de2 121 uint16_t fract, divide;
<> 154:37f96f9d4de2 122 uint32_t remaind = 0;
<> 154:37f96f9d4de2 123 uint32_t current_remainder = 0xFFFFFFFFU;
<> 154:37f96f9d4de2 124 uint16_t current_fract = 0;
<> 154:37f96f9d4de2 125 uint16_t current_divide = 0;
<> 154:37f96f9d4de2 126 uint32_t mul_freq = 0;
<> 154:37f96f9d4de2 127 uint32_t max_fract = 256;
<> 154:37f96f9d4de2 128
<> 154:37f96f9d4de2 129 /*In order to prevent overflow */
<> 154:37f96f9d4de2 130 freq /= 100;
<> 154:37f96f9d4de2 131 mclk_Hz /= 100;
<> 154:37f96f9d4de2 132
<> 154:37f96f9d4de2 133 /* Compute the max fract number */
<> 154:37f96f9d4de2 134 max_fract = mclk_Hz * 4096 / freq + 1;
<> 154:37f96f9d4de2 135 if (max_fract > 256)
<> 154:37f96f9d4de2 136 {
<> 154:37f96f9d4de2 137 max_fract = 256;
<> 154:37f96f9d4de2 138 }
<> 154:37f96f9d4de2 139
<> 154:37f96f9d4de2 140 /* Looking for the closet frequency */
<> 154:37f96f9d4de2 141 for (fract = 1; fract < max_fract; fract++)
<> 154:37f96f9d4de2 142 {
<> 154:37f96f9d4de2 143 mul_freq = freq * fract;
<> 154:37f96f9d4de2 144 remaind = mul_freq % mclk_Hz;
<> 154:37f96f9d4de2 145 divide = mul_freq / mclk_Hz;
<> 154:37f96f9d4de2 146
<> 154:37f96f9d4de2 147 /* Find the exactly frequency */
<> 154:37f96f9d4de2 148 if (remaind == 0)
<> 154:37f96f9d4de2 149 {
<> 154:37f96f9d4de2 150 current_fract = fract;
<> 154:37f96f9d4de2 151 current_divide = mul_freq / mclk_Hz;
<> 154:37f96f9d4de2 152 break;
<> 154:37f96f9d4de2 153 }
<> 154:37f96f9d4de2 154
<> 154:37f96f9d4de2 155 /* Closer to next one, set the closest to next data */
<> 154:37f96f9d4de2 156 if (remaind > mclk_Hz / 2)
<> 154:37f96f9d4de2 157 {
<> 154:37f96f9d4de2 158 remaind = mclk_Hz - remaind;
<> 154:37f96f9d4de2 159 divide += 1;
<> 154:37f96f9d4de2 160 }
<> 154:37f96f9d4de2 161
<> 154:37f96f9d4de2 162 /* Update the closest div and fract */
<> 154:37f96f9d4de2 163 if (remaind < current_remainder)
<> 154:37f96f9d4de2 164 {
<> 154:37f96f9d4de2 165 current_fract = fract;
<> 154:37f96f9d4de2 166 current_divide = divide;
<> 154:37f96f9d4de2 167 current_remainder = remaind;
<> 154:37f96f9d4de2 168 }
<> 154:37f96f9d4de2 169 }
<> 154:37f96f9d4de2 170
<> 154:37f96f9d4de2 171 /* Fill the computed fract and divider to registers */
<> 154:37f96f9d4de2 172 base->MDR = I2S_MDR_DIVIDE(current_divide - 1) | I2S_MDR_FRACT(current_fract - 1);
<> 154:37f96f9d4de2 173
<> 154:37f96f9d4de2 174 /* Waiting for the divider updated */
<> 154:37f96f9d4de2 175 while (base->MCR & I2S_MCR_DUF_MASK)
<> 154:37f96f9d4de2 176 {
<> 154:37f96f9d4de2 177 }
<> 154:37f96f9d4de2 178 }
<> 154:37f96f9d4de2 179 #endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
<> 154:37f96f9d4de2 180
<> 154:37f96f9d4de2 181 uint32_t SAI_GetInstance(I2S_Type *base)
<> 154:37f96f9d4de2 182 {
<> 154:37f96f9d4de2 183 uint32_t instance;
<> 154:37f96f9d4de2 184
<> 154:37f96f9d4de2 185 /* Find the instance index from base address mappings. */
AnnaBridge 175:af195413fb11 186 for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++)
<> 154:37f96f9d4de2 187 {
<> 154:37f96f9d4de2 188 if (s_saiBases[instance] == base)
<> 154:37f96f9d4de2 189 {
<> 154:37f96f9d4de2 190 break;
<> 154:37f96f9d4de2 191 }
<> 154:37f96f9d4de2 192 }
<> 154:37f96f9d4de2 193
AnnaBridge 175:af195413fb11 194 assert(instance < ARRAY_SIZE(s_saiBases));
<> 154:37f96f9d4de2 195
<> 154:37f96f9d4de2 196 return instance;
<> 154:37f96f9d4de2 197 }
<> 154:37f96f9d4de2 198
<> 154:37f96f9d4de2 199 static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
<> 154:37f96f9d4de2 200 {
<> 154:37f96f9d4de2 201 uint32_t i = 0;
<> 154:37f96f9d4de2 202 uint8_t j = 0;
<> 154:37f96f9d4de2 203 uint8_t bytesPerWord = bitWidth / 8U;
<> 154:37f96f9d4de2 204 uint32_t data = 0;
<> 154:37f96f9d4de2 205 uint32_t temp = 0;
<> 154:37f96f9d4de2 206
<> 154:37f96f9d4de2 207 for (i = 0; i < size / bytesPerWord; i++)
<> 154:37f96f9d4de2 208 {
<> 154:37f96f9d4de2 209 for (j = 0; j < bytesPerWord; j++)
<> 154:37f96f9d4de2 210 {
<> 154:37f96f9d4de2 211 temp = (uint32_t)(*buffer);
<> 154:37f96f9d4de2 212 data |= (temp << (8U * j));
<> 154:37f96f9d4de2 213 buffer++;
<> 154:37f96f9d4de2 214 }
<> 154:37f96f9d4de2 215 base->TDR[channel] = data;
<> 154:37f96f9d4de2 216 data = 0;
<> 154:37f96f9d4de2 217 }
<> 154:37f96f9d4de2 218 }
<> 154:37f96f9d4de2 219
<> 154:37f96f9d4de2 220 static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
<> 154:37f96f9d4de2 221 {
<> 154:37f96f9d4de2 222 uint32_t i = 0;
<> 154:37f96f9d4de2 223 uint8_t j = 0;
<> 154:37f96f9d4de2 224 uint8_t bytesPerWord = bitWidth / 8U;
<> 154:37f96f9d4de2 225 uint32_t data = 0;
<> 154:37f96f9d4de2 226
<> 154:37f96f9d4de2 227 for (i = 0; i < size / bytesPerWord; i++)
<> 154:37f96f9d4de2 228 {
<> 154:37f96f9d4de2 229 data = base->RDR[channel];
<> 154:37f96f9d4de2 230 for (j = 0; j < bytesPerWord; j++)
<> 154:37f96f9d4de2 231 {
<> 154:37f96f9d4de2 232 *buffer = (data >> (8U * j)) & 0xFF;
<> 154:37f96f9d4de2 233 buffer++;
<> 154:37f96f9d4de2 234 }
<> 154:37f96f9d4de2 235 }
<> 154:37f96f9d4de2 236 }
<> 154:37f96f9d4de2 237
<> 154:37f96f9d4de2 238 void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
<> 154:37f96f9d4de2 239 {
<> 154:37f96f9d4de2 240 uint32_t val = 0;
<> 154:37f96f9d4de2 241
AnnaBridge 175:af195413fb11 242 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 243 /* Enable the SAI clock */
<> 154:37f96f9d4de2 244 CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
AnnaBridge 175:af195413fb11 245 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 246
<> 154:37f96f9d4de2 247 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
<> 154:37f96f9d4de2 248 /* Master clock source setting */
<> 154:37f96f9d4de2 249 val = (base->MCR & ~I2S_MCR_MICS_MASK);
<> 154:37f96f9d4de2 250 base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
<> 154:37f96f9d4de2 251
<> 154:37f96f9d4de2 252 /* Configure Master clock output enable */
<> 154:37f96f9d4de2 253 val = (base->MCR & ~I2S_MCR_MOE_MASK);
<> 154:37f96f9d4de2 254 base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
<> 154:37f96f9d4de2 255 #endif /* FSL_FEATURE_SAI_HAS_MCR */
<> 154:37f96f9d4de2 256
<> 154:37f96f9d4de2 257 /* Configure audio protocol */
<> 154:37f96f9d4de2 258 switch (config->protocol)
<> 154:37f96f9d4de2 259 {
<> 154:37f96f9d4de2 260 case kSAI_BusLeftJustified:
<> 154:37f96f9d4de2 261 base->TCR2 |= I2S_TCR2_BCP_MASK;
<> 154:37f96f9d4de2 262 base->TCR3 &= ~I2S_TCR3_WDFL_MASK;
<> 154:37f96f9d4de2 263 base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U);
<> 154:37f96f9d4de2 264 break;
<> 154:37f96f9d4de2 265
<> 154:37f96f9d4de2 266 case kSAI_BusRightJustified:
<> 154:37f96f9d4de2 267 base->TCR2 |= I2S_TCR2_BCP_MASK;
<> 154:37f96f9d4de2 268 base->TCR3 &= ~I2S_TCR3_WDFL_MASK;
<> 154:37f96f9d4de2 269 base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U);
<> 154:37f96f9d4de2 270 break;
<> 154:37f96f9d4de2 271
<> 154:37f96f9d4de2 272 case kSAI_BusI2S:
<> 154:37f96f9d4de2 273 base->TCR2 |= I2S_TCR2_BCP_MASK;
<> 154:37f96f9d4de2 274 base->TCR3 &= ~I2S_TCR3_WDFL_MASK;
<> 154:37f96f9d4de2 275 base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U);
<> 154:37f96f9d4de2 276 break;
<> 154:37f96f9d4de2 277
<> 154:37f96f9d4de2 278 case kSAI_BusPCMA:
<> 154:37f96f9d4de2 279 base->TCR2 &= ~I2S_TCR2_BCP_MASK;
<> 154:37f96f9d4de2 280 base->TCR3 &= ~I2S_TCR3_WDFL_MASK;
<> 154:37f96f9d4de2 281 base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U);
<> 154:37f96f9d4de2 282 break;
<> 154:37f96f9d4de2 283
<> 154:37f96f9d4de2 284 case kSAI_BusPCMB:
<> 154:37f96f9d4de2 285 base->TCR2 &= ~I2S_TCR2_BCP_MASK;
<> 154:37f96f9d4de2 286 base->TCR3 &= ~I2S_TCR3_WDFL_MASK;
<> 154:37f96f9d4de2 287 base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U);
<> 154:37f96f9d4de2 288 break;
<> 154:37f96f9d4de2 289
<> 154:37f96f9d4de2 290 default:
<> 154:37f96f9d4de2 291 break;
<> 154:37f96f9d4de2 292 }
<> 154:37f96f9d4de2 293
<> 154:37f96f9d4de2 294 /* Set master or slave */
<> 154:37f96f9d4de2 295 if (config->masterSlave == kSAI_Master)
<> 154:37f96f9d4de2 296 {
<> 154:37f96f9d4de2 297 base->TCR2 |= I2S_TCR2_BCD_MASK;
<> 154:37f96f9d4de2 298 base->TCR4 |= I2S_TCR4_FSD_MASK;
<> 154:37f96f9d4de2 299
<> 154:37f96f9d4de2 300 /* Bit clock source setting */
<> 154:37f96f9d4de2 301 val = base->TCR2 & (~I2S_TCR2_MSEL_MASK);
<> 154:37f96f9d4de2 302 base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource));
<> 154:37f96f9d4de2 303 }
<> 154:37f96f9d4de2 304 else
<> 154:37f96f9d4de2 305 {
<> 154:37f96f9d4de2 306 base->TCR2 &= ~I2S_TCR2_BCD_MASK;
<> 154:37f96f9d4de2 307 base->TCR4 &= ~I2S_TCR4_FSD_MASK;
<> 154:37f96f9d4de2 308 }
<> 154:37f96f9d4de2 309
<> 154:37f96f9d4de2 310 /* Set Sync mode */
<> 154:37f96f9d4de2 311 switch (config->syncMode)
<> 154:37f96f9d4de2 312 {
<> 154:37f96f9d4de2 313 case kSAI_ModeAsync:
<> 154:37f96f9d4de2 314 val = base->TCR2;
<> 154:37f96f9d4de2 315 val &= ~I2S_TCR2_SYNC_MASK;
<> 154:37f96f9d4de2 316 base->TCR2 = (val | I2S_TCR2_SYNC(0U));
<> 154:37f96f9d4de2 317 break;
<> 154:37f96f9d4de2 318 case kSAI_ModeSync:
<> 154:37f96f9d4de2 319 val = base->TCR2;
<> 154:37f96f9d4de2 320 val &= ~I2S_TCR2_SYNC_MASK;
<> 154:37f96f9d4de2 321 base->TCR2 = (val | I2S_TCR2_SYNC(1U));
<> 154:37f96f9d4de2 322 /* If sync with Rx, should set Rx to async mode */
<> 154:37f96f9d4de2 323 val = base->RCR2;
<> 154:37f96f9d4de2 324 val &= ~I2S_RCR2_SYNC_MASK;
<> 154:37f96f9d4de2 325 base->RCR2 = (val | I2S_RCR2_SYNC(0U));
<> 154:37f96f9d4de2 326 break;
<> 154:37f96f9d4de2 327 case kSAI_ModeSyncWithOtherTx:
<> 154:37f96f9d4de2 328 val = base->TCR2;
<> 154:37f96f9d4de2 329 val &= ~I2S_TCR2_SYNC_MASK;
<> 154:37f96f9d4de2 330 base->TCR2 = (val | I2S_TCR2_SYNC(2U));
<> 154:37f96f9d4de2 331 break;
<> 154:37f96f9d4de2 332 case kSAI_ModeSyncWithOtherRx:
<> 154:37f96f9d4de2 333 val = base->TCR2;
<> 154:37f96f9d4de2 334 val &= ~I2S_TCR2_SYNC_MASK;
<> 154:37f96f9d4de2 335 base->TCR2 = (val | I2S_TCR2_SYNC(3U));
<> 154:37f96f9d4de2 336 break;
<> 154:37f96f9d4de2 337 default:
<> 154:37f96f9d4de2 338 break;
<> 154:37f96f9d4de2 339 }
<> 154:37f96f9d4de2 340 }
<> 154:37f96f9d4de2 341
<> 154:37f96f9d4de2 342 void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
<> 154:37f96f9d4de2 343 {
<> 154:37f96f9d4de2 344 uint32_t val = 0;
<> 154:37f96f9d4de2 345
AnnaBridge 175:af195413fb11 346 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 347 /* Enable SAI clock first. */
<> 154:37f96f9d4de2 348 CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]);
AnnaBridge 175:af195413fb11 349 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 350
<> 154:37f96f9d4de2 351 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
<> 154:37f96f9d4de2 352 /* Master clock source setting */
<> 154:37f96f9d4de2 353 val = (base->MCR & ~I2S_MCR_MICS_MASK);
<> 154:37f96f9d4de2 354 base->MCR = (val | I2S_MCR_MICS(config->mclkSource));
<> 154:37f96f9d4de2 355
<> 154:37f96f9d4de2 356 /* Configure Master clock output enable */
<> 154:37f96f9d4de2 357 val = (base->MCR & ~I2S_MCR_MOE_MASK);
<> 154:37f96f9d4de2 358 base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
<> 154:37f96f9d4de2 359 #endif /* FSL_FEATURE_SAI_HAS_MCR */
<> 154:37f96f9d4de2 360
<> 154:37f96f9d4de2 361 /* Configure audio protocol */
<> 154:37f96f9d4de2 362 switch (config->protocol)
<> 154:37f96f9d4de2 363 {
<> 154:37f96f9d4de2 364 case kSAI_BusLeftJustified:
<> 154:37f96f9d4de2 365 base->RCR2 |= I2S_RCR2_BCP_MASK;
<> 154:37f96f9d4de2 366 base->RCR3 &= ~I2S_RCR3_WDFL_MASK;
<> 154:37f96f9d4de2 367 base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U);
<> 154:37f96f9d4de2 368 break;
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 case kSAI_BusRightJustified:
<> 154:37f96f9d4de2 371 base->RCR2 |= I2S_RCR2_BCP_MASK;
<> 154:37f96f9d4de2 372 base->RCR3 &= ~I2S_RCR3_WDFL_MASK;
<> 154:37f96f9d4de2 373 base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U);
<> 154:37f96f9d4de2 374 break;
<> 154:37f96f9d4de2 375
<> 154:37f96f9d4de2 376 case kSAI_BusI2S:
<> 154:37f96f9d4de2 377 base->RCR2 |= I2S_RCR2_BCP_MASK;
<> 154:37f96f9d4de2 378 base->RCR3 &= ~I2S_RCR3_WDFL_MASK;
<> 154:37f96f9d4de2 379 base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U);
<> 154:37f96f9d4de2 380 break;
<> 154:37f96f9d4de2 381
<> 154:37f96f9d4de2 382 case kSAI_BusPCMA:
<> 154:37f96f9d4de2 383 base->RCR2 &= ~I2S_RCR2_BCP_MASK;
<> 154:37f96f9d4de2 384 base->RCR3 &= ~I2S_RCR3_WDFL_MASK;
<> 154:37f96f9d4de2 385 base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U);
<> 154:37f96f9d4de2 386 break;
<> 154:37f96f9d4de2 387
<> 154:37f96f9d4de2 388 case kSAI_BusPCMB:
<> 154:37f96f9d4de2 389 base->RCR2 &= ~I2S_RCR2_BCP_MASK;
<> 154:37f96f9d4de2 390 base->RCR3 &= ~I2S_RCR3_WDFL_MASK;
<> 154:37f96f9d4de2 391 base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U);
<> 154:37f96f9d4de2 392 break;
<> 154:37f96f9d4de2 393
<> 154:37f96f9d4de2 394 default:
<> 154:37f96f9d4de2 395 break;
<> 154:37f96f9d4de2 396 }
<> 154:37f96f9d4de2 397
<> 154:37f96f9d4de2 398 /* Set master or slave */
<> 154:37f96f9d4de2 399 if (config->masterSlave == kSAI_Master)
<> 154:37f96f9d4de2 400 {
<> 154:37f96f9d4de2 401 base->RCR2 |= I2S_RCR2_BCD_MASK;
<> 154:37f96f9d4de2 402 base->RCR4 |= I2S_RCR4_FSD_MASK;
<> 154:37f96f9d4de2 403
<> 154:37f96f9d4de2 404 /* Bit clock source setting */
<> 154:37f96f9d4de2 405 val = base->RCR2 & (~I2S_RCR2_MSEL_MASK);
<> 154:37f96f9d4de2 406 base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource));
<> 154:37f96f9d4de2 407 }
<> 154:37f96f9d4de2 408 else
<> 154:37f96f9d4de2 409 {
<> 154:37f96f9d4de2 410 base->RCR2 &= ~I2S_RCR2_BCD_MASK;
<> 154:37f96f9d4de2 411 base->RCR4 &= ~I2S_RCR4_FSD_MASK;
<> 154:37f96f9d4de2 412 }
<> 154:37f96f9d4de2 413
<> 154:37f96f9d4de2 414 /* Set Sync mode */
<> 154:37f96f9d4de2 415 switch (config->syncMode)
<> 154:37f96f9d4de2 416 {
<> 154:37f96f9d4de2 417 case kSAI_ModeAsync:
<> 154:37f96f9d4de2 418 val = base->RCR2;
<> 154:37f96f9d4de2 419 val &= ~I2S_RCR2_SYNC_MASK;
<> 154:37f96f9d4de2 420 base->RCR2 = (val | I2S_RCR2_SYNC(0U));
<> 154:37f96f9d4de2 421 break;
<> 154:37f96f9d4de2 422 case kSAI_ModeSync:
<> 154:37f96f9d4de2 423 val = base->RCR2;
<> 154:37f96f9d4de2 424 val &= ~I2S_RCR2_SYNC_MASK;
<> 154:37f96f9d4de2 425 base->RCR2 = (val | I2S_RCR2_SYNC(1U));
<> 154:37f96f9d4de2 426 /* If sync with Tx, should set Tx to async mode */
<> 154:37f96f9d4de2 427 val = base->TCR2;
<> 154:37f96f9d4de2 428 val &= ~I2S_TCR2_SYNC_MASK;
<> 154:37f96f9d4de2 429 base->TCR2 = (val | I2S_TCR2_SYNC(0U));
<> 154:37f96f9d4de2 430 break;
<> 154:37f96f9d4de2 431 case kSAI_ModeSyncWithOtherTx:
<> 154:37f96f9d4de2 432 val = base->RCR2;
<> 154:37f96f9d4de2 433 val &= ~I2S_RCR2_SYNC_MASK;
<> 154:37f96f9d4de2 434 base->RCR2 = (val | I2S_RCR2_SYNC(2U));
<> 154:37f96f9d4de2 435 break;
<> 154:37f96f9d4de2 436 case kSAI_ModeSyncWithOtherRx:
<> 154:37f96f9d4de2 437 val = base->RCR2;
<> 154:37f96f9d4de2 438 val &= ~I2S_RCR2_SYNC_MASK;
<> 154:37f96f9d4de2 439 base->RCR2 = (val | I2S_RCR2_SYNC(3U));
<> 154:37f96f9d4de2 440 break;
<> 154:37f96f9d4de2 441 default:
<> 154:37f96f9d4de2 442 break;
<> 154:37f96f9d4de2 443 }
<> 154:37f96f9d4de2 444 }
<> 154:37f96f9d4de2 445
<> 154:37f96f9d4de2 446 void SAI_Deinit(I2S_Type *base)
<> 154:37f96f9d4de2 447 {
<> 154:37f96f9d4de2 448 SAI_TxEnable(base, false);
<> 154:37f96f9d4de2 449 SAI_RxEnable(base, false);
AnnaBridge 175:af195413fb11 450 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
<> 154:37f96f9d4de2 451 CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]);
AnnaBridge 175:af195413fb11 452 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
<> 154:37f96f9d4de2 453 }
<> 154:37f96f9d4de2 454
<> 154:37f96f9d4de2 455 void SAI_TxGetDefaultConfig(sai_config_t *config)
<> 154:37f96f9d4de2 456 {
<> 154:37f96f9d4de2 457 config->bclkSource = kSAI_BclkSourceMclkDiv;
<> 154:37f96f9d4de2 458 config->masterSlave = kSAI_Master;
<> 154:37f96f9d4de2 459 config->mclkSource = kSAI_MclkSourceSysclk;
<> 154:37f96f9d4de2 460 config->protocol = kSAI_BusLeftJustified;
<> 154:37f96f9d4de2 461 config->syncMode = kSAI_ModeAsync;
<> 154:37f96f9d4de2 462 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
<> 154:37f96f9d4de2 463 config->mclkOutputEnable = true;
<> 154:37f96f9d4de2 464 #endif /* FSL_FEATURE_SAI_HAS_MCR */
<> 154:37f96f9d4de2 465 }
<> 154:37f96f9d4de2 466
<> 154:37f96f9d4de2 467 void SAI_RxGetDefaultConfig(sai_config_t *config)
<> 154:37f96f9d4de2 468 {
<> 154:37f96f9d4de2 469 config->bclkSource = kSAI_BclkSourceMclkDiv;
<> 154:37f96f9d4de2 470 config->masterSlave = kSAI_Master;
<> 154:37f96f9d4de2 471 config->mclkSource = kSAI_MclkSourceSysclk;
<> 154:37f96f9d4de2 472 config->protocol = kSAI_BusLeftJustified;
<> 154:37f96f9d4de2 473 config->syncMode = kSAI_ModeSync;
<> 154:37f96f9d4de2 474 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
<> 154:37f96f9d4de2 475 config->mclkOutputEnable = true;
<> 154:37f96f9d4de2 476 #endif /* FSL_FEATURE_SAI_HAS_MCR */
<> 154:37f96f9d4de2 477 }
<> 154:37f96f9d4de2 478
<> 154:37f96f9d4de2 479 void SAI_TxReset(I2S_Type *base)
<> 154:37f96f9d4de2 480 {
<> 154:37f96f9d4de2 481 /* Set the software reset and FIFO reset to clear internal state */
<> 154:37f96f9d4de2 482 base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK;
<> 154:37f96f9d4de2 483
<> 154:37f96f9d4de2 484 /* Clear software reset bit, this should be done by software */
<> 154:37f96f9d4de2 485 base->TCSR &= ~I2S_TCSR_SR_MASK;
<> 154:37f96f9d4de2 486
<> 154:37f96f9d4de2 487 /* Reset all Tx register values */
<> 154:37f96f9d4de2 488 base->TCR2 = 0;
<> 154:37f96f9d4de2 489 base->TCR3 = 0;
<> 154:37f96f9d4de2 490 base->TCR4 = 0;
<> 154:37f96f9d4de2 491 base->TCR5 = 0;
<> 154:37f96f9d4de2 492 base->TMR = 0;
<> 154:37f96f9d4de2 493 }
<> 154:37f96f9d4de2 494
<> 154:37f96f9d4de2 495 void SAI_RxReset(I2S_Type *base)
<> 154:37f96f9d4de2 496 {
<> 154:37f96f9d4de2 497 /* Set the software reset and FIFO reset to clear internal state */
<> 154:37f96f9d4de2 498 base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK;
<> 154:37f96f9d4de2 499
<> 154:37f96f9d4de2 500 /* Clear software reset bit, this should be done by software */
<> 154:37f96f9d4de2 501 base->RCSR &= ~I2S_RCSR_SR_MASK;
<> 154:37f96f9d4de2 502
<> 154:37f96f9d4de2 503 /* Reset all Rx register values */
<> 154:37f96f9d4de2 504 base->RCR2 = 0;
<> 154:37f96f9d4de2 505 base->RCR3 = 0;
<> 154:37f96f9d4de2 506 base->RCR4 = 0;
<> 154:37f96f9d4de2 507 base->RCR5 = 0;
<> 154:37f96f9d4de2 508 base->RMR = 0;
<> 154:37f96f9d4de2 509 }
<> 154:37f96f9d4de2 510
<> 154:37f96f9d4de2 511 void SAI_TxEnable(I2S_Type *base, bool enable)
<> 154:37f96f9d4de2 512 {
<> 154:37f96f9d4de2 513 if (enable)
<> 154:37f96f9d4de2 514 {
<> 154:37f96f9d4de2 515 /* If clock is sync with Rx, should enable RE bit. */
<> 154:37f96f9d4de2 516 if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U)
<> 154:37f96f9d4de2 517 {
<> 154:37f96f9d4de2 518 base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK);
<> 154:37f96f9d4de2 519 }
<> 154:37f96f9d4de2 520 base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK);
<> 154:37f96f9d4de2 521 }
<> 154:37f96f9d4de2 522 else
<> 154:37f96f9d4de2 523 {
<> 154:37f96f9d4de2 524 /* Should not close RE even sync with Rx */
<> 154:37f96f9d4de2 525 base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK));
<> 154:37f96f9d4de2 526 }
<> 154:37f96f9d4de2 527 }
<> 154:37f96f9d4de2 528
<> 154:37f96f9d4de2 529 void SAI_RxEnable(I2S_Type *base, bool enable)
<> 154:37f96f9d4de2 530 {
<> 154:37f96f9d4de2 531 if (enable)
<> 154:37f96f9d4de2 532 {
<> 154:37f96f9d4de2 533 /* If clock is sync with Tx, should enable TE bit. */
<> 154:37f96f9d4de2 534 if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U)
<> 154:37f96f9d4de2 535 {
<> 154:37f96f9d4de2 536 base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK);
<> 154:37f96f9d4de2 537 }
<> 154:37f96f9d4de2 538 base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK);
<> 154:37f96f9d4de2 539 }
<> 154:37f96f9d4de2 540 else
<> 154:37f96f9d4de2 541 {
<> 154:37f96f9d4de2 542 base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK));
<> 154:37f96f9d4de2 543 }
<> 154:37f96f9d4de2 544 }
<> 154:37f96f9d4de2 545
<> 154:37f96f9d4de2 546 void SAI_TxSetFormat(I2S_Type *base,
<> 154:37f96f9d4de2 547 sai_transfer_format_t *format,
<> 154:37f96f9d4de2 548 uint32_t mclkSourceClockHz,
<> 154:37f96f9d4de2 549 uint32_t bclkSourceClockHz)
<> 154:37f96f9d4de2 550 {
<> 154:37f96f9d4de2 551 uint32_t bclk = format->sampleRate_Hz * 32U * 2U;
<> 154:37f96f9d4de2 552
<> 154:37f96f9d4de2 553 /* Compute the mclk */
<> 154:37f96f9d4de2 554 #if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
<> 154:37f96f9d4de2 555 /* Check if master clock divider enabled, then set master clock divider */
<> 154:37f96f9d4de2 556 if (base->MCR & I2S_MCR_MOE_MASK)
<> 154:37f96f9d4de2 557 {
<> 154:37f96f9d4de2 558 SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz);
<> 154:37f96f9d4de2 559 }
<> 154:37f96f9d4de2 560 #endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
<> 154:37f96f9d4de2 561
<> 154:37f96f9d4de2 562 /* Set bclk if needed */
<> 154:37f96f9d4de2 563 if (base->TCR2 & I2S_TCR2_BCD_MASK)
<> 154:37f96f9d4de2 564 {
<> 154:37f96f9d4de2 565 base->TCR2 &= ~I2S_TCR2_DIV_MASK;
<> 154:37f96f9d4de2 566 base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U);
<> 154:37f96f9d4de2 567 }
<> 154:37f96f9d4de2 568
<> 154:37f96f9d4de2 569 /* Set bitWidth */
<> 154:37f96f9d4de2 570 if (format->protocol == kSAI_BusRightJustified)
<> 154:37f96f9d4de2 571 {
<> 154:37f96f9d4de2 572 base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(31U);
<> 154:37f96f9d4de2 573 }
<> 154:37f96f9d4de2 574 else
<> 154:37f96f9d4de2 575 {
<> 154:37f96f9d4de2 576 base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(format->bitWidth - 1);
<> 154:37f96f9d4de2 577 }
<> 154:37f96f9d4de2 578
<> 154:37f96f9d4de2 579 /* Set mono or stereo */
<> 154:37f96f9d4de2 580 base->TMR = (uint32_t)format->stereo;
<> 154:37f96f9d4de2 581
<> 154:37f96f9d4de2 582 /* Set data channel */
<> 154:37f96f9d4de2 583 base->TCR3 &= ~I2S_TCR3_TCE_MASK;
<> 154:37f96f9d4de2 584 base->TCR3 |= I2S_TCR3_TCE(1U << format->channel);
<> 154:37f96f9d4de2 585
<> 154:37f96f9d4de2 586 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 587 /* Set watermark */
<> 154:37f96f9d4de2 588 base->TCR1 = format->watermark;
<> 154:37f96f9d4de2 589 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
<> 154:37f96f9d4de2 590 }
<> 154:37f96f9d4de2 591
<> 154:37f96f9d4de2 592 void SAI_RxSetFormat(I2S_Type *base,
<> 154:37f96f9d4de2 593 sai_transfer_format_t *format,
<> 154:37f96f9d4de2 594 uint32_t mclkSourceClockHz,
<> 154:37f96f9d4de2 595 uint32_t bclkSourceClockHz)
<> 154:37f96f9d4de2 596 {
<> 154:37f96f9d4de2 597 uint32_t bclk = format->sampleRate_Hz * 32U * 2U;
<> 154:37f96f9d4de2 598
<> 154:37f96f9d4de2 599 /* Compute the mclk */
<> 154:37f96f9d4de2 600 #if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
<> 154:37f96f9d4de2 601 /* Check if master clock divider enabled */
<> 154:37f96f9d4de2 602 if (base->MCR & I2S_MCR_MOE_MASK)
<> 154:37f96f9d4de2 603 {
<> 154:37f96f9d4de2 604 SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz);
<> 154:37f96f9d4de2 605 }
<> 154:37f96f9d4de2 606 #endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
<> 154:37f96f9d4de2 607
<> 154:37f96f9d4de2 608 /* Set bclk if needed */
<> 154:37f96f9d4de2 609 if (base->RCR2 & I2S_RCR2_BCD_MASK)
<> 154:37f96f9d4de2 610 {
<> 154:37f96f9d4de2 611 base->RCR2 &= ~I2S_RCR2_DIV_MASK;
<> 154:37f96f9d4de2 612 base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U);
<> 154:37f96f9d4de2 613 }
<> 154:37f96f9d4de2 614
<> 154:37f96f9d4de2 615 /* Set bitWidth */
<> 154:37f96f9d4de2 616 if (format->protocol == kSAI_BusRightJustified)
<> 154:37f96f9d4de2 617 {
<> 154:37f96f9d4de2 618 base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(31U);
<> 154:37f96f9d4de2 619 }
<> 154:37f96f9d4de2 620 else
<> 154:37f96f9d4de2 621 {
<> 154:37f96f9d4de2 622 base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(format->bitWidth - 1);
<> 154:37f96f9d4de2 623 }
<> 154:37f96f9d4de2 624
<> 154:37f96f9d4de2 625 /* Set mono or stereo */
<> 154:37f96f9d4de2 626 base->RMR = (uint32_t)format->stereo;
<> 154:37f96f9d4de2 627
<> 154:37f96f9d4de2 628 /* Set data channel */
<> 154:37f96f9d4de2 629 base->RCR3 &= ~I2S_RCR3_RCE_MASK;
<> 154:37f96f9d4de2 630 base->RCR3 |= I2S_RCR3_RCE(1U << format->channel);
<> 154:37f96f9d4de2 631
<> 154:37f96f9d4de2 632 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 633 /* Set watermark */
<> 154:37f96f9d4de2 634 base->RCR1 = format->watermark;
<> 154:37f96f9d4de2 635 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
<> 154:37f96f9d4de2 636 }
<> 154:37f96f9d4de2 637
<> 154:37f96f9d4de2 638 void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
<> 154:37f96f9d4de2 639 {
<> 154:37f96f9d4de2 640 uint32_t i = 0;
<> 154:37f96f9d4de2 641 uint8_t bytesPerWord = bitWidth / 8U;
<> 154:37f96f9d4de2 642
AnnaBridge 175:af195413fb11 643 while (i < size)
<> 154:37f96f9d4de2 644 {
<> 154:37f96f9d4de2 645 /* Wait until it can write data */
<> 154:37f96f9d4de2 646 while (!(base->TCSR & I2S_TCSR_FWF_MASK))
<> 154:37f96f9d4de2 647 {
<> 154:37f96f9d4de2 648 }
<> 154:37f96f9d4de2 649
<> 154:37f96f9d4de2 650 SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord);
<> 154:37f96f9d4de2 651 buffer += bytesPerWord;
AnnaBridge 175:af195413fb11 652 i += bytesPerWord;
<> 154:37f96f9d4de2 653 }
<> 154:37f96f9d4de2 654
<> 154:37f96f9d4de2 655 /* Wait until the last data is sent */
<> 154:37f96f9d4de2 656 while (!(base->TCSR & I2S_TCSR_FWF_MASK))
<> 154:37f96f9d4de2 657 {
<> 154:37f96f9d4de2 658 }
<> 154:37f96f9d4de2 659 }
<> 154:37f96f9d4de2 660
<> 154:37f96f9d4de2 661 void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size)
<> 154:37f96f9d4de2 662 {
<> 154:37f96f9d4de2 663 uint32_t i = 0;
<> 154:37f96f9d4de2 664 uint8_t bytesPerWord = bitWidth / 8U;
<> 154:37f96f9d4de2 665
AnnaBridge 175:af195413fb11 666 while (i < size)
<> 154:37f96f9d4de2 667 {
<> 154:37f96f9d4de2 668 /* Wait until data is received */
<> 154:37f96f9d4de2 669 while (!(base->RCSR & I2S_RCSR_FWF_MASK))
<> 154:37f96f9d4de2 670 {
<> 154:37f96f9d4de2 671 }
<> 154:37f96f9d4de2 672
<> 154:37f96f9d4de2 673 SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord);
<> 154:37f96f9d4de2 674 buffer += bytesPerWord;
AnnaBridge 175:af195413fb11 675 i += bytesPerWord;
<> 154:37f96f9d4de2 676 }
<> 154:37f96f9d4de2 677 }
<> 154:37f96f9d4de2 678
<> 154:37f96f9d4de2 679 void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
<> 154:37f96f9d4de2 680 {
<> 154:37f96f9d4de2 681 assert(handle);
<> 154:37f96f9d4de2 682
AnnaBridge 175:af195413fb11 683 /* Zero the handle */
AnnaBridge 175:af195413fb11 684 memset(handle, 0, sizeof(*handle));
AnnaBridge 175:af195413fb11 685
<> 154:37f96f9d4de2 686 s_saiHandle[SAI_GetInstance(base)][0] = handle;
<> 154:37f96f9d4de2 687
<> 154:37f96f9d4de2 688 handle->callback = callback;
<> 154:37f96f9d4de2 689 handle->userData = userData;
<> 154:37f96f9d4de2 690
<> 154:37f96f9d4de2 691 /* Set the isr pointer */
<> 154:37f96f9d4de2 692 s_saiTxIsr = SAI_TransferTxHandleIRQ;
<> 154:37f96f9d4de2 693
<> 154:37f96f9d4de2 694 /* Enable Tx irq */
<> 154:37f96f9d4de2 695 EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]);
<> 154:37f96f9d4de2 696 }
<> 154:37f96f9d4de2 697
<> 154:37f96f9d4de2 698 void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData)
<> 154:37f96f9d4de2 699 {
<> 154:37f96f9d4de2 700 assert(handle);
<> 154:37f96f9d4de2 701
AnnaBridge 175:af195413fb11 702 /* Zero the handle */
AnnaBridge 175:af195413fb11 703 memset(handle, 0, sizeof(*handle));
AnnaBridge 175:af195413fb11 704
<> 154:37f96f9d4de2 705 s_saiHandle[SAI_GetInstance(base)][1] = handle;
<> 154:37f96f9d4de2 706
<> 154:37f96f9d4de2 707 handle->callback = callback;
<> 154:37f96f9d4de2 708 handle->userData = userData;
<> 154:37f96f9d4de2 709
<> 154:37f96f9d4de2 710 /* Set the isr pointer */
<> 154:37f96f9d4de2 711 s_saiRxIsr = SAI_TransferRxHandleIRQ;
<> 154:37f96f9d4de2 712
<> 154:37f96f9d4de2 713 /* Enable Rx irq */
<> 154:37f96f9d4de2 714 EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]);
<> 154:37f96f9d4de2 715 }
<> 154:37f96f9d4de2 716
<> 154:37f96f9d4de2 717 status_t SAI_TransferTxSetFormat(I2S_Type *base,
<> 154:37f96f9d4de2 718 sai_handle_t *handle,
<> 154:37f96f9d4de2 719 sai_transfer_format_t *format,
<> 154:37f96f9d4de2 720 uint32_t mclkSourceClockHz,
<> 154:37f96f9d4de2 721 uint32_t bclkSourceClockHz)
<> 154:37f96f9d4de2 722 {
<> 154:37f96f9d4de2 723 assert(handle);
<> 154:37f96f9d4de2 724
<> 154:37f96f9d4de2 725 if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz))
<> 154:37f96f9d4de2 726 {
<> 154:37f96f9d4de2 727 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 728 }
<> 154:37f96f9d4de2 729
<> 154:37f96f9d4de2 730 /* Copy format to handle */
<> 154:37f96f9d4de2 731 handle->bitWidth = format->bitWidth;
<> 154:37f96f9d4de2 732 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 733 handle->watermark = format->watermark;
<> 154:37f96f9d4de2 734 #endif
<> 154:37f96f9d4de2 735 handle->channel = format->channel;
<> 154:37f96f9d4de2 736
<> 154:37f96f9d4de2 737 SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
<> 154:37f96f9d4de2 738
<> 154:37f96f9d4de2 739 return kStatus_Success;
<> 154:37f96f9d4de2 740 }
<> 154:37f96f9d4de2 741
<> 154:37f96f9d4de2 742 status_t SAI_TransferRxSetFormat(I2S_Type *base,
<> 154:37f96f9d4de2 743 sai_handle_t *handle,
<> 154:37f96f9d4de2 744 sai_transfer_format_t *format,
<> 154:37f96f9d4de2 745 uint32_t mclkSourceClockHz,
<> 154:37f96f9d4de2 746 uint32_t bclkSourceClockHz)
<> 154:37f96f9d4de2 747 {
<> 154:37f96f9d4de2 748 assert(handle);
<> 154:37f96f9d4de2 749
<> 154:37f96f9d4de2 750 if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz))
<> 154:37f96f9d4de2 751 {
<> 154:37f96f9d4de2 752 return kStatus_InvalidArgument;
<> 154:37f96f9d4de2 753 }
<> 154:37f96f9d4de2 754
<> 154:37f96f9d4de2 755 /* Copy format to handle */
<> 154:37f96f9d4de2 756 handle->bitWidth = format->bitWidth;
<> 154:37f96f9d4de2 757 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 758 handle->watermark = format->watermark;
<> 154:37f96f9d4de2 759 #endif
<> 154:37f96f9d4de2 760 handle->channel = format->channel;
<> 154:37f96f9d4de2 761
<> 154:37f96f9d4de2 762 SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz);
<> 154:37f96f9d4de2 763
<> 154:37f96f9d4de2 764 return kStatus_Success;
<> 154:37f96f9d4de2 765 }
<> 154:37f96f9d4de2 766
<> 154:37f96f9d4de2 767 status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
<> 154:37f96f9d4de2 768 {
<> 154:37f96f9d4de2 769 assert(handle);
<> 154:37f96f9d4de2 770
<> 154:37f96f9d4de2 771 /* Check if the queue is full */
<> 154:37f96f9d4de2 772 if (handle->saiQueue[handle->queueUser].data)
<> 154:37f96f9d4de2 773 {
<> 154:37f96f9d4de2 774 return kStatus_SAI_QueueFull;
<> 154:37f96f9d4de2 775 }
<> 154:37f96f9d4de2 776
<> 154:37f96f9d4de2 777 /* Add into queue */
<> 154:37f96f9d4de2 778 handle->transferSize[handle->queueUser] = xfer->dataSize;
<> 154:37f96f9d4de2 779 handle->saiQueue[handle->queueUser].data = xfer->data;
<> 154:37f96f9d4de2 780 handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
<> 154:37f96f9d4de2 781 handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
<> 154:37f96f9d4de2 782
<> 154:37f96f9d4de2 783 /* Set the state to busy */
<> 154:37f96f9d4de2 784 handle->state = kSAI_Busy;
<> 154:37f96f9d4de2 785
<> 154:37f96f9d4de2 786 /* Enable interrupt */
<> 154:37f96f9d4de2 787 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 788 /* Use FIFO request interrupt and fifo error*/
<> 154:37f96f9d4de2 789 SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable);
<> 154:37f96f9d4de2 790 #else
<> 154:37f96f9d4de2 791 SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable);
<> 154:37f96f9d4de2 792 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
<> 154:37f96f9d4de2 793
<> 154:37f96f9d4de2 794 /* Enable Tx transfer */
<> 154:37f96f9d4de2 795 SAI_TxEnable(base, true);
<> 154:37f96f9d4de2 796
<> 154:37f96f9d4de2 797 return kStatus_Success;
<> 154:37f96f9d4de2 798 }
<> 154:37f96f9d4de2 799
<> 154:37f96f9d4de2 800 status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer)
<> 154:37f96f9d4de2 801 {
<> 154:37f96f9d4de2 802 assert(handle);
<> 154:37f96f9d4de2 803
<> 154:37f96f9d4de2 804 /* Check if the queue is full */
<> 154:37f96f9d4de2 805 if (handle->saiQueue[handle->queueUser].data)
<> 154:37f96f9d4de2 806 {
<> 154:37f96f9d4de2 807 return kStatus_SAI_QueueFull;
<> 154:37f96f9d4de2 808 }
<> 154:37f96f9d4de2 809
<> 154:37f96f9d4de2 810 /* Add into queue */
<> 154:37f96f9d4de2 811 handle->transferSize[handle->queueUser] = xfer->dataSize;
<> 154:37f96f9d4de2 812 handle->saiQueue[handle->queueUser].data = xfer->data;
<> 154:37f96f9d4de2 813 handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
<> 154:37f96f9d4de2 814 handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
<> 154:37f96f9d4de2 815
<> 154:37f96f9d4de2 816 /* Set state to busy */
<> 154:37f96f9d4de2 817 handle->state = kSAI_Busy;
<> 154:37f96f9d4de2 818
<> 154:37f96f9d4de2 819 /* Enable interrupt */
<> 154:37f96f9d4de2 820 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 821 /* Use FIFO request interrupt and fifo error*/
<> 154:37f96f9d4de2 822 SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable);
<> 154:37f96f9d4de2 823 #else
<> 154:37f96f9d4de2 824 SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable);
<> 154:37f96f9d4de2 825 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
<> 154:37f96f9d4de2 826
<> 154:37f96f9d4de2 827 /* Enable Rx transfer */
<> 154:37f96f9d4de2 828 SAI_RxEnable(base, true);
<> 154:37f96f9d4de2 829
<> 154:37f96f9d4de2 830 return kStatus_Success;
<> 154:37f96f9d4de2 831 }
<> 154:37f96f9d4de2 832
<> 154:37f96f9d4de2 833 status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
<> 154:37f96f9d4de2 834 {
<> 154:37f96f9d4de2 835 assert(handle);
<> 154:37f96f9d4de2 836
<> 154:37f96f9d4de2 837 status_t status = kStatus_Success;
<> 154:37f96f9d4de2 838
<> 154:37f96f9d4de2 839 if (handle->state != kSAI_Busy)
<> 154:37f96f9d4de2 840 {
<> 154:37f96f9d4de2 841 status = kStatus_NoTransferInProgress;
<> 154:37f96f9d4de2 842 }
<> 154:37f96f9d4de2 843 else
<> 154:37f96f9d4de2 844 {
<> 154:37f96f9d4de2 845 *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize);
<> 154:37f96f9d4de2 846 }
<> 154:37f96f9d4de2 847
<> 154:37f96f9d4de2 848 return status;
<> 154:37f96f9d4de2 849 }
<> 154:37f96f9d4de2 850
<> 154:37f96f9d4de2 851 status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count)
<> 154:37f96f9d4de2 852 {
<> 154:37f96f9d4de2 853 assert(handle);
<> 154:37f96f9d4de2 854
<> 154:37f96f9d4de2 855 status_t status = kStatus_Success;
<> 154:37f96f9d4de2 856
<> 154:37f96f9d4de2 857 if (handle->state != kSAI_Busy)
<> 154:37f96f9d4de2 858 {
<> 154:37f96f9d4de2 859 status = kStatus_NoTransferInProgress;
<> 154:37f96f9d4de2 860 }
<> 154:37f96f9d4de2 861 else
<> 154:37f96f9d4de2 862 {
<> 154:37f96f9d4de2 863 *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize);
<> 154:37f96f9d4de2 864 }
<> 154:37f96f9d4de2 865
<> 154:37f96f9d4de2 866 return status;
<> 154:37f96f9d4de2 867 }
<> 154:37f96f9d4de2 868
<> 154:37f96f9d4de2 869 void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle)
<> 154:37f96f9d4de2 870 {
<> 154:37f96f9d4de2 871 assert(handle);
<> 154:37f96f9d4de2 872
<> 154:37f96f9d4de2 873 /* Stop Tx transfer and disable interrupt */
<> 154:37f96f9d4de2 874 SAI_TxEnable(base, false);
<> 154:37f96f9d4de2 875 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 876 /* Use FIFO request interrupt and fifo error */
<> 154:37f96f9d4de2 877 SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable);
<> 154:37f96f9d4de2 878 #else
<> 154:37f96f9d4de2 879 SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable);
<> 154:37f96f9d4de2 880 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
<> 154:37f96f9d4de2 881
<> 154:37f96f9d4de2 882 handle->state = kSAI_Idle;
<> 154:37f96f9d4de2 883
<> 154:37f96f9d4de2 884 /* Clear the queue */
<> 154:37f96f9d4de2 885 memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE);
<> 154:37f96f9d4de2 886 handle->queueDriver = 0;
<> 154:37f96f9d4de2 887 handle->queueUser = 0;
<> 154:37f96f9d4de2 888 }
<> 154:37f96f9d4de2 889
<> 154:37f96f9d4de2 890 void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle)
<> 154:37f96f9d4de2 891 {
<> 154:37f96f9d4de2 892 assert(handle);
<> 154:37f96f9d4de2 893
<> 154:37f96f9d4de2 894 /* Stop Tx transfer and disable interrupt */
<> 154:37f96f9d4de2 895 SAI_RxEnable(base, false);
<> 154:37f96f9d4de2 896 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 897 /* Use FIFO request interrupt and fifo error */
<> 154:37f96f9d4de2 898 SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable);
<> 154:37f96f9d4de2 899 #else
<> 154:37f96f9d4de2 900 SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable);
<> 154:37f96f9d4de2 901 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
<> 154:37f96f9d4de2 902
<> 154:37f96f9d4de2 903 handle->state = kSAI_Idle;
<> 154:37f96f9d4de2 904
<> 154:37f96f9d4de2 905 /* Clear the queue */
<> 154:37f96f9d4de2 906 memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE);
<> 154:37f96f9d4de2 907 handle->queueDriver = 0;
<> 154:37f96f9d4de2 908 handle->queueUser = 0;
<> 154:37f96f9d4de2 909 }
<> 154:37f96f9d4de2 910
<> 154:37f96f9d4de2 911 void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
<> 154:37f96f9d4de2 912 {
<> 154:37f96f9d4de2 913 assert(handle);
<> 154:37f96f9d4de2 914
<> 154:37f96f9d4de2 915 uint8_t *buffer = handle->saiQueue[handle->queueDriver].data;
<> 154:37f96f9d4de2 916 uint8_t dataSize = handle->bitWidth / 8U;
<> 154:37f96f9d4de2 917
<> 154:37f96f9d4de2 918 /* Handle Error */
<> 154:37f96f9d4de2 919 if (base->TCSR & I2S_TCSR_FEF_MASK)
<> 154:37f96f9d4de2 920 {
<> 154:37f96f9d4de2 921 /* Clear FIFO error flag to continue transfer */
<> 154:37f96f9d4de2 922 SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag);
<> 154:37f96f9d4de2 923
<> 154:37f96f9d4de2 924 /* Call the callback */
<> 154:37f96f9d4de2 925 if (handle->callback)
<> 154:37f96f9d4de2 926 {
<> 154:37f96f9d4de2 927 (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData);
<> 154:37f96f9d4de2 928 }
<> 154:37f96f9d4de2 929 }
<> 154:37f96f9d4de2 930
<> 154:37f96f9d4de2 931 /* Handle transfer */
<> 154:37f96f9d4de2 932 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 933 if (base->TCSR & I2S_TCSR_FRF_MASK)
<> 154:37f96f9d4de2 934 {
<> 154:37f96f9d4de2 935 /* Judge if the data need to transmit is less than space */
<> 154:37f96f9d4de2 936 uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize),
<> 154:37f96f9d4de2 937 (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize));
<> 154:37f96f9d4de2 938
<> 154:37f96f9d4de2 939 /* Copy the data from sai buffer to FIFO */
<> 154:37f96f9d4de2 940 SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size);
<> 154:37f96f9d4de2 941
<> 154:37f96f9d4de2 942 /* Update the internal counter */
<> 154:37f96f9d4de2 943 handle->saiQueue[handle->queueDriver].dataSize -= size;
<> 154:37f96f9d4de2 944 handle->saiQueue[handle->queueDriver].data += size;
<> 154:37f96f9d4de2 945 }
<> 154:37f96f9d4de2 946 #else
<> 154:37f96f9d4de2 947 if (base->TCSR & I2S_TCSR_FWF_MASK)
<> 154:37f96f9d4de2 948 {
<> 154:37f96f9d4de2 949 uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize);
<> 154:37f96f9d4de2 950
<> 154:37f96f9d4de2 951 SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size);
<> 154:37f96f9d4de2 952
<> 154:37f96f9d4de2 953 /* Update internal counter */
<> 154:37f96f9d4de2 954 handle->saiQueue[handle->queueDriver].dataSize -= size;
<> 154:37f96f9d4de2 955 handle->saiQueue[handle->queueDriver].data += size;
<> 154:37f96f9d4de2 956 }
<> 154:37f96f9d4de2 957 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
<> 154:37f96f9d4de2 958
<> 154:37f96f9d4de2 959 /* If finished a blcok, call the callback function */
<> 154:37f96f9d4de2 960 if (handle->saiQueue[handle->queueDriver].dataSize == 0U)
<> 154:37f96f9d4de2 961 {
<> 154:37f96f9d4de2 962 memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t));
<> 154:37f96f9d4de2 963 handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE;
<> 154:37f96f9d4de2 964 if (handle->callback)
<> 154:37f96f9d4de2 965 {
<> 154:37f96f9d4de2 966 (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData);
<> 154:37f96f9d4de2 967 }
<> 154:37f96f9d4de2 968 }
<> 154:37f96f9d4de2 969
<> 154:37f96f9d4de2 970 /* If all data finished, just stop the transfer */
<> 154:37f96f9d4de2 971 if (handle->saiQueue[handle->queueDriver].data == NULL)
<> 154:37f96f9d4de2 972 {
<> 154:37f96f9d4de2 973 SAI_TransferAbortSend(base, handle);
<> 154:37f96f9d4de2 974 }
<> 154:37f96f9d4de2 975 }
<> 154:37f96f9d4de2 976
<> 154:37f96f9d4de2 977 void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle)
<> 154:37f96f9d4de2 978 {
<> 154:37f96f9d4de2 979 assert(handle);
<> 154:37f96f9d4de2 980
<> 154:37f96f9d4de2 981 uint8_t *buffer = handle->saiQueue[handle->queueDriver].data;
<> 154:37f96f9d4de2 982 uint8_t dataSize = handle->bitWidth / 8U;
<> 154:37f96f9d4de2 983
<> 154:37f96f9d4de2 984 /* Handle Error */
<> 154:37f96f9d4de2 985 if (base->RCSR & I2S_RCSR_FEF_MASK)
<> 154:37f96f9d4de2 986 {
<> 154:37f96f9d4de2 987 /* Clear FIFO error flag to continue transfer */
<> 154:37f96f9d4de2 988 SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag);
<> 154:37f96f9d4de2 989
<> 154:37f96f9d4de2 990 /* Call the callback */
<> 154:37f96f9d4de2 991 if (handle->callback)
<> 154:37f96f9d4de2 992 {
<> 154:37f96f9d4de2 993 (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData);
<> 154:37f96f9d4de2 994 }
<> 154:37f96f9d4de2 995 }
<> 154:37f96f9d4de2 996
<> 154:37f96f9d4de2 997 /* Handle transfer */
<> 154:37f96f9d4de2 998 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
<> 154:37f96f9d4de2 999 if (base->RCSR & I2S_RCSR_FRF_MASK)
<> 154:37f96f9d4de2 1000 {
<> 154:37f96f9d4de2 1001 /* Judge if the data need to transmit is less than space */
<> 154:37f96f9d4de2 1002 uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize));
<> 154:37f96f9d4de2 1003
<> 154:37f96f9d4de2 1004 /* Copy the data from sai buffer to FIFO */
<> 154:37f96f9d4de2 1005 SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size);
<> 154:37f96f9d4de2 1006
<> 154:37f96f9d4de2 1007 /* Update the internal counter */
<> 154:37f96f9d4de2 1008 handle->saiQueue[handle->queueDriver].dataSize -= size;
<> 154:37f96f9d4de2 1009 handle->saiQueue[handle->queueDriver].data += size;
<> 154:37f96f9d4de2 1010 }
<> 154:37f96f9d4de2 1011 #else
<> 154:37f96f9d4de2 1012 if (base->RCSR & I2S_RCSR_FWF_MASK)
<> 154:37f96f9d4de2 1013 {
<> 154:37f96f9d4de2 1014 uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize);
<> 154:37f96f9d4de2 1015
<> 154:37f96f9d4de2 1016 SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size);
<> 154:37f96f9d4de2 1017
<> 154:37f96f9d4de2 1018 /* Update internal state */
<> 154:37f96f9d4de2 1019 handle->saiQueue[handle->queueDriver].dataSize -= size;
<> 154:37f96f9d4de2 1020 handle->saiQueue[handle->queueDriver].data += size;
<> 154:37f96f9d4de2 1021 }
<> 154:37f96f9d4de2 1022 #endif /* FSL_FEATURE_SAI_FIFO_COUNT */
<> 154:37f96f9d4de2 1023
<> 154:37f96f9d4de2 1024 /* If finished a blcok, call the callback function */
<> 154:37f96f9d4de2 1025 if (handle->saiQueue[handle->queueDriver].dataSize == 0U)
<> 154:37f96f9d4de2 1026 {
<> 154:37f96f9d4de2 1027 memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t));
<> 154:37f96f9d4de2 1028 handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE;
<> 154:37f96f9d4de2 1029 if (handle->callback)
<> 154:37f96f9d4de2 1030 {
<> 154:37f96f9d4de2 1031 (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData);
<> 154:37f96f9d4de2 1032 }
<> 154:37f96f9d4de2 1033 }
<> 154:37f96f9d4de2 1034
<> 154:37f96f9d4de2 1035 /* If all data finished, just stop the transfer */
<> 154:37f96f9d4de2 1036 if (handle->saiQueue[handle->queueDriver].data == NULL)
<> 154:37f96f9d4de2 1037 {
<> 154:37f96f9d4de2 1038 SAI_TransferAbortReceive(base, handle);
<> 154:37f96f9d4de2 1039 }
<> 154:37f96f9d4de2 1040 }
<> 154:37f96f9d4de2 1041
<> 154:37f96f9d4de2 1042 #if defined(I2S0)
<> 154:37f96f9d4de2 1043 void I2S0_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1044 {
AnnaBridge 175:af195413fb11 1045 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
AnnaBridge 175:af195413fb11 1046 if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFORequestFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1047 ((I2S0->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1048 #else
AnnaBridge 175:af195413fb11 1049 if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1050 ((I2S0->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1051 #endif
<> 154:37f96f9d4de2 1052 {
<> 154:37f96f9d4de2 1053 s_saiRxIsr(I2S0, s_saiHandle[0][1]);
<> 154:37f96f9d4de2 1054 }
AnnaBridge 175:af195413fb11 1055 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
AnnaBridge 175:af195413fb11 1056 if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFORequestFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1057 ((I2S0->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1058 #else
AnnaBridge 175:af195413fb11 1059 if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1060 ((I2S0->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1061 #endif
<> 154:37f96f9d4de2 1062 {
<> 154:37f96f9d4de2 1063 s_saiTxIsr(I2S0, s_saiHandle[0][0]);
<> 154:37f96f9d4de2 1064 }
<> 154:37f96f9d4de2 1065 }
AnnaBridge 175:af195413fb11 1066
<> 154:37f96f9d4de2 1067 void I2S0_Tx_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1068 {
<> 154:37f96f9d4de2 1069 assert(s_saiHandle[0][0]);
<> 154:37f96f9d4de2 1070 s_saiTxIsr(I2S0, s_saiHandle[0][0]);
<> 154:37f96f9d4de2 1071 }
<> 154:37f96f9d4de2 1072
<> 154:37f96f9d4de2 1073 void I2S0_Rx_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1074 {
<> 154:37f96f9d4de2 1075 assert(s_saiHandle[0][1]);
<> 154:37f96f9d4de2 1076 s_saiRxIsr(I2S0, s_saiHandle[0][1]);
<> 154:37f96f9d4de2 1077 }
<> 154:37f96f9d4de2 1078 #endif /* I2S0*/
<> 154:37f96f9d4de2 1079
<> 154:37f96f9d4de2 1080 #if defined(I2S1)
AnnaBridge 175:af195413fb11 1081 void I2S1_DriverIRQHandler(void)
AnnaBridge 175:af195413fb11 1082 {
AnnaBridge 175:af195413fb11 1083 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
AnnaBridge 175:af195413fb11 1084 if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFORequestFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1085 ((I2S1->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1086 #else
AnnaBridge 175:af195413fb11 1087 if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFOWarningFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1088 ((I2S1->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1089 #endif
AnnaBridge 175:af195413fb11 1090 {
AnnaBridge 175:af195413fb11 1091 s_saiRxIsr(I2S1, s_saiHandle[1][1]);
AnnaBridge 175:af195413fb11 1092 }
AnnaBridge 175:af195413fb11 1093 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
AnnaBridge 175:af195413fb11 1094 if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFORequestFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1095 ((I2S1->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1096 #else
AnnaBridge 175:af195413fb11 1097 if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFOWarningFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1098 ((I2S1->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1099 #endif
AnnaBridge 175:af195413fb11 1100 {
AnnaBridge 175:af195413fb11 1101 s_saiTxIsr(I2S1, s_saiHandle[1][0]);
AnnaBridge 175:af195413fb11 1102 }
AnnaBridge 175:af195413fb11 1103 }
AnnaBridge 175:af195413fb11 1104
<> 154:37f96f9d4de2 1105 void I2S1_Tx_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1106 {
<> 154:37f96f9d4de2 1107 assert(s_saiHandle[1][0]);
<> 154:37f96f9d4de2 1108 s_saiTxIsr(I2S1, s_saiHandle[1][0]);
<> 154:37f96f9d4de2 1109 }
<> 154:37f96f9d4de2 1110
<> 154:37f96f9d4de2 1111 void I2S1_Rx_DriverIRQHandler(void)
<> 154:37f96f9d4de2 1112 {
<> 154:37f96f9d4de2 1113 assert(s_saiHandle[1][1]);
<> 154:37f96f9d4de2 1114 s_saiRxIsr(I2S1, s_saiHandle[1][1]);
<> 154:37f96f9d4de2 1115 }
AnnaBridge 175:af195413fb11 1116 #endif /* I2S1*/
AnnaBridge 175:af195413fb11 1117
AnnaBridge 175:af195413fb11 1118 #if defined(I2S2)
AnnaBridge 175:af195413fb11 1119 void I2S2_DriverIRQHandler(void)
AnnaBridge 175:af195413fb11 1120 {
AnnaBridge 175:af195413fb11 1121 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
AnnaBridge 175:af195413fb11 1122 if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFORequestFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1123 ((I2S2->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1124 #else
AnnaBridge 175:af195413fb11 1125 if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFOWarningFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1126 ((I2S2->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable)))
<> 154:37f96f9d4de2 1127 #endif
AnnaBridge 175:af195413fb11 1128 {
AnnaBridge 175:af195413fb11 1129 s_saiRxIsr(I2S2, s_saiHandle[2][1]);
AnnaBridge 175:af195413fb11 1130 }
AnnaBridge 175:af195413fb11 1131 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
AnnaBridge 175:af195413fb11 1132 if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFORequestFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1133 ((I2S2->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1134 #else
AnnaBridge 175:af195413fb11 1135 if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFOWarningFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1136 ((I2S2->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1137 #endif
AnnaBridge 175:af195413fb11 1138 {
AnnaBridge 175:af195413fb11 1139 s_saiTxIsr(I2S2, s_saiHandle[2][0]);
AnnaBridge 175:af195413fb11 1140 }
AnnaBridge 175:af195413fb11 1141 }
AnnaBridge 175:af195413fb11 1142
AnnaBridge 175:af195413fb11 1143 void I2S2_Tx_DriverIRQHandler(void)
AnnaBridge 175:af195413fb11 1144 {
AnnaBridge 175:af195413fb11 1145 assert(s_saiHandle[2][0]);
AnnaBridge 175:af195413fb11 1146 s_saiTxIsr(I2S2, s_saiHandle[2][0]);
AnnaBridge 175:af195413fb11 1147 }
AnnaBridge 175:af195413fb11 1148
AnnaBridge 175:af195413fb11 1149 void I2S2_Rx_DriverIRQHandler(void)
AnnaBridge 175:af195413fb11 1150 {
AnnaBridge 175:af195413fb11 1151 assert(s_saiHandle[2][1]);
AnnaBridge 175:af195413fb11 1152 s_saiRxIsr(I2S2, s_saiHandle[2][1]);
AnnaBridge 175:af195413fb11 1153 }
AnnaBridge 175:af195413fb11 1154 #endif /* I2S2*/
AnnaBridge 175:af195413fb11 1155
AnnaBridge 175:af195413fb11 1156 #if defined(I2S3)
AnnaBridge 175:af195413fb11 1157 void I2S3_DriverIRQHandler(void)
AnnaBridge 175:af195413fb11 1158 {
AnnaBridge 175:af195413fb11 1159 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
AnnaBridge 175:af195413fb11 1160 if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFORequestFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1161 ((I2S3->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1162 #else
AnnaBridge 175:af195413fb11 1163 if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFOWarningFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1164 ((I2S3->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1165 #endif
AnnaBridge 175:af195413fb11 1166 {
AnnaBridge 175:af195413fb11 1167 s_saiRxIsr(I2S3, s_saiHandle[3][1]);
AnnaBridge 175:af195413fb11 1168 }
AnnaBridge 175:af195413fb11 1169 #if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
AnnaBridge 175:af195413fb11 1170 if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFORequestFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1171 ((I2S3->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1172 #else
AnnaBridge 175:af195413fb11 1173 if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFOWarningFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) &&
AnnaBridge 175:af195413fb11 1174 ((I2S3->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable)))
AnnaBridge 175:af195413fb11 1175 #endif
AnnaBridge 175:af195413fb11 1176 {
AnnaBridge 175:af195413fb11 1177 s_saiTxIsr(I2S3, s_saiHandle[3][0]);
AnnaBridge 175:af195413fb11 1178 }
AnnaBridge 175:af195413fb11 1179 }
AnnaBridge 175:af195413fb11 1180
AnnaBridge 175:af195413fb11 1181 void I2S3_Tx_DriverIRQHandler(void)
AnnaBridge 175:af195413fb11 1182 {
AnnaBridge 175:af195413fb11 1183 assert(s_saiHandle[3][0]);
AnnaBridge 175:af195413fb11 1184 s_saiTxIsr(I2S3, s_saiHandle[3][0]);
AnnaBridge 175:af195413fb11 1185 }
AnnaBridge 175:af195413fb11 1186
AnnaBridge 175:af195413fb11 1187 void I2S3_Rx_DriverIRQHandler(void)
AnnaBridge 175:af195413fb11 1188 {
AnnaBridge 175:af195413fb11 1189 assert(s_saiHandle[3][1]);
AnnaBridge 175:af195413fb11 1190 s_saiRxIsr(I2S3, s_saiHandle[3][1]);
AnnaBridge 175:af195413fb11 1191 }
AnnaBridge 175:af195413fb11 1192 #endif /* I2S3*/