mbed library sources. Supersedes mbed-src.
Dependents: Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more
Fork of mbed-dev by
cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S@181:36facd806e4a, 2018-07-30 (annotated)
- Committer:
- benkatz
- Date:
- Mon Jul 30 20:31:44 2018 +0000
- Revision:
- 181:36facd806e4a
- Parent:
- 172:7d866c31b3c5
going on the robot. fixed a dumb bug in float_to_uint
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 172:7d866c31b3c5 | 1 | /* Copyright (c) 2009 - 2012 ARM LIMITED |
AnnaBridge | 172:7d866c31b3c5 | 2 | |
AnnaBridge | 172:7d866c31b3c5 | 3 | All rights reserved. |
AnnaBridge | 172:7d866c31b3c5 | 4 | Redistribution and use in source and binary forms, with or without |
AnnaBridge | 172:7d866c31b3c5 | 5 | modification, are permitted provided that the following conditions are met: |
AnnaBridge | 172:7d866c31b3c5 | 6 | - Redistributions of source code must retain the above copyright |
AnnaBridge | 172:7d866c31b3c5 | 7 | notice, this list of conditions and the following disclaimer. |
AnnaBridge | 172:7d866c31b3c5 | 8 | - Redistributions in binary form must reproduce the above copyright |
AnnaBridge | 172:7d866c31b3c5 | 9 | notice, this list of conditions and the following disclaimer in the |
AnnaBridge | 172:7d866c31b3c5 | 10 | documentation and/or other materials provided with the distribution. |
AnnaBridge | 172:7d866c31b3c5 | 11 | - Neither the name of ARM nor the names of its contributors may be used |
AnnaBridge | 172:7d866c31b3c5 | 12 | to endorse or promote products derived from this software without |
AnnaBridge | 172:7d866c31b3c5 | 13 | specific prior written permission. |
AnnaBridge | 172:7d866c31b3c5 | 14 | * |
AnnaBridge | 172:7d866c31b3c5 | 15 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 172:7d866c31b3c5 | 16 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 172:7d866c31b3c5 | 17 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
AnnaBridge | 172:7d866c31b3c5 | 18 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
AnnaBridge | 172:7d866c31b3c5 | 19 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
AnnaBridge | 172:7d866c31b3c5 | 20 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
AnnaBridge | 172:7d866c31b3c5 | 21 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
AnnaBridge | 172:7d866c31b3c5 | 22 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
AnnaBridge | 172:7d866c31b3c5 | 23 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
AnnaBridge | 172:7d866c31b3c5 | 24 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 172:7d866c31b3c5 | 25 | POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 172:7d866c31b3c5 | 26 | ---------------------------------------------------------------------------*/ |
AnnaBridge | 172:7d866c31b3c5 | 27 | |
AnnaBridge | 172:7d866c31b3c5 | 28 | /*---------------------------------------------------------------------------- |
AnnaBridge | 172:7d866c31b3c5 | 29 | * Functions |
AnnaBridge | 172:7d866c31b3c5 | 30 | *---------------------------------------------------------------------------*/ |
AnnaBridge | 172:7d866c31b3c5 | 31 | SECTION `.text`:CODE:NOROOT(2) |
AnnaBridge | 172:7d866c31b3c5 | 32 | arm |
AnnaBridge | 172:7d866c31b3c5 | 33 | PUBLIC __v7_all_cache |
AnnaBridge | 172:7d866c31b3c5 | 34 | /* |
AnnaBridge | 172:7d866c31b3c5 | 35 | * __STATIC_ASM void __v7_all_cache(uint32_t op) { |
AnnaBridge | 172:7d866c31b3c5 | 36 | */ |
AnnaBridge | 172:7d866c31b3c5 | 37 | |
AnnaBridge | 172:7d866c31b3c5 | 38 | __v7_all_cache: |
AnnaBridge | 172:7d866c31b3c5 | 39 | |
AnnaBridge | 172:7d866c31b3c5 | 40 | |
AnnaBridge | 172:7d866c31b3c5 | 41 | PUSH {R4-R11} |
AnnaBridge | 172:7d866c31b3c5 | 42 | |
AnnaBridge | 172:7d866c31b3c5 | 43 | MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */ |
AnnaBridge | 172:7d866c31b3c5 | 44 | ANDS R3, R6, #0x07000000 /* Extract coherency level */ |
AnnaBridge | 172:7d866c31b3c5 | 45 | MOV R3, R3, LSR #23 /* Total cache levels << 1 */ |
AnnaBridge | 172:7d866c31b3c5 | 46 | BEQ Finished /* If 0, no need to clean */ |
AnnaBridge | 172:7d866c31b3c5 | 47 | |
AnnaBridge | 172:7d866c31b3c5 | 48 | MOV R10, #0 /* R10 holds current cache level << 1 */ |
AnnaBridge | 172:7d866c31b3c5 | 49 | Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */ |
AnnaBridge | 172:7d866c31b3c5 | 50 | MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */ |
AnnaBridge | 172:7d866c31b3c5 | 51 | AND R1, R1, #7 /* Isolate those lower 3 bits */ |
AnnaBridge | 172:7d866c31b3c5 | 52 | CMP R1, #2 |
AnnaBridge | 172:7d866c31b3c5 | 53 | BLT Skip /* No cache or only instruction cache at this level */ |
AnnaBridge | 172:7d866c31b3c5 | 54 | |
AnnaBridge | 172:7d866c31b3c5 | 55 | MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */ |
AnnaBridge | 172:7d866c31b3c5 | 56 | ISB /* ISB to sync the change to the CacheSizeID reg */ |
AnnaBridge | 172:7d866c31b3c5 | 57 | MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */ |
AnnaBridge | 172:7d866c31b3c5 | 58 | AND R2, R1, #7 /* Extract the line length field */ |
AnnaBridge | 172:7d866c31b3c5 | 59 | ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */ |
AnnaBridge | 172:7d866c31b3c5 | 60 | LDR R4, =0x3FF |
AnnaBridge | 172:7d866c31b3c5 | 61 | ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */ |
AnnaBridge | 172:7d866c31b3c5 | 62 | CLZ R5, R4 /* R5 is the bit position of the way size increment */ |
AnnaBridge | 172:7d866c31b3c5 | 63 | LDR R7, =0x7FFF |
AnnaBridge | 172:7d866c31b3c5 | 64 | ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */ |
AnnaBridge | 172:7d866c31b3c5 | 65 | |
AnnaBridge | 172:7d866c31b3c5 | 66 | Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */ |
AnnaBridge | 172:7d866c31b3c5 | 67 | |
AnnaBridge | 172:7d866c31b3c5 | 68 | Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */ |
AnnaBridge | 172:7d866c31b3c5 | 69 | ORR R11, R11, R7, LSL R2 /* Factor in the Set number */ |
AnnaBridge | 172:7d866c31b3c5 | 70 | CMP R0, #0 |
AnnaBridge | 172:7d866c31b3c5 | 71 | BNE Dccsw |
AnnaBridge | 172:7d866c31b3c5 | 72 | MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */ |
AnnaBridge | 172:7d866c31b3c5 | 73 | B cont |
AnnaBridge | 172:7d866c31b3c5 | 74 | Dccsw: CMP R0, #1 |
AnnaBridge | 172:7d866c31b3c5 | 75 | BNE Dccisw |
AnnaBridge | 172:7d866c31b3c5 | 76 | MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */ |
AnnaBridge | 172:7d866c31b3c5 | 77 | B cont |
AnnaBridge | 172:7d866c31b3c5 | 78 | Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */ |
AnnaBridge | 172:7d866c31b3c5 | 79 | cont: SUBS R9, R9, #1 /* Decrement the Way number */ |
AnnaBridge | 172:7d866c31b3c5 | 80 | BGE Loop3 |
AnnaBridge | 172:7d866c31b3c5 | 81 | SUBS R7, R7, #1 /* Decrement the Set number */ |
AnnaBridge | 172:7d866c31b3c5 | 82 | BGE Loop2 |
AnnaBridge | 172:7d866c31b3c5 | 83 | Skip: ADD R10, R10, #2 /* increment the cache number */ |
AnnaBridge | 172:7d866c31b3c5 | 84 | CMP R3, R10 |
AnnaBridge | 172:7d866c31b3c5 | 85 | BGT Loop1 |
AnnaBridge | 172:7d866c31b3c5 | 86 | |
AnnaBridge | 172:7d866c31b3c5 | 87 | Finished: |
AnnaBridge | 172:7d866c31b3c5 | 88 | DSB |
AnnaBridge | 172:7d866c31b3c5 | 89 | POP {R4-R11} |
AnnaBridge | 172:7d866c31b3c5 | 90 | BX lr |
AnnaBridge | 172:7d866c31b3c5 | 91 | |
AnnaBridge | 172:7d866c31b3c5 | 92 | |
AnnaBridge | 172:7d866c31b3c5 | 93 | END |
AnnaBridge | 172:7d866c31b3c5 | 94 | /*---------------------------------------------------------------------------- |
AnnaBridge | 172:7d866c31b3c5 | 95 | * end of file |
AnnaBridge | 172:7d866c31b3c5 | 96 | *---------------------------------------------------------------------------*/ |
AnnaBridge | 172:7d866c31b3c5 | 97 |