ban4jp -
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uIP-1-0_webserver
uIP 1.0 based webserver for LPC1114 + ENC28J60
dev-enc28j60/enc28j60.h@0:685224d2f66d, 2014-06-14 (annotated)
- Committer:
- ban4jp
- Date:
- Sat Jun 14 16:02:21 2014 +0000
- Revision:
- 0:685224d2f66d
initial commit.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
ban4jp | 0:685224d2f66d | 1 | #ifndef ENC28J60_H |
ban4jp | 0:685224d2f66d | 2 | #define ENC28J60_H |
ban4jp | 0:685224d2f66d | 3 | |
ban4jp | 0:685224d2f66d | 4 | #include "mbed.h" |
ban4jp | 0:685224d2f66d | 5 | |
ban4jp | 0:685224d2f66d | 6 | typedef unsigned char u8; |
ban4jp | 0:685224d2f66d | 7 | typedef unsigned short int u16; |
ban4jp | 0:685224d2f66d | 8 | //typedef unsigned int u32; |
ban4jp | 0:685224d2f66d | 9 | |
ban4jp | 0:685224d2f66d | 10 | // ENC28J60 Control Registers |
ban4jp | 0:685224d2f66d | 11 | // Control register definitions are a combination of address, |
ban4jp | 0:685224d2f66d | 12 | // bank number, and Ethernet/MAC/PHY indicator bits. |
ban4jp | 0:685224d2f66d | 13 | // - Register address (bits 0-4) |
ban4jp | 0:685224d2f66d | 14 | // - Bank number (bits 5-6) |
ban4jp | 0:685224d2f66d | 15 | // - MAC/PHY indicator (bit 7) |
ban4jp | 0:685224d2f66d | 16 | #define ADDR_MASK 0x1F |
ban4jp | 0:685224d2f66d | 17 | #define BANK_MASK 0x60 |
ban4jp | 0:685224d2f66d | 18 | #define SPRD_MASK 0x80 |
ban4jp | 0:685224d2f66d | 19 | // All-bank registers |
ban4jp | 0:685224d2f66d | 20 | #define EIE 0x1B |
ban4jp | 0:685224d2f66d | 21 | #define EIR 0x1C |
ban4jp | 0:685224d2f66d | 22 | #define ESTAT 0x1D |
ban4jp | 0:685224d2f66d | 23 | #define ECON2 0x1E |
ban4jp | 0:685224d2f66d | 24 | #define ECON1 0x1F |
ban4jp | 0:685224d2f66d | 25 | // Bank 0 registers |
ban4jp | 0:685224d2f66d | 26 | #define ERDPTL (0x00|0x00) |
ban4jp | 0:685224d2f66d | 27 | #define ERDPTH (0x01|0x00) |
ban4jp | 0:685224d2f66d | 28 | #define EWRPTL (0x02|0x00) |
ban4jp | 0:685224d2f66d | 29 | #define EWRPTH (0x03|0x00) |
ban4jp | 0:685224d2f66d | 30 | #define ETXSTL (0x04|0x00) |
ban4jp | 0:685224d2f66d | 31 | #define ETXSTH (0x05|0x00) |
ban4jp | 0:685224d2f66d | 32 | #define ETXNDL (0x06|0x00) |
ban4jp | 0:685224d2f66d | 33 | #define ETXNDH (0x07|0x00) |
ban4jp | 0:685224d2f66d | 34 | #define ERXSTL (0x08|0x00) |
ban4jp | 0:685224d2f66d | 35 | #define ERXSTH (0x09|0x00) |
ban4jp | 0:685224d2f66d | 36 | #define ERXNDL (0x0A|0x00) |
ban4jp | 0:685224d2f66d | 37 | #define ERXNDH (0x0B|0x00) |
ban4jp | 0:685224d2f66d | 38 | #define ERXRDPTL (0x0C|0x00) |
ban4jp | 0:685224d2f66d | 39 | #define ERXRDPTH (0x0D|0x00) |
ban4jp | 0:685224d2f66d | 40 | #define ERXWRPTL (0x0E|0x00) |
ban4jp | 0:685224d2f66d | 41 | #define ERXWRPTH (0x0F|0x00) |
ban4jp | 0:685224d2f66d | 42 | #define EDMASTL (0x10|0x00) |
ban4jp | 0:685224d2f66d | 43 | #define EDMASTH (0x11|0x00) |
ban4jp | 0:685224d2f66d | 44 | #define EDMANDL (0x12|0x00) |
ban4jp | 0:685224d2f66d | 45 | #define EDMANDH (0x13|0x00) |
ban4jp | 0:685224d2f66d | 46 | #define EDMADSTL (0x14|0x00) |
ban4jp | 0:685224d2f66d | 47 | #define EDMADSTH (0x15|0x00) |
ban4jp | 0:685224d2f66d | 48 | #define EDMACSL (0x16|0x00) |
ban4jp | 0:685224d2f66d | 49 | #define EDMACSH (0x17|0x00) |
ban4jp | 0:685224d2f66d | 50 | // Bank 1 registers |
ban4jp | 0:685224d2f66d | 51 | #define EHT0 (0x00|0x20) |
ban4jp | 0:685224d2f66d | 52 | #define EHT1 (0x01|0x20) |
ban4jp | 0:685224d2f66d | 53 | #define EHT2 (0x02|0x20) |
ban4jp | 0:685224d2f66d | 54 | #define EHT3 (0x03|0x20) |
ban4jp | 0:685224d2f66d | 55 | #define EHT4 (0x04|0x20) |
ban4jp | 0:685224d2f66d | 56 | #define EHT5 (0x05|0x20) |
ban4jp | 0:685224d2f66d | 57 | #define EHT6 (0x06|0x20) |
ban4jp | 0:685224d2f66d | 58 | #define EHT7 (0x07|0x20) |
ban4jp | 0:685224d2f66d | 59 | #define EPMM0 (0x08|0x20) |
ban4jp | 0:685224d2f66d | 60 | #define EPMM1 (0x09|0x20) |
ban4jp | 0:685224d2f66d | 61 | #define EPMM2 (0x0A|0x20) |
ban4jp | 0:685224d2f66d | 62 | #define EPMM3 (0x0B|0x20) |
ban4jp | 0:685224d2f66d | 63 | #define EPMM4 (0x0C|0x20) |
ban4jp | 0:685224d2f66d | 64 | #define EPMM5 (0x0D|0x20) |
ban4jp | 0:685224d2f66d | 65 | #define EPMM6 (0x0E|0x20) |
ban4jp | 0:685224d2f66d | 66 | #define EPMM7 (0x0F|0x20) |
ban4jp | 0:685224d2f66d | 67 | #define EPMCSL (0x10|0x20) |
ban4jp | 0:685224d2f66d | 68 | #define EPMCSH (0x11|0x20) |
ban4jp | 0:685224d2f66d | 69 | #define EPMOL (0x14|0x20) |
ban4jp | 0:685224d2f66d | 70 | #define EPMOH (0x15|0x20) |
ban4jp | 0:685224d2f66d | 71 | #define EWOLIE (0x16|0x20) |
ban4jp | 0:685224d2f66d | 72 | #define EWOLIR (0x17|0x20) |
ban4jp | 0:685224d2f66d | 73 | #define ERXFCON (0x18|0x20) |
ban4jp | 0:685224d2f66d | 74 | #define EPKTCNT (0x19|0x20) |
ban4jp | 0:685224d2f66d | 75 | // Bank 2 registers |
ban4jp | 0:685224d2f66d | 76 | #define MACON1 (0x00|0x40|0x80) |
ban4jp | 0:685224d2f66d | 77 | #define MACON2 (0x01|0x40|0x80) |
ban4jp | 0:685224d2f66d | 78 | #define MACON3 (0x02|0x40|0x80) |
ban4jp | 0:685224d2f66d | 79 | #define MACON4 (0x03|0x40|0x80) |
ban4jp | 0:685224d2f66d | 80 | #define MABBIPG (0x04|0x40|0x80) |
ban4jp | 0:685224d2f66d | 81 | #define MAIPGL (0x06|0x40|0x80) |
ban4jp | 0:685224d2f66d | 82 | #define MAIPGH (0x07|0x40|0x80) |
ban4jp | 0:685224d2f66d | 83 | #define MACLCON1 (0x08|0x40|0x80) |
ban4jp | 0:685224d2f66d | 84 | #define MACLCON2 (0x09|0x40|0x80) |
ban4jp | 0:685224d2f66d | 85 | #define MAMXFLL (0x0A|0x40|0x80) |
ban4jp | 0:685224d2f66d | 86 | #define MAMXFLH (0x0B|0x40|0x80) |
ban4jp | 0:685224d2f66d | 87 | #define MAPHSUP (0x0D|0x40|0x80) |
ban4jp | 0:685224d2f66d | 88 | #define MICON (0x11|0x40|0x80) |
ban4jp | 0:685224d2f66d | 89 | #define MICMD (0x12|0x40|0x80) |
ban4jp | 0:685224d2f66d | 90 | #define MIREGADR (0x14|0x40|0x80) |
ban4jp | 0:685224d2f66d | 91 | #define MIWRL (0x16|0x40|0x80) |
ban4jp | 0:685224d2f66d | 92 | #define MIWRH (0x17|0x40|0x80) |
ban4jp | 0:685224d2f66d | 93 | #define MIRDL (0x18|0x40|0x80) |
ban4jp | 0:685224d2f66d | 94 | #define MIRDH (0x19|0x40|0x80) |
ban4jp | 0:685224d2f66d | 95 | // Bank 3 registers |
ban4jp | 0:685224d2f66d | 96 | #define MAADR1 (0x00|0x60|0x80) |
ban4jp | 0:685224d2f66d | 97 | #define MAADR0 (0x01|0x60|0x80) |
ban4jp | 0:685224d2f66d | 98 | #define MAADR3 (0x02|0x60|0x80) |
ban4jp | 0:685224d2f66d | 99 | #define MAADR2 (0x03|0x60|0x80) |
ban4jp | 0:685224d2f66d | 100 | #define MAADR5 (0x04|0x60|0x80) |
ban4jp | 0:685224d2f66d | 101 | #define MAADR4 (0x05|0x60|0x80) |
ban4jp | 0:685224d2f66d | 102 | #define EBSTSD (0x06|0x60) |
ban4jp | 0:685224d2f66d | 103 | #define EBSTCON (0x07|0x60) |
ban4jp | 0:685224d2f66d | 104 | #define EBSTCSL (0x08|0x60) |
ban4jp | 0:685224d2f66d | 105 | #define EBSTCSH (0x09|0x60) |
ban4jp | 0:685224d2f66d | 106 | #define MISTAT (0x0A|0x60|0x80) |
ban4jp | 0:685224d2f66d | 107 | #define EREVID (0x12|0x60) |
ban4jp | 0:685224d2f66d | 108 | #define ECOCON (0x15|0x60) |
ban4jp | 0:685224d2f66d | 109 | #define EFLOCON (0x17|0x60) |
ban4jp | 0:685224d2f66d | 110 | #define EPAUSL (0x18|0x60) |
ban4jp | 0:685224d2f66d | 111 | #define EPAUSH (0x19|0x60) |
ban4jp | 0:685224d2f66d | 112 | // PHY registers |
ban4jp | 0:685224d2f66d | 113 | #define PHCON1 0x00 |
ban4jp | 0:685224d2f66d | 114 | #define PHSTAT1 0x01 |
ban4jp | 0:685224d2f66d | 115 | #define PHHID1 0x02 |
ban4jp | 0:685224d2f66d | 116 | #define PHHID2 0x03 |
ban4jp | 0:685224d2f66d | 117 | #define PHCON2 0x10 |
ban4jp | 0:685224d2f66d | 118 | #define PHSTAT2 0x11 |
ban4jp | 0:685224d2f66d | 119 | #define PHIE 0x12 |
ban4jp | 0:685224d2f66d | 120 | #define PHIR 0x13 |
ban4jp | 0:685224d2f66d | 121 | #define PHLCON 0x14 |
ban4jp | 0:685224d2f66d | 122 | |
ban4jp | 0:685224d2f66d | 123 | // ENC28J60 EIE Register Bit Definitions |
ban4jp | 0:685224d2f66d | 124 | #define EIE_INTIE 0x80 |
ban4jp | 0:685224d2f66d | 125 | #define EIE_PKTIE 0x40 |
ban4jp | 0:685224d2f66d | 126 | #define EIE_DMAIE 0x20 |
ban4jp | 0:685224d2f66d | 127 | #define EIE_LINKIE 0x10 |
ban4jp | 0:685224d2f66d | 128 | #define EIE_TXIE 0x08 |
ban4jp | 0:685224d2f66d | 129 | #define EIE_WOLIE 0x04 |
ban4jp | 0:685224d2f66d | 130 | #define EIE_TXERIE 0x02 |
ban4jp | 0:685224d2f66d | 131 | #define EIE_RXERIE 0x01 |
ban4jp | 0:685224d2f66d | 132 | // ENC28J60 EIR Register Bit Definitions |
ban4jp | 0:685224d2f66d | 133 | #define EIR_PKTIF 0x40 |
ban4jp | 0:685224d2f66d | 134 | #define EIR_DMAIF 0x20 |
ban4jp | 0:685224d2f66d | 135 | #define EIR_LINKIF 0x10 |
ban4jp | 0:685224d2f66d | 136 | #define EIR_TXIF 0x08 |
ban4jp | 0:685224d2f66d | 137 | #define EIR_WOLIF 0x04 |
ban4jp | 0:685224d2f66d | 138 | #define EIR_TXERIF 0x02 |
ban4jp | 0:685224d2f66d | 139 | #define EIR_RXERIF 0x01 |
ban4jp | 0:685224d2f66d | 140 | // ENC28J60 ESTAT Register Bit Definitions |
ban4jp | 0:685224d2f66d | 141 | #define ESTAT_INT 0x80 |
ban4jp | 0:685224d2f66d | 142 | #define ESTAT_LATECOL 0x10 |
ban4jp | 0:685224d2f66d | 143 | #define ESTAT_RXBUSY 0x04 |
ban4jp | 0:685224d2f66d | 144 | #define ESTAT_TXABRT 0x02 |
ban4jp | 0:685224d2f66d | 145 | #define ESTAT_CLKRDY 0x01 |
ban4jp | 0:685224d2f66d | 146 | // ENC28J60 ECON2 Register Bit Definitions |
ban4jp | 0:685224d2f66d | 147 | #define ECON2_AUTOINC 0x80 |
ban4jp | 0:685224d2f66d | 148 | #define ECON2_PKTDEC 0x40 |
ban4jp | 0:685224d2f66d | 149 | #define ECON2_PWRSV 0x20 |
ban4jp | 0:685224d2f66d | 150 | #define ECON2_VRPS 0x08 |
ban4jp | 0:685224d2f66d | 151 | // ENC28J60 ECON1 Register Bit Definitions |
ban4jp | 0:685224d2f66d | 152 | #define ECON1_TXRST 0x80 |
ban4jp | 0:685224d2f66d | 153 | #define ECON1_RXRST 0x40 |
ban4jp | 0:685224d2f66d | 154 | #define ECON1_DMAST 0x20 |
ban4jp | 0:685224d2f66d | 155 | #define ECON1_CSUMEN 0x10 |
ban4jp | 0:685224d2f66d | 156 | #define ECON1_TXRTS 0x08 |
ban4jp | 0:685224d2f66d | 157 | #define ECON1_RXEN 0x04 |
ban4jp | 0:685224d2f66d | 158 | #define ECON1_BSEL1 0x02 |
ban4jp | 0:685224d2f66d | 159 | #define ECON1_BSEL0 0x01 |
ban4jp | 0:685224d2f66d | 160 | // ENC28J60 MACON1 Register Bit Definitions |
ban4jp | 0:685224d2f66d | 161 | #define MACON1_LOOPBK 0x10 |
ban4jp | 0:685224d2f66d | 162 | #define MACON1_TXPAUS 0x08 |
ban4jp | 0:685224d2f66d | 163 | #define MACON1_RXPAUS 0x04 |
ban4jp | 0:685224d2f66d | 164 | #define MACON1_PASSALL 0x02 |
ban4jp | 0:685224d2f66d | 165 | #define MACON1_MARXEN 0x01 |
ban4jp | 0:685224d2f66d | 166 | // ENC28J60 MACON2 Register Bit Definitions |
ban4jp | 0:685224d2f66d | 167 | #define MACON2_MARST 0x80 |
ban4jp | 0:685224d2f66d | 168 | #define MACON2_RNDRST 0x40 |
ban4jp | 0:685224d2f66d | 169 | #define MACON2_MARXRST 0x08 |
ban4jp | 0:685224d2f66d | 170 | #define MACON2_RFUNRST 0x04 |
ban4jp | 0:685224d2f66d | 171 | #define MACON2_MATXRST 0x02 |
ban4jp | 0:685224d2f66d | 172 | #define MACON2_TFUNRST 0x01 |
ban4jp | 0:685224d2f66d | 173 | // ENC28J60 MACON3 Register Bit Definitions |
ban4jp | 0:685224d2f66d | 174 | #define MACON3_PADCFG2 0x80 |
ban4jp | 0:685224d2f66d | 175 | #define MACON3_PADCFG1 0x40 |
ban4jp | 0:685224d2f66d | 176 | #define MACON3_PADCFG0 0x20 |
ban4jp | 0:685224d2f66d | 177 | #define MACON3_TXCRCEN 0x10 |
ban4jp | 0:685224d2f66d | 178 | #define MACON3_PHDRLEN 0x08 |
ban4jp | 0:685224d2f66d | 179 | #define MACON3_HFRMLEN 0x04 |
ban4jp | 0:685224d2f66d | 180 | #define MACON3_FRMLNEN 0x02 |
ban4jp | 0:685224d2f66d | 181 | #define MACON3_FULDPX 0x01 |
ban4jp | 0:685224d2f66d | 182 | // ENC28J60 MICMD Register Bit Definitions |
ban4jp | 0:685224d2f66d | 183 | #define MICMD_MIISCAN 0x02 |
ban4jp | 0:685224d2f66d | 184 | #define MICMD_MIIRD 0x01 |
ban4jp | 0:685224d2f66d | 185 | // ENC28J60 MISTAT Register Bit Definitions |
ban4jp | 0:685224d2f66d | 186 | #define MISTAT_NVALID 0x04 |
ban4jp | 0:685224d2f66d | 187 | #define MISTAT_SCAN 0x02 |
ban4jp | 0:685224d2f66d | 188 | #define MISTAT_BUSY 0x01 |
ban4jp | 0:685224d2f66d | 189 | // ENC28J60 PHY PHCON1 Register Bit Definitions |
ban4jp | 0:685224d2f66d | 190 | #define PHCON1_PRST 0x8000 |
ban4jp | 0:685224d2f66d | 191 | #define PHCON1_PLOOPBK 0x4000 |
ban4jp | 0:685224d2f66d | 192 | #define PHCON1_PPWRSV 0x0800 |
ban4jp | 0:685224d2f66d | 193 | #define PHCON1_PDPXMD 0x0100 |
ban4jp | 0:685224d2f66d | 194 | // ENC28J60 PHY PHSTAT1 Register Bit Definitions |
ban4jp | 0:685224d2f66d | 195 | #define PHSTAT1_PFDPX 0x1000 |
ban4jp | 0:685224d2f66d | 196 | #define PHSTAT1_PHDPX 0x0800 |
ban4jp | 0:685224d2f66d | 197 | #define PHSTAT1_LLSTAT 0x0004 |
ban4jp | 0:685224d2f66d | 198 | #define PHSTAT1_JBSTAT 0x0002 |
ban4jp | 0:685224d2f66d | 199 | // ENC28J60 PHY PHCON2 Register Bit Definitions |
ban4jp | 0:685224d2f66d | 200 | #define PHCON2_FRCLINK 0x4000 |
ban4jp | 0:685224d2f66d | 201 | #define PHCON2_TXDIS 0x2000 |
ban4jp | 0:685224d2f66d | 202 | #define PHCON2_JABBER 0x0400 |
ban4jp | 0:685224d2f66d | 203 | #define PHCON2_HDLDIS 0x0100 |
ban4jp | 0:685224d2f66d | 204 | |
ban4jp | 0:685224d2f66d | 205 | // ENC28J60 Packet Control Byte Bit Definitions |
ban4jp | 0:685224d2f66d | 206 | #define PKTCTRL_PHUGEEN 0x08 |
ban4jp | 0:685224d2f66d | 207 | #define PKTCTRL_PPADEN 0x04 |
ban4jp | 0:685224d2f66d | 208 | #define PKTCTRL_PCRCEN 0x02 |
ban4jp | 0:685224d2f66d | 209 | #define PKTCTRL_POVERRIDE 0x01 |
ban4jp | 0:685224d2f66d | 210 | |
ban4jp | 0:685224d2f66d | 211 | // SPI operation codes |
ban4jp | 0:685224d2f66d | 212 | #define ENC28J60_READ_CTRL_REG 0x00 |
ban4jp | 0:685224d2f66d | 213 | #define ENC28J60_READ_BUF_MEM 0x3A |
ban4jp | 0:685224d2f66d | 214 | #define ENC28J60_WRITE_CTRL_REG 0x40 |
ban4jp | 0:685224d2f66d | 215 | #define ENC28J60_WRITE_BUF_MEM 0x7A |
ban4jp | 0:685224d2f66d | 216 | #define ENC28J60_BIT_FIELD_SET 0x80 |
ban4jp | 0:685224d2f66d | 217 | #define ENC28J60_BIT_FIELD_CLR 0xA0 |
ban4jp | 0:685224d2f66d | 218 | #define ENC28J60_SOFT_RESET 0xFF |
ban4jp | 0:685224d2f66d | 219 | |
ban4jp | 0:685224d2f66d | 220 | |
ban4jp | 0:685224d2f66d | 221 | // buffer boundaries applied to internal 8K ram |
ban4jp | 0:685224d2f66d | 222 | // entire available packet buffer space is allocated |
ban4jp | 0:685224d2f66d | 223 | //#define TXSTART_INIT 0x0000 // start TX buffer at 0 |
ban4jp | 0:685224d2f66d | 224 | //#define RXSTART_INIT 0x0600 // give TX buffer space for one full ethernet frame (~1500 bytes) |
ban4jp | 0:685224d2f66d | 225 | //#define RXSTOP_INIT 0x1FFF // receive buffer gets the rest |
ban4jp | 0:685224d2f66d | 226 | #define TXSTART_INIT 0x1A00 // start TX buffer at 0 |
ban4jp | 0:685224d2f66d | 227 | #define RXSTART_INIT 0x0000 // give TX buffer space for one full ethernet frame (~1500 bytes) |
ban4jp | 0:685224d2f66d | 228 | #define RXSTOP_INIT 0x19FF // receive buffer gets the rest |
ban4jp | 0:685224d2f66d | 229 | |
ban4jp | 0:685224d2f66d | 230 | #define MAX_FRAMELEN 1518 // maximum ethernet frame length |
ban4jp | 0:685224d2f66d | 231 | |
ban4jp | 0:685224d2f66d | 232 | // Ethernet constants |
ban4jp | 0:685224d2f66d | 233 | #define ETHERNET_MIN_PACKET_LENGTH 0x3C |
ban4jp | 0:685224d2f66d | 234 | //#define ETHERNET_HEADER_LENGTH 0x0E |
ban4jp | 0:685224d2f66d | 235 | |
ban4jp | 0:685224d2f66d | 236 | #define ENC28J60_CONTROL_PORT PORTB |
ban4jp | 0:685224d2f66d | 237 | #define ENC28J60_CONTROL_DDR DDRB |
ban4jp | 0:685224d2f66d | 238 | #define ENC28J60_CONTROL_CS 0 |
ban4jp | 0:685224d2f66d | 239 | |
ban4jp | 0:685224d2f66d | 240 | class ENC28J60 { |
ban4jp | 0:685224d2f66d | 241 | public: |
ban4jp | 0:685224d2f66d | 242 | |
ban4jp | 0:685224d2f66d | 243 | ENC28J60(SPI* _spi, PinName _cs, PinName _int); |
ban4jp | 0:685224d2f66d | 244 | |
ban4jp | 0:685224d2f66d | 245 | protected: |
ban4jp | 0:685224d2f66d | 246 | |
ban4jp | 0:685224d2f66d | 247 | //! do a ENC28J60 read operation |
ban4jp | 0:685224d2f66d | 248 | u8 readOp(u8 op, u8 address); |
ban4jp | 0:685224d2f66d | 249 | //! do a ENC28J60 write operation |
ban4jp | 0:685224d2f66d | 250 | void writeOp(u8 op, u8 address, u8 data); |
ban4jp | 0:685224d2f66d | 251 | //! read the packet buffer memory |
ban4jp | 0:685224d2f66d | 252 | void readBuffer(u16 len, u8* data); |
ban4jp | 0:685224d2f66d | 253 | //! write the packet buffer memory |
ban4jp | 0:685224d2f66d | 254 | void writeBuffer(u16 len, u8* data); |
ban4jp | 0:685224d2f66d | 255 | //! set the register bank for register at address |
ban4jp | 0:685224d2f66d | 256 | void setBank(u8 address); |
ban4jp | 0:685224d2f66d | 257 | //! read ax88796 register |
ban4jp | 0:685224d2f66d | 258 | u8 read(u8 address); |
ban4jp | 0:685224d2f66d | 259 | //! write ax88796 register |
ban4jp | 0:685224d2f66d | 260 | void write(u8 address, u8 data); |
ban4jp | 0:685224d2f66d | 261 | //! read a PHY register |
ban4jp | 0:685224d2f66d | 262 | u16 phyRead(u8 address); |
ban4jp | 0:685224d2f66d | 263 | //! write a PHY register |
ban4jp | 0:685224d2f66d | 264 | void phyWrite(u8 address, u16 data); |
ban4jp | 0:685224d2f66d | 265 | |
ban4jp | 0:685224d2f66d | 266 | public: |
ban4jp | 0:685224d2f66d | 267 | |
ban4jp | 0:685224d2f66d | 268 | //! initialize the ethernet interface for transmit/receive |
ban4jp | 0:685224d2f66d | 269 | void init(void); |
ban4jp | 0:685224d2f66d | 270 | |
ban4jp | 0:685224d2f66d | 271 | //! Packet transmit function. |
ban4jp | 0:685224d2f66d | 272 | /// Sends a packet on the network. It is assumed that the packet is headed by a valid ethernet header. |
ban4jp | 0:685224d2f66d | 273 | /// \param len Length of packet in bytes. |
ban4jp | 0:685224d2f66d | 274 | /// \param packet Pointer to packet data. |
ban4jp | 0:685224d2f66d | 275 | void packetSend(unsigned int len, unsigned char* packet); |
ban4jp | 0:685224d2f66d | 276 | void packetSend2(unsigned int len1, unsigned char* packet1, unsigned int len2, unsigned char* packet2); |
ban4jp | 0:685224d2f66d | 277 | |
ban4jp | 0:685224d2f66d | 278 | //! Packet receive function. |
ban4jp | 0:685224d2f66d | 279 | /// Gets a packet from the network receive buffer, if one is available. |
ban4jp | 0:685224d2f66d | 280 | /// The packet will by headed by an ethernet header. |
ban4jp | 0:685224d2f66d | 281 | /// \param maxlen The maximum acceptable length of a retrieved packet. |
ban4jp | 0:685224d2f66d | 282 | /// \param packet Pointer where packet data should be stored. |
ban4jp | 0:685224d2f66d | 283 | /// \return Packet length in bytes if a packet was retrieved, zero otherwise. |
ban4jp | 0:685224d2f66d | 284 | unsigned int packetReceive(unsigned int maxlen, unsigned char* packet); |
ban4jp | 0:685224d2f66d | 285 | |
ban4jp | 0:685224d2f66d | 286 | //! execute procedure for recovering from a receive overflow |
ban4jp | 0:685224d2f66d | 287 | /// this should be done when the receive memory fills up with packets |
ban4jp | 0:685224d2f66d | 288 | void receiveOverflowRecover(void); |
ban4jp | 0:685224d2f66d | 289 | |
ban4jp | 0:685224d2f66d | 290 | //! formatted print of important ENC28J60 registers |
ban4jp | 0:685224d2f66d | 291 | void regDump(void); |
ban4jp | 0:685224d2f66d | 292 | |
ban4jp | 0:685224d2f66d | 293 | protected: |
ban4jp | 0:685224d2f66d | 294 | SPI* spi; |
ban4jp | 0:685224d2f66d | 295 | DigitalOut cs_pin; |
ban4jp | 0:685224d2f66d | 296 | DigitalIn int_pin; |
ban4jp | 0:685224d2f66d | 297 | |
ban4jp | 0:685224d2f66d | 298 | }; |
ban4jp | 0:685224d2f66d | 299 | |
ban4jp | 0:685224d2f66d | 300 | #endif |