ban4jp - / Mbed 2 deprecated uIP-1-0_webserver

uIP 1.0 based webserver for LPC1114 + ENC28J60

Dependencies:   mbed TMP102

dev-enc28j60/enc28j60.cpp@1:b4d28172cacd, 2014-06-15 (annotated)

Committer:
ban4jp
Date:
Sun Jun 15 17:03:02 2014 +0000
Revision:
1:b4d28172cacd
Parent:
0:685224d2f66d
Child:
3:a2715e9c7737
update "httpd-fsdata.c".;   Convert contents, hex to char.;   Fixed Invalid html tags and contents data.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ban4jp 0:685224d2f66d 1 #include "mbed.h"
ban4jp 0:685224d2f66d 2
ban4jp 0:685224d2f66d 3 #include "enc28j60.h"
ban4jp 0:685224d2f66d 4 #include "uip-conf.h"
ban4jp 0:685224d2f66d 5
ban4jp 0:685224d2f66d 6 u8 Enc28j60Bank;
ban4jp 0:685224d2f66d 7 u16 NextPacketPtr;
ban4jp 0:685224d2f66d 8
ban4jp 0:685224d2f66d 9 ENC28J60::ENC28J60(SPI* _spi, PinName _cs, PinName _int):
ban4jp 0:685224d2f66d 10 cs_pin(_cs), int_pin(_int)
ban4jp 0:685224d2f66d 11 {
ban4jp 0:685224d2f66d 12 this->spi = _spi;
ban4jp 0:685224d2f66d 13
ban4jp 0:685224d2f66d 14 this->spi->format(8,0);
ban4jp 0:685224d2f66d 15 this->spi->frequency(8000000);
ban4jp 0:685224d2f66d 16
ban4jp 0:685224d2f66d 17 cs_pin = 1;
ban4jp 0:685224d2f66d 18 }
ban4jp 0:685224d2f66d 19
ban4jp 0:685224d2f66d 20 u8 ENC28J60::readOp(u8 op, u8 address)
ban4jp 0:685224d2f66d 21 {
ban4jp 0:685224d2f66d 22 u8 data;
ban4jp 0:685224d2f66d 23
ban4jp 0:685224d2f66d 24 // assert CS
ban4jp 0:685224d2f66d 25 cs_pin = 0;
ban4jp 0:685224d2f66d 26
ban4jp 0:685224d2f66d 27 // issue read command
ban4jp 0:685224d2f66d 28 spi->write(op | (address & ADDR_MASK));
ban4jp 0:685224d2f66d 29 // read data
ban4jp 0:685224d2f66d 30 data = spi->write(0x00);
ban4jp 0:685224d2f66d 31 // do dummy read if needed
ban4jp 0:685224d2f66d 32 if(address & 0x80)
ban4jp 0:685224d2f66d 33 {
ban4jp 0:685224d2f66d 34 data = spi->write(0x00);
ban4jp 0:685224d2f66d 35 }
ban4jp 0:685224d2f66d 36
ban4jp 0:685224d2f66d 37 // release CS
ban4jp 0:685224d2f66d 38 cs_pin = 1;
ban4jp 0:685224d2f66d 39
ban4jp 0:685224d2f66d 40 return data;
ban4jp 0:685224d2f66d 41 }
ban4jp 0:685224d2f66d 42
ban4jp 0:685224d2f66d 43 void ENC28J60::writeOp(u8 op, u8 address, u8 data)
ban4jp 0:685224d2f66d 44 {
ban4jp 0:685224d2f66d 45 // assert CS
ban4jp 0:685224d2f66d 46 cs_pin = 0;
ban4jp 0:685224d2f66d 47
ban4jp 0:685224d2f66d 48 // issue write command
ban4jp 0:685224d2f66d 49 spi->write(op | (address & ADDR_MASK));
ban4jp 0:685224d2f66d 50 // write data
ban4jp 0:685224d2f66d 51 spi->write(data);
ban4jp 0:685224d2f66d 52
ban4jp 0:685224d2f66d 53 // release CS
ban4jp 0:685224d2f66d 54 cs_pin = 1;
ban4jp 0:685224d2f66d 55 }
ban4jp 0:685224d2f66d 56
ban4jp 0:685224d2f66d 57 void ENC28J60::readBuffer(u16 len, u8* data)
ban4jp 0:685224d2f66d 58 {
ban4jp 0:685224d2f66d 59 // assert CS
ban4jp 0:685224d2f66d 60 cs_pin = 0;
ban4jp 0:685224d2f66d 61
ban4jp 0:685224d2f66d 62 // issue read command
ban4jp 0:685224d2f66d 63 spi->write(ENC28J60_READ_BUF_MEM);
ban4jp 0:685224d2f66d 64 while(len--)
ban4jp 0:685224d2f66d 65 {
ban4jp 0:685224d2f66d 66 // read data
ban4jp 0:685224d2f66d 67 *data++ = spi->write(0x00);
ban4jp 0:685224d2f66d 68 }
ban4jp 0:685224d2f66d 69
ban4jp 0:685224d2f66d 70 // release CS
ban4jp 0:685224d2f66d 71 cs_pin = 1;
ban4jp 0:685224d2f66d 72 }
ban4jp 0:685224d2f66d 73
ban4jp 0:685224d2f66d 74 void ENC28J60::writeBuffer(u16 len, u8* data)
ban4jp 0:685224d2f66d 75 {
ban4jp 0:685224d2f66d 76 // assert CS
ban4jp 0:685224d2f66d 77 cs_pin = 0;
ban4jp 0:685224d2f66d 78
ban4jp 0:685224d2f66d 79 // issue write command
ban4jp 0:685224d2f66d 80 spi->write(ENC28J60_WRITE_BUF_MEM);
ban4jp 0:685224d2f66d 81 while(len--)
ban4jp 0:685224d2f66d 82 {
ban4jp 0:685224d2f66d 83 // write data
ban4jp 0:685224d2f66d 84 spi->write(*data++);
ban4jp 0:685224d2f66d 85 }
ban4jp 0:685224d2f66d 86
ban4jp 0:685224d2f66d 87 // release CS
ban4jp 0:685224d2f66d 88 cs_pin = 1;
ban4jp 0:685224d2f66d 89 }
ban4jp 0:685224d2f66d 90
ban4jp 0:685224d2f66d 91 void ENC28J60::setBank(u8 address)
ban4jp 0:685224d2f66d 92 {
ban4jp 0:685224d2f66d 93 // set the bank (if needed)
ban4jp 0:685224d2f66d 94 if((address & BANK_MASK) != Enc28j60Bank)
ban4jp 0:685224d2f66d 95 {
ban4jp 0:685224d2f66d 96 // set the bank
ban4jp 0:685224d2f66d 97 this->writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1|ECON1_BSEL0));
ban4jp 0:685224d2f66d 98 this->writeOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK)>>5);
ban4jp 0:685224d2f66d 99 Enc28j60Bank = (address & BANK_MASK);
ban4jp 0:685224d2f66d 100 }
ban4jp 0:685224d2f66d 101 }
ban4jp 0:685224d2f66d 102
ban4jp 0:685224d2f66d 103 u8 ENC28J60::read(u8 address)
ban4jp 0:685224d2f66d 104 {
ban4jp 0:685224d2f66d 105 // set the bank
ban4jp 0:685224d2f66d 106 this->setBank(address);
ban4jp 0:685224d2f66d 107 // do the read
ban4jp 0:685224d2f66d 108 return this->readOp(ENC28J60_READ_CTRL_REG, address);
ban4jp 0:685224d2f66d 109 }
ban4jp 0:685224d2f66d 110
ban4jp 0:685224d2f66d 111 void ENC28J60::write(u8 address, u8 data)
ban4jp 0:685224d2f66d 112 {
ban4jp 0:685224d2f66d 113 // set the bank
ban4jp 0:685224d2f66d 114 this->setBank(address);
ban4jp 0:685224d2f66d 115 // do the write
ban4jp 0:685224d2f66d 116 this->writeOp(ENC28J60_WRITE_CTRL_REG, address, data);
ban4jp 0:685224d2f66d 117 }
ban4jp 0:685224d2f66d 118
ban4jp 0:685224d2f66d 119 u16 ENC28J60::phyRead(u8 address)
ban4jp 0:685224d2f66d 120 {
ban4jp 0:685224d2f66d 121 u16 data;
ban4jp 0:685224d2f66d 122
ban4jp 0:685224d2f66d 123 // Set the right address and start the register read operation
ban4jp 0:685224d2f66d 124 this->write(MIREGADR, address);
ban4jp 0:685224d2f66d 125 this->write(MICMD, MICMD_MIIRD);
ban4jp 0:685224d2f66d 126
ban4jp 0:685224d2f66d 127 // wait until the PHY read completes
ban4jp 0:685224d2f66d 128 while(this->read(MISTAT) & MISTAT_BUSY);
ban4jp 0:685224d2f66d 129
ban4jp 0:685224d2f66d 130 // quit reading
ban4jp 0:685224d2f66d 131 this->write(MICMD, 0x00);
ban4jp 0:685224d2f66d 132
ban4jp 0:685224d2f66d 133 // get data value
ban4jp 0:685224d2f66d 134 data = this->read(MIRDL);
ban4jp 0:685224d2f66d 135 data |= this->read(MIRDH);
ban4jp 0:685224d2f66d 136 // return the data
ban4jp 0:685224d2f66d 137 return data;
ban4jp 0:685224d2f66d 138 }
ban4jp 0:685224d2f66d 139
ban4jp 0:685224d2f66d 140 void ENC28J60::phyWrite(u8 address, u16 data)
ban4jp 0:685224d2f66d 141 {
ban4jp 0:685224d2f66d 142 // set the PHY register address
ban4jp 0:685224d2f66d 143 this->write(MIREGADR, address);
ban4jp 0:685224d2f66d 144
ban4jp 0:685224d2f66d 145 // write the PHY data
ban4jp 0:685224d2f66d 146 this->write(MIWRL, data);
ban4jp 0:685224d2f66d 147 this->write(MIWRH, data>>8);
ban4jp 0:685224d2f66d 148
ban4jp 0:685224d2f66d 149 // wait until the PHY write completes
ban4jp 0:685224d2f66d 150 while(this->read(MISTAT) & MISTAT_BUSY);
ban4jp 0:685224d2f66d 151 }
ban4jp 0:685224d2f66d 152
ban4jp 0:685224d2f66d 153 void ENC28J60::init(void)
ban4jp 0:685224d2f66d 154 {
ban4jp 0:685224d2f66d 155 cs_pin = 1; //Disable CS
ban4jp 0:685224d2f66d 156
ban4jp 0:685224d2f66d 157 // perform system reset
ban4jp 0:685224d2f66d 158 this->writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
ban4jp 0:685224d2f66d 159 // check CLKRDY bit to see if reset is complete
ban4jp 0:685224d2f66d 160 wait_us(50);
ban4jp 0:685224d2f66d 161 while(!(this->read(ESTAT) & ESTAT_CLKRDY));
ban4jp 0:685224d2f66d 162
ban4jp 0:685224d2f66d 163 // do bank 0 stuff
ban4jp 0:685224d2f66d 164 // initialize receive buffer
ban4jp 0:685224d2f66d 165 // 16-bit transfers, must write low byte first
ban4jp 0:685224d2f66d 166 // set receive buffer start address
ban4jp 0:685224d2f66d 167 NextPacketPtr = RXSTART_INIT;
ban4jp 0:685224d2f66d 168 this->write(ERXSTL, RXSTART_INIT&0xFF);
ban4jp 0:685224d2f66d 169 this->write(ERXSTH, RXSTART_INIT>>8);
ban4jp 0:685224d2f66d 170 // set receive pointer address
ban4jp 0:685224d2f66d 171 this->write(ERXRDPTL, RXSTART_INIT&0xFF);
ban4jp 0:685224d2f66d 172 this->write(ERXRDPTH, RXSTART_INIT>>8);
ban4jp 0:685224d2f66d 173 // set receive buffer end
ban4jp 0:685224d2f66d 174 // ERXND defaults to 0x1FFF (end of ram)
ban4jp 0:685224d2f66d 175 this->write(ERXNDL, RXSTOP_INIT&0xFF);
ban4jp 0:685224d2f66d 176 this->write(ERXNDH, RXSTOP_INIT>>8);
ban4jp 0:685224d2f66d 177 // set transmit buffer start
ban4jp 0:685224d2f66d 178 // ETXST defaults to 0x0000 (beginnging of ram)
ban4jp 0:685224d2f66d 179 this->write(ETXSTL, TXSTART_INIT&0xFF);
ban4jp 0:685224d2f66d 180 this->write(ETXSTH, TXSTART_INIT>>8);
ban4jp 0:685224d2f66d 181
ban4jp 0:685224d2f66d 182 // do bank 2 stuff
ban4jp 0:685224d2f66d 183 // enable MAC receive
ban4jp 0:685224d2f66d 184 this->write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
ban4jp 0:685224d2f66d 185 // bring MAC out of reset
ban4jp 0:685224d2f66d 186 this->write(MACON2, 0x00);
ban4jp 0:685224d2f66d 187 // enable automatic padding and CRC operations
ban4jp 0:685224d2f66d 188 this->writeOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
ban4jp 0:685224d2f66d 189 // this->write(MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
ban4jp 0:685224d2f66d 190 // set inter-frame gap (non-back-to-back)
ban4jp 0:685224d2f66d 191 this->write(MAIPGL, 0x12);
ban4jp 0:685224d2f66d 192 this->write(MAIPGH, 0x0C);
ban4jp 0:685224d2f66d 193 // set inter-frame gap (back-to-back)
ban4jp 0:685224d2f66d 194 this->write(MABBIPG, 0x12);
ban4jp 0:685224d2f66d 195 // Set the maximum packet size which the controller will accept
ban4jp 0:685224d2f66d 196 this->write(MAMXFLL, MAX_FRAMELEN&0xFF);
ban4jp 0:685224d2f66d 197 this->write(MAMXFLH, MAX_FRAMELEN>>8);
ban4jp 0:685224d2f66d 198
ban4jp 0:685224d2f66d 199 // do bank 3 stuff
ban4jp 0:685224d2f66d 200 // write MAC address
ban4jp 0:685224d2f66d 201 // NOTE: MAC address in ENC28J60 is byte-backward
ban4jp 0:685224d2f66d 202 this->write(MAADR5, UIP_ETHADDR0);
ban4jp 0:685224d2f66d 203 this->write(MAADR4, UIP_ETHADDR1);
ban4jp 0:685224d2f66d 204 this->write(MAADR3, UIP_ETHADDR2);
ban4jp 0:685224d2f66d 205 this->write(MAADR2, UIP_ETHADDR3);
ban4jp 0:685224d2f66d 206 this->write(MAADR1, UIP_ETHADDR4);
ban4jp 0:685224d2f66d 207 this->write(MAADR0, UIP_ETHADDR5);
ban4jp 0:685224d2f66d 208
ban4jp 0:685224d2f66d 209 // no loopback of transmitted frames
ban4jp 0:685224d2f66d 210 this->phyWrite(PHCON2, PHCON2_HDLDIS);
ban4jp 0:685224d2f66d 211
ban4jp 0:685224d2f66d 212 // switch to bank 0
ban4jp 0:685224d2f66d 213 this->setBank(ECON1);
ban4jp 0:685224d2f66d 214 // enable interrutps
ban4jp 0:685224d2f66d 215 this->writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
ban4jp 0:685224d2f66d 216 // enable packet reception
ban4jp 0:685224d2f66d 217 this->writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
ban4jp 0:685224d2f66d 218 /*
ban4jp 0:685224d2f66d 219 this->phyWrite(PHLCON, 0x0AA2);
ban4jp 0:685224d2f66d 220
ban4jp 0:685224d2f66d 221 // setup duplex ----------------------
ban4jp 0:685224d2f66d 222
ban4jp 0:685224d2f66d 223 // Disable receive logic and abort any packets currently being transmitted
ban4jp 0:685224d2f66d 224 this->writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS|ECON1_RXEN);
ban4jp 0:685224d2f66d 225
ban4jp 0:685224d2f66d 226 {
ban4jp 0:685224d2f66d 227 u16 temp;
ban4jp 0:685224d2f66d 228 // Set the PHY to the proper duplex mode
ban4jp 0:685224d2f66d 229 temp = enc28j60PhyRead(PHCON1);
ban4jp 0:685224d2f66d 230 temp &= ~PHCON1_PDPXMD;
ban4jp 0:685224d2f66d 231 this->phyWrite(PHCON1, temp);
ban4jp 0:685224d2f66d 232 // Set the MAC to the proper duplex mode
ban4jp 0:685224d2f66d 233 temp = this->read(MACON3);
ban4jp 0:685224d2f66d 234 temp &= ~MACON3_FULDPX;
ban4jp 0:685224d2f66d 235 this->write(MACON3, temp);
ban4jp 0:685224d2f66d 236 }
ban4jp 0:685224d2f66d 237
ban4jp 0:685224d2f66d 238 // Set the back-to-back inter-packet gap time to IEEE specified
ban4jp 0:685224d2f66d 239 // requirements. The meaning of the MABBIPG value changes with the duplex
ban4jp 0:685224d2f66d 240 // state, so it must be updated in this function.
ban4jp 0:685224d2f66d 241 // In full duplex, 0x15 represents 9.6us; 0x12 is 9.6us in half duplex
ban4jp 0:685224d2f66d 242 //this->write(MABBIPG, DuplexState ? 0x15 : 0x12);
ban4jp 0:685224d2f66d 243
ban4jp 0:685224d2f66d 244 // Reenable receive logic
ban4jp 0:685224d2f66d 245 this->writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
ban4jp 0:685224d2f66d 246
ban4jp 0:685224d2f66d 247 // setup duplex ----------------------
ban4jp 0:685224d2f66d 248 */
ban4jp 0:685224d2f66d 249 }
ban4jp 0:685224d2f66d 250
ban4jp 0:685224d2f66d 251 void ENC28J60::packetSend(unsigned int len, unsigned char* packet)
ban4jp 0:685224d2f66d 252 {
ban4jp 0:685224d2f66d 253 //Errata: Transmit Logic reset
ban4jp 0:685224d2f66d 254 this->writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
ban4jp 0:685224d2f66d 255 this->writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
ban4jp 0:685224d2f66d 256
ban4jp 0:685224d2f66d 257 // Set the write pointer to start of transmit buffer area
ban4jp 0:685224d2f66d 258 this->write(EWRPTL, TXSTART_INIT);
ban4jp 0:685224d2f66d 259 this->write(EWRPTH, TXSTART_INIT>>8);
ban4jp 0:685224d2f66d 260 // Set the TXND pointer to correspond to the packet size given
ban4jp 0:685224d2f66d 261 this->write(ETXNDL, (TXSTART_INIT+len));
ban4jp 0:685224d2f66d 262 this->write(ETXNDH, (TXSTART_INIT+len)>>8);
ban4jp 0:685224d2f66d 263
ban4jp 0:685224d2f66d 264 // write per-packet control byte
ban4jp 0:685224d2f66d 265 this->writeOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
ban4jp 0:685224d2f66d 266
ban4jp 0:685224d2f66d 267 // copy the packet into the transmit buffer
ban4jp 0:685224d2f66d 268 this->writeBuffer(len, packet);
ban4jp 0:685224d2f66d 269
ban4jp 0:685224d2f66d 270 // send the contents of the transmit buffer onto the network
ban4jp 0:685224d2f66d 271 this->writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
ban4jp 0:685224d2f66d 272 }
ban4jp 0:685224d2f66d 273
ban4jp 0:685224d2f66d 274 void ENC28J60::packetSend2(unsigned int len1, unsigned char* packet1, unsigned int len2, unsigned char* packet2)
ban4jp 0:685224d2f66d 275 {
ban4jp 0:685224d2f66d 276 //Errata: Transmit Logic reset
ban4jp 0:685224d2f66d 277 this->writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
ban4jp 0:685224d2f66d 278 this->writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
ban4jp 0:685224d2f66d 279
ban4jp 0:685224d2f66d 280 // Set the write pointer to start of transmit buffer area
ban4jp 0:685224d2f66d 281 this->write(EWRPTL, TXSTART_INIT);
ban4jp 0:685224d2f66d 282 this->write(EWRPTH, TXSTART_INIT>>8);
ban4jp 0:685224d2f66d 283 // Set the TXND pointer to correspond to the packet size given
ban4jp 0:685224d2f66d 284 this->write(ETXNDL, (TXSTART_INIT+len1+len2));
ban4jp 0:685224d2f66d 285 this->write(ETXNDH, (TXSTART_INIT+len1+len2)>>8);
ban4jp 0:685224d2f66d 286
ban4jp 0:685224d2f66d 287 // write per-packet control byte
ban4jp 0:685224d2f66d 288 this->writeOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
ban4jp 0:685224d2f66d 289
ban4jp 0:685224d2f66d 290 // copy the packet into the transmit buffer
ban4jp 0:685224d2f66d 291 this->writeBuffer(len1, packet1);
ban4jp 0:685224d2f66d 292 if(len2>0) this->writeBuffer(len2, packet2);
ban4jp 0:685224d2f66d 293
ban4jp 0:685224d2f66d 294 // send the contents of the transmit buffer onto the network
ban4jp 0:685224d2f66d 295 this->writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
ban4jp 0:685224d2f66d 296 }
ban4jp 0:685224d2f66d 297
ban4jp 0:685224d2f66d 298 unsigned int ENC28J60::packetReceive(unsigned int maxlen, unsigned char* packet)
ban4jp 0:685224d2f66d 299 {
ban4jp 0:685224d2f66d 300 u16 rxstat;
ban4jp 0:685224d2f66d 301 u16 len;
ban4jp 0:685224d2f66d 302
ban4jp 0:685224d2f66d 303 // check if a packet has been received and buffered
ban4jp 0:685224d2f66d 304 if( !(this->read(EIR) & EIR_PKTIF) )
ban4jp 0:685224d2f66d 305 return 0;
ban4jp 0:685224d2f66d 306
ban4jp 0:685224d2f66d 307 // Make absolutely certain that any previous packet was discarded
ban4jp 0:685224d2f66d 308 //if( WasDiscarded == FALSE)
ban4jp 0:685224d2f66d 309 // MACDiscardRx();
ban4jp 0:685224d2f66d 310
ban4jp 0:685224d2f66d 311 // Set the read pointer to the start of the received packet
ban4jp 0:685224d2f66d 312 this->write(ERDPTL, (NextPacketPtr));
ban4jp 0:685224d2f66d 313 this->write(ERDPTH, (NextPacketPtr)>>8);
ban4jp 0:685224d2f66d 314 // read the next packet pointer
ban4jp 0:685224d2f66d 315 NextPacketPtr = this->readOp(ENC28J60_READ_BUF_MEM, 0);
ban4jp 0:685224d2f66d 316 NextPacketPtr |= this->readOp(ENC28J60_READ_BUF_MEM, 0)<<8;
ban4jp 0:685224d2f66d 317 // read the packet length
ban4jp 0:685224d2f66d 318 len = this->readOp(ENC28J60_READ_BUF_MEM, 0);
ban4jp 0:685224d2f66d 319 len |= this->readOp(ENC28J60_READ_BUF_MEM, 0)<<8;
ban4jp 0:685224d2f66d 320 // read the receive status
ban4jp 0:685224d2f66d 321 rxstat = this->readOp(ENC28J60_READ_BUF_MEM, 0);
ban4jp 0:685224d2f66d 322 rxstat |= this->readOp(ENC28J60_READ_BUF_MEM, 0)<<8;
ban4jp 0:685224d2f66d 323
ban4jp 0:685224d2f66d 324 // limit retrieve length
ban4jp 0:685224d2f66d 325 // (we reduce the MAC-reported length by 4 to remove the CRC)
ban4jp 0:685224d2f66d 326 if(len>maxlen){
ban4jp 0:685224d2f66d 327 len=maxlen;
ban4jp 0:685224d2f66d 328 }
ban4jp 0:685224d2f66d 329
ban4jp 0:685224d2f66d 330 // copy the packet from the receive buffer
ban4jp 0:685224d2f66d 331 this->readBuffer(len, packet);
ban4jp 0:685224d2f66d 332
ban4jp 0:685224d2f66d 333 // Move the RX read pointer to the start of the next received packet
ban4jp 0:685224d2f66d 334 // This frees the memory we just read out
ban4jp 0:685224d2f66d 335 this->write(ERXRDPTL, (NextPacketPtr));
ban4jp 0:685224d2f66d 336 this->write(ERXRDPTH, (NextPacketPtr)>>8);
ban4jp 0:685224d2f66d 337
ban4jp 0:685224d2f66d 338 // decrement the packet counter indicate we are done with this packet
ban4jp 0:685224d2f66d 339 this->writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
ban4jp 0:685224d2f66d 340
ban4jp 0:685224d2f66d 341 return len;
ban4jp 0:685224d2f66d 342 }
ban4jp 0:685224d2f66d 343
ban4jp 0:685224d2f66d 344 void ENC28J60::receiveOverflowRecover(void)
ban4jp 0:685224d2f66d 345 {
ban4jp 0:685224d2f66d 346 // receive buffer overflow handling procedure
ban4jp 0:685224d2f66d 347
ban4jp 0:685224d2f66d 348 // recovery completed
ban4jp 0:685224d2f66d 349 }
ban4jp 0:685224d2f66d 350
ban4jp 0:685224d2f66d 351 void ENC28J60::regDump(void)
ban4jp 0:685224d2f66d 352 {
ban4jp 1:b4d28172cacd 353 printf("RevID: 0x%x\n", this->read(EREVID));
ban4jp 0:685224d2f66d 354
ban4jp 0:685224d2f66d 355 printf("Cntrl:\n");
ban4jp 0:685224d2f66d 356 printf("ECON1=%x ",this->read(ECON1));
ban4jp 0:685224d2f66d 357 printf("ECON2=%x ",this->read(ECON2));
ban4jp 0:685224d2f66d 358 printf("ESTAT=%x ",this->read(ESTAT));
ban4jp 0:685224d2f66d 359 printf("EIR=%x\n",this->read(EIR));
ban4jp 0:685224d2f66d 360 printf("EIE=%x\n",this->read(EIE));
ban4jp 0:685224d2f66d 361
ban4jp 0:685224d2f66d 362 printf("MAC:\n");
ban4jp 0:685224d2f66d 363 printf("MACON1=%x ",this->read(MACON1));
ban4jp 0:685224d2f66d 364 printf("MACON2=%x ",this->read(MACON2));
ban4jp 0:685224d2f66d 365 printf("MACON3=%x ",this->read(MACON3));
ban4jp 0:685224d2f66d 366 printf("MACON4=%x\n",this->read(MACON4));
ban4jp 0:685224d2f66d 367 printf("MAD=%x%x\n",
ban4jp 0:685224d2f66d 368 this->read(MAADR5)*0x1000000+this->read(MAADR4)*0x10000+this->read(MAADR3)*0x100+this->read(MAADR2),
ban4jp 0:685224d2f66d 369 this->read(MAADR1)*0x1000000+this->read(MAADR0)*0x10000+0xffff);
ban4jp 0:685224d2f66d 370
ban4jp 0:685224d2f66d 371 printf("Rx:\n");
ban4jp 0:685224d2f66d 372 printf("ERXST=%x ",this->read(ERXSTH)*0x100+this->read(ERXSTL));
ban4jp 0:685224d2f66d 373 printf("ERXND=%x ",this->read(ERXNDH)*0x100+this->read(ERXNDL));
ban4jp 0:685224d2f66d 374 printf("ERXWRPT=%x ",this->read(ERXWRPTH)*0x100+this->read(ERXWRPTL));
ban4jp 0:685224d2f66d 375 printf("ERXRDPT=%x\n",this->read(ERXRDPTH)*0x100+this->read(ERXRDPTL));
ban4jp 0:685224d2f66d 376 printf("ERXFCON=%x ",this->read(ERXFCON));
ban4jp 0:685224d2f66d 377 printf("EPKTCNT=%x ",this->read(EPKTCNT));
ban4jp 0:685224d2f66d 378 printf("MAMXFL=%x ",this->read(MAMXFLH)*0x100+this->read(MAMXFLL));
ban4jp 0:685224d2f66d 379
ban4jp 0:685224d2f66d 380 printf("Tx:\n");
ban4jp 0:685224d2f66d 381 printf("ETXST=%x ",this->read(ETXSTH)*0x100+this->read(ETXSTL));
ban4jp 0:685224d2f66d 382 printf("ETXND=%x ",this->read(ETXNDH)*0x100+this->read(ETXNDL));
ban4jp 0:685224d2f66d 383 printf("MACLCON1=%x ",this->read(MACLCON1));
ban4jp 0:685224d2f66d 384 printf("MACLCON2=%x\n",this->read(MACLCON2));
ban4jp 0:685224d2f66d 385 printf("MAPHSUP=%x\n",this->read(MAPHSUP));
ban4jp 0:685224d2f66d 386 }