Diff: WIZ820io/WIZ820io.h

Revision:

9:615198a7b82b

Parent:

7:93e358253dd8

--- a/WIZ820io/WIZ820io.h	Sun Dec 15 12:29:47 2013 +0000
+++ b/WIZ820io/WIZ820io.h	Mon Dec 23 13:51:35 2013 +0000
@@ -45,6 +45,14 @@
     
 };
 
+enum Interrupt {
+    INT_CON     = 0x01,
+    INT_DISCON  = 0x02,
+    INT_RECV    = 0x04,
+    INT_TIMEOUT = 0x08,
+    INT_SEND_OK = 0x10,
+};
+
 enum Status {
     SOCK_CLOSED      = 0x00,
     SOCK_INIT        = 0x13,
@@ -64,16 +72,19 @@
 #define SIPR      0x000f
 #define PHYSTATUS 0x0035
 // socket
-#define Sn_MR     0x0000
-#define Sn_CR     0x0001
-#define Sn_SR     0x0003
-#define Sn_PORT   0x0004
-#define Sn_DIPR   0x000c
-#define Sn_DPORT  0x0010
-#define Sn_TX_FSR 0x0020
-#define Sn_TX_WR  0x0024
-#define Sn_RX_RSR 0x0026
-#define Sn_RX_RD  0x0028
+#define Sn_MR         0x0000
+#define Sn_CR         0x0001
+#define Sn_IR         0x0002
+#define Sn_SR         0x0003
+#define Sn_PORT       0x0004
+#define Sn_DIPR       0x000c
+#define Sn_DPORT      0x0010
+#define Sn_RXBUF_SIZE 0x001e
+#define Sn_TXBUF_SIZE 0x001f
+#define Sn_TX_FSR     0x0020
+#define Sn_TX_WR      0x0024
+#define Sn_RX_RSR     0x0026
+#define Sn_RX_RD      0x0028
 
 class WIZ820io {
 public: