DSP program for the Surfboard hardware (PCB to be open sourced) http://www.avbotz.com/ourauv/electrical/signal-processing/

Dependencies:   MODDMA SimpleIOMacros mbed-dsp mbed

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Show/hide line numbers MODDMA_cache.cpp Source File

MODDMA_cache.cpp

00001 #include "MODDMA_cache.h"
00002 
00003 // Exists so the IRQ handler can access MODDMA object.
00004 MODDMA_Cache* moddma_p;
00005 
00006 // Setup the DMA controller and then cache some values. they will be used in Reset().
00007 // does not work; these values do not change. we aren't caching the right ones.
00008 
00009 MODDMA_Cache::MODDMA_Cache()
00010 {
00011     moddma_p = this;
00012     init();
00013 }
00014 
00015 // A copy of Kirkham's setup function. This caches most values as they are set. 
00016 uint32_t MODDMA_Cache::Setup(MODDMA_Config* config)
00017 {
00018     LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( config->channelNum() );
00019     
00020     setups[config->channelNum() & 0x7] = config;
00021     
00022     // Reset the Interrupt status
00023     LPC_GPDMA->DMACIntTCClear = DMACIntTCClear = IntTCClear_Ch( config->channelNum() );
00024     LPC_GPDMA->DMACIntErrClr  = DMACIntErrClr  = IntErrClr_Ch ( config->channelNum() );
00025 
00026     // Clear DMA configure
00027     pChannel->DMACCControl = 0x00;
00028     pChannel->DMACCConfig  = 0x00;
00029 
00030     // Assign Linker List Item value 
00031     pChannel->DMACCLLI = DMACCLLI = config->dmaLLI();
00032 
00033     // Set value to Channel Control Registers 
00034     switch (config->transferType()) {
00035     
00036         // Memory to memory
00037         case m2m:
00038             // Assign physical source and destination address
00039             pChannel->DMACCSrcAddr  = config->srcMemAddr();
00040             pChannel->DMACCDestAddr = config->dstMemAddr();
00041             pChannel->DMACCControl
00042                 = CxControl_TransferSize(config->transferSize()) 
00043                 | CxControl_SBSize(_32) 
00044                 | CxControl_DBSize(_32) 
00045                 | CxControl_SWidth(config->transferWidth()) 
00046                 | CxControl_DWidth(config->transferWidth()) 
00047                 | CxControl_SI() 
00048                 | CxControl_DI() 
00049                 | CxControl_I();
00050             break;
00051         
00052         // Memory to peripheral
00053         case m2p:
00054             // Assign physical source
00055             pChannel->DMACCSrcAddr = DMACCSrcAddr = config->srcMemAddr();
00056             // Assign peripheral destination address
00057             pChannel->DMACCDestAddr = DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
00058             pChannel->DMACCControl = DMACCControl
00059                 = CxControl_TransferSize((uint32_t)config->transferSize()) 
00060                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00061                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00062                 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) 
00063                 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) 
00064                 | CxControl_SI() 
00065                 | CxControl_I();
00066             break;
00067             
00068         // Peripheral to memory
00069         case p2m:
00070             // Assign peripheral source address
00071             pChannel->DMACCSrcAddr = DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
00072             // Assign memory destination address
00073             pChannel->DMACCDestAddr = DMACCDestAddr = config->dstMemAddr();
00074             pChannel->DMACCControl = DMACCControl
00075                 = CxControl_TransferSize((uint32_t)config->transferSize()) 
00076                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00077                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00078                 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) 
00079                 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) 
00080                 | CxControl_DI() 
00081                 | CxControl_I();
00082             break;
00083             
00084         // Peripheral to peripheral
00085         case p2p:
00086             // Assign peripheral source address
00087             pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
00088             // Assign peripheral destination address
00089             pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
00090             pChannel->DMACCControl
00091                 = CxControl_TransferSize((uint32_t)config->transferSize()) 
00092                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00093                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00094                 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) 
00095                 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) 
00096                 | CxControl_I();
00097             break;
00098             
00099         // GPIO to memory
00100         case g2m:
00101             // Assign GPIO source address
00102             pChannel->DMACCSrcAddr = config->srcMemAddr();
00103             // Assign memory destination address
00104             pChannel->DMACCDestAddr = config->dstMemAddr();
00105             pChannel->DMACCControl
00106                 = CxControl_TransferSize((uint32_t)config->transferSize()) 
00107                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00108                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00109                 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) 
00110                 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) 
00111                 | CxControl_DI() 
00112                 | CxControl_I();
00113             break;
00114             
00115         // Memory to GPIO
00116         case m2g:
00117             // Assign physical source
00118             pChannel->DMACCSrcAddr = config->srcMemAddr();
00119             // Assign peripheral destination address
00120             pChannel->DMACCDestAddr = config->dstMemAddr();
00121             pChannel->DMACCControl
00122                 = CxControl_TransferSize((uint32_t)config->transferSize()) 
00123                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00124                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00125                 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) 
00126                 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) 
00127                 | CxControl_SI() 
00128                 | CxControl_I();
00129             break;
00130             
00131         // Do not support any more transfer type, return ERROR
00132         default:
00133             return 0;
00134     }
00135 
00136      // Re-Configure DMA Request Select for source peripheral 
00137     if (config->srcConn() > 15) {
00138         DMAREQSEL = LPC_SC->DMAREQSEL |= (1 << (config->srcConn() - 16));
00139     } 
00140     else {
00141         DMAREQSEL = LPC_SC->DMAREQSEL &= ~(1 << (config->srcConn() - 8));
00142     }
00143 
00144     // Re-Configure DMA Request Select for destination peripheral
00145     if (config->dstConn() > 15) {
00146         DMAREQSEL = LPC_SC->DMAREQSEL |= (1 << (config->dstConn() - 16));
00147     } 
00148     else {
00149         DMAREQSEL = LPC_SC->DMAREQSEL &= ~(1 << (config->dstConn() - 8));
00150     }
00151 
00152     // Enable DMA channels, little endian 
00153     LPC_GPDMA->DMACConfig = _E;
00154     while (!(LPC_GPDMA->DMACConfig & _E));
00155 
00156     // Calculate absolute value for Connection number
00157     uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
00158     uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
00159 
00160     if (config->dmacSync()) {
00161         uint32_t tmp3 = config->dmacSync(); tmp3 = ((tmp3 > 15) ? (tmp3 - 8) : tmp3);
00162         LPC_GPDMA->DMACSync |= DMACSync = Sync_Src( tmp3 );
00163     }
00164     
00165     uint32_t tfer_type = (uint32_t)config->transferType();
00166     if (tfer_type == g2m || tfer_type == m2g) {
00167         tfer_type -= 2; // Adjust psuedo transferType to a real transferType.
00168     }
00169     
00170     // Configure DMA Channel, enable Error Counter and Terminate counter
00171     pChannel->DMACCConfig = DMACCConfig
00172         = CxConfig_IE() 
00173         | CxConfig_ITC() 
00174         | CxConfig_TransferType(tfer_type) 
00175         | CxConfig_SrcPeripheral(tmp1) 
00176         | CxConfig_DestPeripheral(tmp2);
00177 
00178     return pChannel->DMACCControl;
00179 }
00180 /*
00181 uint32_t MODDMA_Cache::Setup(MODDMA_Config* config)
00182 {
00183     moddma_p = this;
00184     
00185     //uint32_t ret = ((MODDMA*)this)->Setup(config);
00186     uint32_t ret = MODDMA::Setup(config);
00187     LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef*)Channel_p(config->channelNum());
00188     
00189     DMACCSrcAddr = pChannel->DMACCSrcAddr;
00190     DMACCDestAddr = pChannel->DMACCDestAddr;
00191     DMACCLLI = pChannel->DMACCLLI;
00192     //DMACCControl = pChannel->DMACCControl;
00193     
00194     switch (config->transferType())
00195     {
00196     case p2m:
00197         DMACCControl
00198             = CxControl_TransferSize((uint32_t)config->transferSize()) 
00199             | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00200             | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00201             | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) 
00202             | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) 
00203             | CxControl_DI() 
00204             | CxControl_I();
00205         break;
00206         
00207     case m2p:
00208         DMACCControl
00209             = CxControl_TransferSize((uint32_t)config->transferSize()) 
00210             | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00211             | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00212             | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) 
00213             | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) 
00214             | CxControl_SI() 
00215             | CxControl_I();
00216         break;
00217         
00218     default:
00219         return 5000; // oh no, your mbed blew up!
00220     }
00221     
00222     uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
00223     uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
00224 
00225     if (config->dmacSync()) {
00226         uint32_t tmp3 = config->dmacSync(); tmp3 = ((tmp3 > 15) ? (tmp3 - 8) : tmp3);
00227         LPC_GPDMA->DMACSync |= Sync_Src( tmp3 );
00228     }
00229     
00230     uint32_t tfer_type = (uint32_t)config->transferType();
00231     if (tfer_type == g2m || tfer_type == m2g) {
00232         tfer_type -= 2; // Adjust psuedo transferType to a real transferType.
00233     }
00234     
00235     // Configure DMA Channel, enable Error Counter and Terminate counter
00236         DMACCConfig = CxConfig_IE() 
00237         | CxConfig_ITC() 
00238         | CxConfig_TransferType(tfer_type) 
00239         | CxConfig_SrcPeripheral(tmp1) 
00240         | CxConfig_DestPeripheral(tmp2);
00241     
00242     DMACSync = LPC_GPDMA->DMACSync;
00243     
00244     return ret;
00245 }*/
00246 
00247 // This is modified from MODDMA::Setup(). Values that don't change between DMA operations will be cached to make it faster.
00248 // Everything commented or deleted here wasn't necessary to restart DMA.
00249 /*void MODDMA_Cache::Reset(MODDMA_Config* config)
00250 {
00251     LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef*)Channel_p(config->channelNum());
00252   
00253     //LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );
00254     //LPC_GPDMA->DMACIntErrClr  = IntErrClr_Ch ( config->channelNum() );
00255     
00256     //pChannel->DMACCLLI = DMACCLLI;
00257     pChannel->DMACCConfig = DMACCConfig;//
00258     
00259     //LPC_GPDMA->DMACSync = DMACSync;
00260     
00261     
00262     //setups[config->channelNum() & 0x7] = config;
00263     
00264     // Reset the Interrupt status
00265     LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );//
00266     LPC_GPDMA->DMACIntErrClr  = IntErrClr_Ch ( config->channelNum() );
00267     
00268     // BIGASS SWITCH WENT HERE
00269     pChannel->DMACCControl = DMACCControl;
00270     
00271     if (config->transferType() == p2m)
00272     {
00273         pChannel->DMACCSrcAddr = DMACCSrcAddr;
00274         pChannel->DMACCDestAddr = config->dstMemAddr();//
00275     }
00276 
00277     // Enable DMA channels, little endian 
00278     pChannel->DMACCConfig |= _E;
00279     return;
00280 }
00281 */
00282 
00283 /*
00284 void MODDMA_Cache::Reset(MODDMA_Config* config)
00285 {
00286     LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef*)Channel_p(config->channelNum());
00287   
00288     LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );
00289     LPC_GPDMA->DMACIntErrClr  = IntErrClr_Ch ( config->channelNum() );
00290     
00291     pChannel->DMACCLLI = DMACCLLI;
00292     pChannel->DMACCConfig = DMACCConfig;//
00293     
00294     LPC_GPDMA->DMACSync = DMACSync;
00295     
00296     
00297     setups[config->channelNum() & 0x7] = config;
00298     
00299     // Reset the Interrupt status
00300     LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );//
00301     LPC_GPDMA->DMACIntErrClr  = IntErrClr_Ch ( config->channelNum() );
00302     
00303     // BIGASS SWITCH WENT HERE
00304     pChannel->DMACCControl = DMACCControl;
00305     
00306     if (config->transferType() == p2m)
00307     {
00308         pChannel->DMACCSrcAddr = DMACCSrcAddr;
00309         pChannel->DMACCDestAddr = config->dstMemAddr();//
00310     }
00311 
00312     // Enable DMA channels, little endian 
00313     //pChannel->DMACCConfig |= _E;
00314     LPC_GPDMA->DMACConfig = _E;
00315     return;
00316 }*/
00317 /*
00318 These notes based on the LPC17xx family datasheet:
00319 
00320 DMACIntTCClear
00321 Interrupt terminal count clear
00322 clear interrupt request
00323 from <http://dreamrunner.org/wiki/public_html/Embedded%20System/kernel/DMA.html>
00324 "When the value in the current count register goes from 0 to -1, a terminal count (TC) signal is generated, which signifies the completion of the DMA transfer sequence."
00325 "DMA controllers require reprogramming when a DMA channel reaches TC."
00326 
00327 DMACIntErrClr
00328 Write 1 to request that some error flags be cleared
00329 
00330 DMACCControl*
00331 contain tons of information: transfer size, burst size, transfer width, etc
00332 Updated by DMA controller when the linked list is followed. So may not change in our application?
00333 
00334 DMACCConfig
00335 Contains Enable, src type, dest type, transfer type, error mask (to find/mask out the error bit), terminal count irq mask, active (whether there is data), and halt (to stop transfer)
00336 
00337 DMACCLLI
00338 address of next linked list item. If zero, this is the last item in the list and the transfer is complete after this list item is done. 
00339 
00340 DMACCSrcAddr*
00341 User sets the starting address. DMA updates w/ current read address as it goes.
00342 
00343 DMACCDestAddr*
00344 same idea as SrcAddr, but for the data destination
00345 
00346 DMAREQSEL
00347 Datasheet calls it "DMAReqSel" for some reason. 
00348 I'm not too clear on what this is. 
00349 Lets you pick whether you want UART or Timer DMA for DMA inputs 8-15.
00350 
00351 *Changes very quickly while the transfer in progress, so don't bother reading at that time
00352 */
00353 void MODDMA_Cache::Reset(MODDMA_Config *config)
00354 {
00355     /*Setup(config);
00356     return;*/
00357     LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( config->channelNum() );
00358     
00359     setups[config->channelNum() & 0x7] = config;
00360     
00361     // Reset the Interrupt status
00362     LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );
00363     LPC_GPDMA->DMACIntErrClr  = IntErrClr_Ch ( config->channelNum() );
00364 
00365     // Clear DMA configure
00366     pChannel->DMACCControl = 0x00;
00367     pChannel->DMACCConfig  = 0x00;
00368 
00369     // Assign Linker List Item value 
00370     pChannel->DMACCLLI = config->dmaLLI();
00371     
00372     // Set value to Channel Control Registers 
00373     switch (config->transferType()) {
00374     
00375         // Memory to memory
00376         case m2m:
00377             // Assign physical source and destination address
00378             pChannel->DMACCSrcAddr  = config->srcMemAddr();
00379             pChannel->DMACCDestAddr = config->dstMemAddr();
00380             pChannel->DMACCControl
00381                 = CxControl_TransferSize(config->transferSize()) 
00382                 | CxControl_SBSize(_32) 
00383                 | CxControl_DBSize(_32) 
00384                 | CxControl_SWidth(config->transferWidth()) 
00385                 | CxControl_DWidth(config->transferWidth()) 
00386                 | CxControl_SI() 
00387                 | CxControl_DI() 
00388                 | CxControl_I();
00389             break;
00390         
00391         // Memory to peripheral
00392         case m2p:
00393             // Assign physical source
00394             pChannel->DMACCSrcAddr = config->srcMemAddr();
00395             // Assign peripheral destination address
00396             pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
00397             pChannel->DMACCControl
00398                 = /*DMACCControl;*/CxControl_TransferSize((uint32_t)config->transferSize()) 
00399                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00400                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00401                 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) 
00402                 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) 
00403                 | CxControl_SI() 
00404                 | CxControl_I();
00405             break;
00406             
00407         // Peripheral to memory
00408         case p2m:
00409             // Assign peripheral source address
00410             pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
00411             // Assign memory destination address
00412             pChannel->DMACCDestAddr = config->dstMemAddr();
00413             pChannel->DMACCControl
00414                 = /*DMACCControl;*/CxControl_TransferSize((uint32_t)config->transferSize()) 
00415                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00416                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00417                 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) 
00418                 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) 
00419                 | CxControl_DI() 
00420                 | CxControl_I();
00421             break;
00422             
00423         // Peripheral to peripheral
00424         case p2p:
00425             // Assign peripheral source address
00426             pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());
00427             // Assign peripheral destination address
00428             pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());
00429             pChannel->DMACCControl
00430                 = CxControl_TransferSize((uint32_t)config->transferSize()) 
00431                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00432                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00433                 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) 
00434                 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) 
00435                 | CxControl_I();
00436             break;
00437             
00438         // GPIO to memory
00439         case g2m:
00440             // Assign GPIO source address
00441             pChannel->DMACCSrcAddr = config->srcMemAddr();
00442             // Assign memory destination address
00443             pChannel->DMACCDestAddr = config->dstMemAddr();
00444             pChannel->DMACCControl
00445                 = CxControl_TransferSize((uint32_t)config->transferSize()) 
00446                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00447                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) 
00448                 | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) 
00449                 | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) 
00450                 | CxControl_DI() 
00451                 | CxControl_I();
00452             break;
00453             
00454         // Memory to GPIO
00455         case m2g:
00456             // Assign physical source
00457             pChannel->DMACCSrcAddr = config->srcMemAddr();
00458             // Assign peripheral destination address
00459             pChannel->DMACCDestAddr = config->dstMemAddr();
00460             pChannel->DMACCControl
00461                 = CxControl_TransferSize((uint32_t)config->transferSize()) 
00462                 | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00463                 | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) 
00464                 | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) 
00465                 | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) 
00466                 | CxControl_SI() 
00467                 | CxControl_I();
00468             break;
00469             
00470         // Do not support any more transfer type, return ERROR
00471         default:
00472             return;// 0;
00473     }
00474 
00475      // Re-Configure DMA Request Select for source peripheral 
00476     if (config->srcConn() > 15) {
00477         LPC_SC->DMAREQSEL |= (1 << (config->srcConn() - 16));
00478     } 
00479     else {
00480         LPC_SC->DMAREQSEL &= ~(1 << (config->srcConn() - 8));
00481     }
00482 
00483     // Re-Configure DMA Request Select for destination peripheral
00484     if (config->dstConn() > 15) {
00485         LPC_SC->DMAREQSEL |= (1 << (config->dstConn() - 16));
00486     }
00487     else {
00488         LPC_SC->DMAREQSEL &= ~(1 << (config->dstConn() - 8));
00489     }
00490 
00491     // Enable DMA channels, little endian 
00492     LPC_GPDMA->DMACConfig = _E;
00493     pChannel->DMACCConfig |= _E; // copied from MODDMA::Enable()
00494     while (!(LPC_GPDMA->DMACConfig & _E));
00495 
00496     // Calculate absolute value for Connection number
00497     uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
00498     uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
00499 
00500     if (config->dmacSync()) {
00501         uint32_t tmp3 = config->dmacSync(); tmp3 = ((tmp3 > 15) ? (tmp3 - 8) : tmp3);
00502         LPC_GPDMA->DMACSync |= Sync_Src( tmp3 );
00503     }
00504     
00505     uint32_t tfer_type = (uint32_t)config->transferType();
00506     if (tfer_type == g2m || tfer_type == m2g) {
00507         tfer_type -= 2; // Adjust psuedo transferType to a real transferType.
00508     }
00509     
00510     // Configure DMA Channel, enable Error Counter and Terminate counter
00511     pChannel->DMACCConfig 
00512         = /*DMACCConfig;*/CxConfig_IE() 
00513         | CxConfig_ITC() 
00514         | CxConfig_TransferType(tfer_type) 
00515         | CxConfig_SrcPeripheral(tmp1) 
00516         | CxConfig_DestPeripheral(tmp2);
00517     
00518     return;// pChannel->DMACCControl;
00519 }
00520 
00521 extern "C" void MODDMA_Cache_IRQHandler()
00522 {
00523     p6_TOGGLE;
00524     
00525     /*if (moddma_p == (class MODDMA *)NULL) {
00526         if (oldDMAHandler) {
00527             ((MODDMA_FN)oldDMAHandler)();
00528             return;
00529         }
00530         else {
00531             error("Interrupt without instance");
00532         }
00533     }*/
00534     
00535     
00536     // SEE UNROLLED VERSION BELOW. They are equivalent.
00537     for (int channel_number = 0; channel_number < 2; channel_number++)
00538     {
00539         uint32_t channel_mask = (1UL << channel_number);
00540         
00541         // Since we only have one if statement inside anyway, I took this out
00542         //if (LPC_GPDMA->DMACIntStat & channel_mask)
00543         //{
00544             if (LPC_GPDMA->DMACIntTCStat & channel_mask)
00545             {
00546                 moddma_p->setups[channel_number]->isrIntTCStat->call();
00547                 LPC_GPDMA->DMACIntTCClear = channel_mask;
00548             }
00549             
00550             //if (LPC_GPDMA->DMACIntErrStat & channel_mask)
00551             //{
00552                 // removed for speed
00553                 //moddma_p->setups[channel_number]->isrIntErrStat->call();
00554                 LPC_GPDMA->DMACIntErrClr = channel_mask;
00555             //}
00556         //}
00557     }
00558     
00559     
00560     /*
00561     // This is some nasty code
00562     uint32_t channel_mask;
00563     channel_mask = (1UL << 0);
00564     
00565     // Since we only have one if statement inside anyway, I took this out
00566     //if (LPC_GPDMA->DMACIntStat & channel_mask)
00567     //{
00568         if (LPC_GPDMA->DMACIntTCStat & channel_mask)
00569         {
00570             moddma_p->setups[0]->isrIntTCStat->call();
00571             LPC_GPDMA->DMACIntTCClear = channel_mask;
00572         }
00573         
00574         //if (LPC_GPDMA->DMACIntErrStat & channel_mask)
00575         //{
00576             // removed for speed
00577             //moddma_p->setups[channel_number]->isrIntErrStat->call();
00578             LPC_GPDMA->DMACIntErrClr = channel_mask;
00579         //}
00580     //}
00581     channel_mask = (1UL << 1);
00582     // Since we only have one if statement inside anyway, I took this out
00583     //if (LPC_GPDMA->DMACIntStat & channel_mask)
00584     //{
00585         if (LPC_GPDMA->DMACIntTCStat & channel_mask)
00586         {
00587             moddma_p->setups[1]->isrIntTCStat->call();
00588             LPC_GPDMA->DMACIntTCClear = channel_mask;
00589         }
00590         
00591         //if (LPC_GPDMA->DMACIntErrStat & channel_mask)
00592         //{
00593             // removed for speed
00594             //moddma_p->setups[channel_number]->isrIntErrStat->call();
00595             LPC_GPDMA->DMACIntErrClr = channel_mask;
00596         //}
00597     //}*/
00598     
00599     p6_TOGGLE;
00600 }
00601 
00602 void MODDMA_Cache::init()
00603 {
00604     NVIC_SetVector(DMA_IRQn, (uint32_t)MODDMA_Cache_IRQHandler);
00605     NVIC_EnableIRQ(DMA_IRQn);
00606 }