HWsetup.cpp

00001 #include "mbed.h"
00002 #include "HWsetup.h"
00003 
00004 
00005 void Init_PWM(void){
00006     
00007     printf("\nStarting Hardware PWM\n\r");
00008     
00009     RCC->AHBENR |= RCC_AHBENR_GPIOAEN;                 // enable the clock to GPIOA
00010     RCC->AHBENR |= RCC_AHBENR_GPIOBEN;                 // enable the clock to GPIOA
00011     RCC->APB2ENR |= RCC_APB2ENR_TIM1EN;                // enable TIM1 clock
00012 
00013     
00014     //PWM Setup
00015     TIM1->CCMR1 |= 0x60;                             // Enable output compare 1 in PWM mode 1 
00016     TIM1->CCER |=  TIM_CCER_CC1E;                    // enable output 1
00017     TIM1->PSC = 0;                                   // set prescaler to 0
00018     TIM1->ARR = 1440;                               // set auto reload to 720- 100kHz but PWM is center aligned so zero
00019     TIM1->CR1 |= TIM_CR1_CMS_1;                      // Enable center-aligned PWM.
00020     TIM1->CR1 |= TIM_CR1_ARPE;                         // autoreload preload enable
00021     TIM1->CCMR1 |= TIM_CCMR1_OC1PE;                  // enable preloading of OC1
00022     RCC->CFGR3 |= RCC_CFGR3_TIM1SW;                    // bump tim1 up to 144MHz. 
00023     
00024     //hardware pin setup
00025     GPIOA->MODER   |= GPIO_MODER_MODER8_1 ;
00026     GPIOA->AFR[1]    |= 0x00000006;                    // PA8 to alternate function 6
00027     
00028     
00029     //interrupt generation
00030     NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);   //Enable TIM1 IRQ         
00031     TIM1->EGR |= TIM_EGR_UG;
00032     
00033     
00034     TIM1->CR1 |= TIM_CR1_CEN;   //go!
00035     
00036     }
00037 
00038 void Init_ADC(void){
00039         // ADC Setup
00040     RCC->AHBENR |= RCC_AHBENR_GPIOAEN; 
00041     RCC->AHBENR |= RCC_AHBENR_ADC12EN;                        // clock for ADC1 and 2 enable 
00042 
00043     ADC12_COMMON->CCR |= 0x20001;                 // Regular simultaneous mode plus injected conversions
00044     
00045     
00046     ADC1->SQR1 = 0x40;                            // use PA_0 as input, ADC1 in1
00047     GPIOA->MODER |= 0b0000000011;                 // PA_0  analog input
00048 
00049     ADC2->CR |= ADC_CR_ADEN;   //must be done before SMPR1
00050     ADC1->CR |= ADC_CR_ADEN;
00051     
00052     ADC1->CFGR |= ADC_CFGR_OVRMOD;
00053     
00054     }
00055     
00056 
00057 
00058 
00059 
00060 void Init_ADC_Tim_Sync() {
00061  
00062     ADC1->CFGR |= ADC_CFGR_EXTEN_0;
00063     ADC1->CFGR |= ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1;  // set to event 10, tim1 TRGO2
00064     TIM1->CR2 |= TIM_CR2_MMS2_1;
00065 
00066     ADC1->CR  |= ADC_CR_ADSTART; 
00067 }
00068 
00069 
00070 
00071 void Init_JADC() {
00072       //must be run before ADC sync, as it cannot be run before ADC is enabled
00073       //must be run after ADCen
00074     
00075     GPIOA->MODER |= 0b1100;                        // PA_1 is analog input
00076     ADC1->JSQR = ADC_JSQR_JSQ1_1;                  // on ADC1 channel 2
00077 
00078     //GPIOA->MODER |= 0b110000000000;                 // PA_5 is analog input 
00079     //ADC2->JSQR = ADC_JSQR_JSQ1_1;                   // on ADC2 channel 2
00080      
00081 }
00082 
00083 
00084 void BumpClock() {
00085     
00086     //bumpclock function
00087     RCC->CR |= RCC_CR_HSEON;             //turn on HSE 
00088     RCC->CR |= RCC_CR_HSEBYP;            //use external clock input, not oscillator, comment out for crystal
00089     
00090     while (((RCC->CR)>>17)&0x1 == 0) {}       //wait til HSE is stable with HSERDY bit
00091     
00092     RCC->CFGR &= ~RCC_CFGR_SW_0 & ~RCC_CFGR_SW_1;  //use HSI as system clock- flying blind!
00093     RCC->CR &= ~RCC_CR_PLLON;                            //turn off PLL
00094 
00095     while (((RCC->CR)>>25)&0x1) {}                 //wait til PLL is off
00096     
00097     RCC->CFGR |= RCC_CFGR_PLLSRC;                  // set PLL source to HSE
00098     RCC->CFGR2 &= ~RCC_CFGR2_PREDIV_0 & ~RCC_CFGR2_PREDIV_1 & ~RCC_CFGR2_PREDIV_2 & ~RCC_CFGR2_PREDIV_3;// deselect all
00099     
00100     RCC->CFGR &= ~RCC_CFGR_PLLMUL_0 & ~RCC_CFGR_PLLMUL_1 & ~RCC_CFGR_PLLMUL_2 & ~RCC_CFGR_PLLMUL_3;  // deselect all
00101     RCC->CFGR |= RCC_CFGR_PLLMUL_0 | RCC_CFGR_PLLMUL_1 | RCC_CFGR_PLLMUL_2;  // set PLL multiplier to 9
00102     
00103     
00104     RCC->CFGR |= RCC_CFGR_SW_1;                    //reselect PLL as system clock
00105     RCC->CR |= RCC_CR_PLLON;
00106     while ( ((RCC->CR)>>25)&0x1 == 0 ) {}          //wait while PLL is starting up
00107     
00108     // APB1 prescaler = 2, APB1 limited to 36MHz, APB2 operates at full speed
00109     // RCC_CFGR: MCO = 100, Sysclk out
00110     // RCC_CFGR: PLLMUL = x9, PLLXTPRE is zero
00111     //           PLLSRC = 1, 1: HSE/PREDIV selected as PLL input clock 
00112     //  SWS = 10, PLL is systme clock
00113     //  SW = 10
00114     // PRE1 = 100; set APB1 to 2
00115     
00116     // check out PREDIV in RCC_CFGR2
00117     //APB1 prescaler = 2 for 36MHz, APB2 prescaler = 1
00118 }
00119 
00120 
00121 void Init_All_HW(void){
00122     wait_ms(100);
00123     Init_ADC();
00124     wait_ms(10);
00125     Init_JADC();
00126     wait(0.1);         
00127     
00128     //Init_DAC();
00129     //wait_ms(10);
00130     
00131     Init_PWM();
00132     
00133 
00134     
00135     }