Austin Brown / Mbed 2 deprecated 2171_MicroLab_3

Make 2171 Great Again

Dependencies:   mbed

HWsetup/HWsetup.cpp@1:f1d2d02d724d, 2019-12-04 (annotated)

Committer:
austinbrown124
Date:
Wed Dec 04 02:36:34 2019 +0000
Revision:
1:f1d2d02d724d
Parent:
0:d229bc2fa375 
Commit 2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
austinbrown124 0:d229bc2fa375 1 #include "mbed.h"
austinbrown124 0:d229bc2fa375 2 #include "HWsetup.h"
austinbrown124 0:d229bc2fa375 3
austinbrown124 0:d229bc2fa375 4
austinbrown124 0:d229bc2fa375 5 void Init_PWM(void){
austinbrown124 0:d229bc2fa375 6
austinbrown124 0:d229bc2fa375 7 printf("\nStarting Hardware PWM\n\r");
austinbrown124 0:d229bc2fa375 8
austinbrown124 0:d229bc2fa375 9 RCC->AHBENR |= RCC_AHBENR_GPIOAEN; // enable the clock to GPIOA
austinbrown124 0:d229bc2fa375 10 RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // enable the clock to GPIOA
austinbrown124 0:d229bc2fa375 11 RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; // enable TIM1 clock
austinbrown124 0:d229bc2fa375 12
austinbrown124 0:d229bc2fa375 13
austinbrown124 0:d229bc2fa375 14 //PWM Setup
austinbrown124 0:d229bc2fa375 15 TIM1->CCMR1 |= 0x60; // Enable output compare 1 in PWM mode 1
austinbrown124 0:d229bc2fa375 16 TIM1->CCER |= TIM_CCER_CC1E; // enable output 1
austinbrown124 0:d229bc2fa375 17 TIM1->PSC = 0; // set prescaler to 0
austinbrown124 0:d229bc2fa375 18 TIM1->ARR = 1440; // set auto reload to 720- 100kHz but PWM is center aligned so zero
austinbrown124 0:d229bc2fa375 19 TIM1->CR1 |= TIM_CR1_CMS_1; // Enable center-aligned PWM.
austinbrown124 0:d229bc2fa375 20 TIM1->CR1 |= TIM_CR1_ARPE; // autoreload preload enable
austinbrown124 0:d229bc2fa375 21 TIM1->CCMR1 |= TIM_CCMR1_OC1PE; // enable preloading of OC1
austinbrown124 0:d229bc2fa375 22 RCC->CFGR3 |= RCC_CFGR3_TIM1SW; // bump tim1 up to 144MHz.
austinbrown124 0:d229bc2fa375 23
austinbrown124 0:d229bc2fa375 24 //hardware pin setup
austinbrown124 0:d229bc2fa375 25 GPIOA->MODER |= GPIO_MODER_MODER8_1 ;
austinbrown124 0:d229bc2fa375 26 GPIOA->AFR[1] |= 0x00000006; // PA8 to alternate function 6
austinbrown124 0:d229bc2fa375 27
austinbrown124 0:d229bc2fa375 28
austinbrown124 0:d229bc2fa375 29 //interrupt generation
austinbrown124 0:d229bc2fa375 30 NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn); //Enable TIM1 IRQ
austinbrown124 0:d229bc2fa375 31 TIM1->EGR |= TIM_EGR_UG;
austinbrown124 0:d229bc2fa375 32
austinbrown124 0:d229bc2fa375 33
austinbrown124 0:d229bc2fa375 34 TIM1->CR1 |= TIM_CR1_CEN; //go!
austinbrown124 0:d229bc2fa375 35
austinbrown124 0:d229bc2fa375 36 }
austinbrown124 0:d229bc2fa375 37
austinbrown124 0:d229bc2fa375 38 void Init_ADC(void){
austinbrown124 0:d229bc2fa375 39 // ADC Setup
austinbrown124 0:d229bc2fa375 40 RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
austinbrown124 0:d229bc2fa375 41 RCC->AHBENR |= RCC_AHBENR_ADC12EN; // clock for ADC1 and 2 enable
austinbrown124 0:d229bc2fa375 42
austinbrown124 0:d229bc2fa375 43 ADC12_COMMON->CCR |= 0x20001; // Regular simultaneous mode plus injected conversions
austinbrown124 0:d229bc2fa375 44
austinbrown124 0:d229bc2fa375 45
austinbrown124 0:d229bc2fa375 46 ADC1->SQR1 = 0x40; // use PA_0 as input, ADC1 in1
austinbrown124 0:d229bc2fa375 47 GPIOA->MODER |= 0b0000000011; // PA_0 analog input
austinbrown124 0:d229bc2fa375 48
austinbrown124 0:d229bc2fa375 49 ADC2->CR |= ADC_CR_ADEN; //must be done before SMPR1
austinbrown124 0:d229bc2fa375 50 ADC1->CR |= ADC_CR_ADEN;
austinbrown124 0:d229bc2fa375 51
austinbrown124 0:d229bc2fa375 52 ADC1->CFGR |= ADC_CFGR_OVRMOD;
austinbrown124 0:d229bc2fa375 53
austinbrown124 0:d229bc2fa375 54 }
austinbrown124 0:d229bc2fa375 55
austinbrown124 0:d229bc2fa375 56
austinbrown124 0:d229bc2fa375 57
austinbrown124 0:d229bc2fa375 58
austinbrown124 0:d229bc2fa375 59
austinbrown124 0:d229bc2fa375 60 void Init_ADC_Tim_Sync() {
austinbrown124 0:d229bc2fa375 61
austinbrown124 0:d229bc2fa375 62 ADC1->CFGR |= ADC_CFGR_EXTEN_0;
austinbrown124 0:d229bc2fa375 63 ADC1->CFGR |= ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1; // set to event 10, tim1 TRGO2
austinbrown124 0:d229bc2fa375 64 TIM1->CR2 |= TIM_CR2_MMS2_1;
austinbrown124 0:d229bc2fa375 65
austinbrown124 0:d229bc2fa375 66 ADC1->CR |= ADC_CR_ADSTART;
austinbrown124 0:d229bc2fa375 67 }
austinbrown124 0:d229bc2fa375 68
austinbrown124 0:d229bc2fa375 69
austinbrown124 0:d229bc2fa375 70
austinbrown124 0:d229bc2fa375 71 void Init_JADC() {
austinbrown124 0:d229bc2fa375 72 //must be run before ADC sync, as it cannot be run before ADC is enabled
austinbrown124 0:d229bc2fa375 73 //must be run after ADCen
austinbrown124 0:d229bc2fa375 74
austinbrown124 0:d229bc2fa375 75 GPIOA->MODER |= 0b1100; // PA_1 is analog input
austinbrown124 0:d229bc2fa375 76 ADC1->JSQR = ADC_JSQR_JSQ1_1; // on ADC1 channel 2
austinbrown124 0:d229bc2fa375 77
austinbrown124 0:d229bc2fa375 78 //GPIOA->MODER |= 0b110000000000; // PA_5 is analog input
austinbrown124 0:d229bc2fa375 79 //ADC2->JSQR = ADC_JSQR_JSQ1_1; // on ADC2 channel 2
austinbrown124 0:d229bc2fa375 80
austinbrown124 0:d229bc2fa375 81 }
austinbrown124 0:d229bc2fa375 82
austinbrown124 0:d229bc2fa375 83
austinbrown124 0:d229bc2fa375 84 void BumpClock() {
austinbrown124 0:d229bc2fa375 85
austinbrown124 0:d229bc2fa375 86 //bumpclock function
austinbrown124 0:d229bc2fa375 87 RCC->CR |= RCC_CR_HSEON; //turn on HSE
austinbrown124 0:d229bc2fa375 88 RCC->CR |= RCC_CR_HSEBYP; //use external clock input, not oscillator, comment out for crystal
austinbrown124 0:d229bc2fa375 89
austinbrown124 0:d229bc2fa375 90 while (((RCC->CR)>>17)&0x1 == 0) {} //wait til HSE is stable with HSERDY bit
austinbrown124 0:d229bc2fa375 91
austinbrown124 0:d229bc2fa375 92 RCC->CFGR &= ~RCC_CFGR_SW_0 & ~RCC_CFGR_SW_1; //use HSI as system clock- flying blind!
austinbrown124 0:d229bc2fa375 93 RCC->CR &= ~RCC_CR_PLLON; //turn off PLL
austinbrown124 0:d229bc2fa375 94
austinbrown124 0:d229bc2fa375 95 while (((RCC->CR)>>25)&0x1) {} //wait til PLL is off
austinbrown124 0:d229bc2fa375 96
austinbrown124 0:d229bc2fa375 97 RCC->CFGR |= RCC_CFGR_PLLSRC; // set PLL source to HSE
austinbrown124 0:d229bc2fa375 98 RCC->CFGR2 &= ~RCC_CFGR2_PREDIV_0 & ~RCC_CFGR2_PREDIV_1 & ~RCC_CFGR2_PREDIV_2 & ~RCC_CFGR2_PREDIV_3;// deselect all
austinbrown124 0:d229bc2fa375 99
austinbrown124 0:d229bc2fa375 100 RCC->CFGR &= ~RCC_CFGR_PLLMUL_0 & ~RCC_CFGR_PLLMUL_1 & ~RCC_CFGR_PLLMUL_2 & ~RCC_CFGR_PLLMUL_3; // deselect all
austinbrown124 0:d229bc2fa375 101 RCC->CFGR |= RCC_CFGR_PLLMUL_0 | RCC_CFGR_PLLMUL_1 | RCC_CFGR_PLLMUL_2; // set PLL multiplier to 9
austinbrown124 0:d229bc2fa375 102
austinbrown124 0:d229bc2fa375 103
austinbrown124 0:d229bc2fa375 104 RCC->CFGR |= RCC_CFGR_SW_1; //reselect PLL as system clock
austinbrown124 0:d229bc2fa375 105 RCC->CR |= RCC_CR_PLLON;
austinbrown124 0:d229bc2fa375 106 while ( ((RCC->CR)>>25)&0x1 == 0 ) {} //wait while PLL is starting up
austinbrown124 0:d229bc2fa375 107
austinbrown124 0:d229bc2fa375 108 // APB1 prescaler = 2, APB1 limited to 36MHz, APB2 operates at full speed
austinbrown124 0:d229bc2fa375 109 // RCC_CFGR: MCO = 100, Sysclk out
austinbrown124 0:d229bc2fa375 110 // RCC_CFGR: PLLMUL = x9, PLLXTPRE is zero
austinbrown124 0:d229bc2fa375 111 // PLLSRC = 1, 1: HSE/PREDIV selected as PLL input clock
austinbrown124 0:d229bc2fa375 112 // SWS = 10, PLL is systme clock
austinbrown124 0:d229bc2fa375 113 // SW = 10
austinbrown124 0:d229bc2fa375 114 // PRE1 = 100; set APB1 to 2
austinbrown124 0:d229bc2fa375 115
austinbrown124 0:d229bc2fa375 116 // check out PREDIV in RCC_CFGR2
austinbrown124 0:d229bc2fa375 117 //APB1 prescaler = 2 for 36MHz, APB2 prescaler = 1
austinbrown124 0:d229bc2fa375 118 }
austinbrown124 0:d229bc2fa375 119
austinbrown124 0:d229bc2fa375 120
austinbrown124 0:d229bc2fa375 121 void Init_All_HW(void){
austinbrown124 0:d229bc2fa375 122 wait_ms(100);
austinbrown124 0:d229bc2fa375 123 Init_ADC();
austinbrown124 0:d229bc2fa375 124 wait_ms(10);
austinbrown124 0:d229bc2fa375 125 Init_JADC();
austinbrown124 0:d229bc2fa375 126 wait(0.1);
austinbrown124 0:d229bc2fa375 127
austinbrown124 0:d229bc2fa375 128 //Init_DAC();
austinbrown124 0:d229bc2fa375 129 //wait_ms(10);
austinbrown124 0:d229bc2fa375 130
austinbrown124 0:d229bc2fa375 131 Init_PWM();
austinbrown124 0:d229bc2fa375 132
austinbrown124 0:d229bc2fa375 133
austinbrown124 0:d229bc2fa375 134
austinbrown124 0:d229bc2fa375 135 }