Aravind Vadali / mbed-src-RatRacerAV

Mbed Library with modified HSE_Startup timeout

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC13XX/pinmap.c@636:a11c0372f0ba, 2015-09-30 (annotated)

Committer:
mbed_official
Date:
Wed Sep 30 17:00:09 2015 +0100
Revision:
636:a11c0372f0ba
Parent:
285:31249416b6f9 
Synchronized with git revision d29c98dae61be0946ddf3a3c641c7726056f9452



Full URL: https://github.com/mbedmicro/mbed/commit/d29c98dae61be0946ddf3a3c641c7726056f9452/



Added support for SAMW25

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
mbed_official 227:7bd0639b8911 16 #include "mbed_assert.h"
emilmont 10:3bc89ef62ce7 17 #include "pinmap.h"
mbed_official 285:31249416b6f9 18 #include "mbed_error.h"
emilmont 10:3bc89ef62ce7 19
emilmont 10:3bc89ef62ce7 20 #define LPC_IOCON0_BASE (LPC_IOCON_BASE)
emilmont 10:3bc89ef62ce7 21 #define LPC_IOCON1_BASE (LPC_IOCON_BASE + 0x60)
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 void pin_function(PinName pin, int function) {
mbed_official 227:7bd0639b8911 24 MBED_ASSERT(pin != (PinName)NC);
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26 uint32_t pin_number = (uint32_t)pin;
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 __IO uint32_t *reg = (pin_number < 32) ?
emilmont 10:3bc89ef62ce7 29 (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
emilmont 10:3bc89ef62ce7 30 (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
emilmont 10:3bc89ef62ce7 31
emilmont 10:3bc89ef62ce7 32 // pin function bits: [2:0] -> 111 = (0x7)
emilmont 10:3bc89ef62ce7 33 *reg = (*reg & ~0x7) | (function & 0x7);
emilmont 10:3bc89ef62ce7 34 }
emilmont 10:3bc89ef62ce7 35
emilmont 10:3bc89ef62ce7 36 void pin_mode(PinName pin, PinMode mode) {
mbed_official 227:7bd0639b8911 37 MBED_ASSERT(pin != (PinName)NC);
emilmont 10:3bc89ef62ce7 38
emilmont 10:3bc89ef62ce7 39 uint32_t pin_number = (uint32_t)pin;
emilmont 10:3bc89ef62ce7 40 uint32_t drain = ((uint32_t) mode & (uint32_t) OpenDrain) >> 2;
emilmont 10:3bc89ef62ce7 41
emilmont 10:3bc89ef62ce7 42 __IO uint32_t *reg = (pin_number < 32) ?
emilmont 10:3bc89ef62ce7 43 (__IO uint32_t*)(LPC_IOCON0_BASE + 4 * pin_number) :
emilmont 10:3bc89ef62ce7 44 (__IO uint32_t*)(LPC_IOCON1_BASE + 4 * (pin_number - 32));
emilmont 10:3bc89ef62ce7 45 uint32_t tmp = *reg;
emilmont 10:3bc89ef62ce7 46
emilmont 10:3bc89ef62ce7 47 // pin mode bits: [4:3] -> 11000 = (0x3 << 3)
emilmont 10:3bc89ef62ce7 48 tmp &= ~(0x3 << 3);
emilmont 10:3bc89ef62ce7 49 tmp |= (mode & 0x3) << 3;
emilmont 10:3bc89ef62ce7 50
emilmont 10:3bc89ef62ce7 51 // drain
emilmont 10:3bc89ef62ce7 52 tmp &= ~(0x1 << 10);
emilmont 10:3bc89ef62ce7 53 tmp |= drain << 10;
emilmont 10:3bc89ef62ce7 54
emilmont 10:3bc89ef62ce7 55 *reg = tmp;
emilmont 10:3bc89ef62ce7 56 }