Aravind Vadali / mbed-src-RatRacerAV

Mbed Library with modified HSE_Startup timeout

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC81X/pinmap.c@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Parent:
vendor/NXP/LPC812/hal/pinmap.c@10:3bc89ef62ce7 
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 17 #include "error.h"
emilmont 10:3bc89ef62ce7 18
emilmont 10:3bc89ef62ce7 19 __IO uint32_t* IOCON_REGISTERS[18] = {
emilmont 10:3bc89ef62ce7 20 &LPC_IOCON->PIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 ,
emilmont 10:3bc89ef62ce7 21 &LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 ,
emilmont 10:3bc89ef62ce7 22 &LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 ,
emilmont 10:3bc89ef62ce7 23 &LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11,
emilmont 10:3bc89ef62ce7 24 &LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14,
emilmont 10:3bc89ef62ce7 25 &LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17,
emilmont 10:3bc89ef62ce7 26 };
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 void pin_function(PinName pin, int function) {
emilmont 10:3bc89ef62ce7 29
emilmont 10:3bc89ef62ce7 30 }
emilmont 10:3bc89ef62ce7 31
emilmont 10:3bc89ef62ce7 32 void pin_mode(PinName pin, PinMode mode) {
emilmont 10:3bc89ef62ce7 33 if (pin == (uint32_t)NC) { return; }
emilmont 10:3bc89ef62ce7 34
emilmont 10:3bc89ef62ce7 35 if ((pin == 10) || (pin == 11)) {
emilmont 10:3bc89ef62ce7 36 // True open-drain pins can be configured for different I2C-bus speeds
emilmont 10:3bc89ef62ce7 37 return;
emilmont 10:3bc89ef62ce7 38 }
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 __IO uint32_t *reg = IOCON_REGISTERS[pin];
emilmont 10:3bc89ef62ce7 41
emilmont 10:3bc89ef62ce7 42 if (mode == OpenDrain) {
emilmont 10:3bc89ef62ce7 43 *reg |= (1 << 10);
emilmont 10:3bc89ef62ce7 44 } else {
emilmont 10:3bc89ef62ce7 45 uint32_t tmp = *reg;
emilmont 10:3bc89ef62ce7 46 tmp &= ~(0x3 << 3);
emilmont 10:3bc89ef62ce7 47 tmp |= (mode & 0x3) << 3;
emilmont 10:3bc89ef62ce7 48 *reg = tmp;
emilmont 10:3bc89ef62ce7 49 }
emilmont 10:3bc89ef62ce7 50 }