Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc.c@1:ebce2ad32f95, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 03:07:12 2015 +0000
Revision:
1:ebce2ad32f95
Parent:
0:ba7650f404af 
Changed the RCC timeout value to 500 ms, so total code startup time before program starts running is ~1s. Hopefully no side-effects from lower startup timeouts

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /**
aravindsv 0:ba7650f404af 2 ******************************************************************************
aravindsv 0:ba7650f404af 3 * @file stm32f4xx_hal_rcc.c
aravindsv 0:ba7650f404af 4 * @author MCD Application Team
aravindsv 0:ba7650f404af 5 * @version V1.3.2
aravindsv 0:ba7650f404af 6 * @date 26-June-2015
aravindsv 0:ba7650f404af 7 * @brief RCC HAL module driver.
aravindsv 0:ba7650f404af 8 * This file provides firmware functions to manage the following
aravindsv 0:ba7650f404af 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
aravindsv 0:ba7650f404af 10 * + Initialization and de-initialization functions
aravindsv 0:ba7650f404af 11 * + Peripheral Control functions
aravindsv 0:ba7650f404af 12 *
aravindsv 0:ba7650f404af 13 @verbatim
aravindsv 0:ba7650f404af 14 ==============================================================================
aravindsv 0:ba7650f404af 15 ##### RCC specific features #####
aravindsv 0:ba7650f404af 16 ==============================================================================
aravindsv 0:ba7650f404af 17 [..]
aravindsv 0:ba7650f404af 18 After reset the device is running from Internal High Speed oscillator
aravindsv 0:ba7650f404af 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
aravindsv 0:ba7650f404af 20 and I-Cache are disabled, and all peripherals are off except internal
aravindsv 0:ba7650f404af 21 SRAM, Flash and JTAG.
aravindsv 0:ba7650f404af 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
aravindsv 0:ba7650f404af 23 all peripherals mapped on these busses are running at HSI speed.
aravindsv 0:ba7650f404af 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
aravindsv 0:ba7650f404af 25 (+) All GPIOs are in input floating state, except the JTAG pins which
aravindsv 0:ba7650f404af 26 are assigned to be used for debug purpose.
aravindsv 0:ba7650f404af 27
aravindsv 0:ba7650f404af 28 [..]
aravindsv 0:ba7650f404af 29 Once the device started from reset, the user application has to:
aravindsv 0:ba7650f404af 30 (+) Configure the clock source to be used to drive the System clock
aravindsv 0:ba7650f404af 31 (if the application needs higher frequency/performance)
aravindsv 0:ba7650f404af 32 (+) Configure the System clock frequency and Flash settings
aravindsv 0:ba7650f404af 33 (+) Configure the AHB and APB busses prescalers
aravindsv 0:ba7650f404af 34 (+) Enable the clock for the peripheral(s) to be used
aravindsv 0:ba7650f404af 35 (+) Configure the clock source(s) for peripherals which clocks are not
aravindsv 0:ba7650f404af 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
aravindsv 0:ba7650f404af 37
aravindsv 0:ba7650f404af 38 ##### RCC Limitations #####
aravindsv 0:ba7650f404af 39 ==============================================================================
aravindsv 0:ba7650f404af 40 [..]
aravindsv 0:ba7650f404af 41 A delay between an RCC peripheral clock enable and the effective peripheral
aravindsv 0:ba7650f404af 42 enabling should be taken into account in order to manage the peripheral read/write
aravindsv 0:ba7650f404af 43 from/to registers.
aravindsv 0:ba7650f404af 44 (+) This delay depends on the peripheral mapping.
aravindsv 0:ba7650f404af 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
aravindsv 0:ba7650f404af 46 after the clock enable bit is set on the hardware register
aravindsv 0:ba7650f404af 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
aravindsv 0:ba7650f404af 48 after the clock enable bit is set on the hardware register
aravindsv 0:ba7650f404af 49
aravindsv 0:ba7650f404af 50 [..]
aravindsv 0:ba7650f404af 51 Possible Workarounds:
aravindsv 0:ba7650f404af 52 (#) Enable the peripheral clock sometimes before the peripheral read/write
aravindsv 0:ba7650f404af 53 register is required.
aravindsv 0:ba7650f404af 54 (#) For AHB peripheral, insert two dummy read to the peripheral register.
aravindsv 0:ba7650f404af 55 (#) For APB peripheral, insert a dummy read to the peripheral register.
aravindsv 0:ba7650f404af 56
aravindsv 0:ba7650f404af 57 @endverbatim
aravindsv 0:ba7650f404af 58 ******************************************************************************
aravindsv 0:ba7650f404af 59 * @attention
aravindsv 0:ba7650f404af 60 *
aravindsv 0:ba7650f404af 61 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
aravindsv 0:ba7650f404af 62 *
aravindsv 0:ba7650f404af 63 * Redistribution and use in source and binary forms, with or without modification,
aravindsv 0:ba7650f404af 64 * are permitted provided that the following conditions are met:
aravindsv 0:ba7650f404af 65 * 1. Redistributions of source code must retain the above copyright notice,
aravindsv 0:ba7650f404af 66 * this list of conditions and the following disclaimer.
aravindsv 0:ba7650f404af 67 * 2. Redistributions in binary form must reproduce the above copyright notice,
aravindsv 0:ba7650f404af 68 * this list of conditions and the following disclaimer in the documentation
aravindsv 0:ba7650f404af 69 * and/or other materials provided with the distribution.
aravindsv 0:ba7650f404af 70 * 3. Neither the name of STMicroelectronics nor the names of its contributors
aravindsv 0:ba7650f404af 71 * may be used to endorse or promote products derived from this software
aravindsv 0:ba7650f404af 72 * without specific prior written permission.
aravindsv 0:ba7650f404af 73 *
aravindsv 0:ba7650f404af 74 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
aravindsv 0:ba7650f404af 75 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
aravindsv 0:ba7650f404af 76 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
aravindsv 0:ba7650f404af 77 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
aravindsv 0:ba7650f404af 78 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
aravindsv 0:ba7650f404af 79 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
aravindsv 0:ba7650f404af 80 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
aravindsv 0:ba7650f404af 81 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
aravindsv 0:ba7650f404af 82 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
aravindsv 0:ba7650f404af 83 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
aravindsv 0:ba7650f404af 84 *
aravindsv 0:ba7650f404af 85 ******************************************************************************
aravindsv 0:ba7650f404af 86 */
aravindsv 0:ba7650f404af 87
aravindsv 0:ba7650f404af 88 /* Includes ------------------------------------------------------------------*/
aravindsv 0:ba7650f404af 89 #include "stm32f4xx_hal.h"
aravindsv 0:ba7650f404af 90
aravindsv 0:ba7650f404af 91 /** @addtogroup STM32F4xx_HAL_Driver
aravindsv 0:ba7650f404af 92 * @{
aravindsv 0:ba7650f404af 93 */
aravindsv 0:ba7650f404af 94
aravindsv 0:ba7650f404af 95 /** @defgroup RCC RCC
aravindsv 0:ba7650f404af 96 * @brief RCC HAL module driver
aravindsv 0:ba7650f404af 97 * @{
aravindsv 0:ba7650f404af 98 */
aravindsv 0:ba7650f404af 99
aravindsv 0:ba7650f404af 100 #ifdef HAL_RCC_MODULE_ENABLED
aravindsv 0:ba7650f404af 101
aravindsv 0:ba7650f404af 102 /* Private typedef -----------------------------------------------------------*/
aravindsv 0:ba7650f404af 103 /* Private define ------------------------------------------------------------*/
aravindsv 0:ba7650f404af 104 /** @addtogroup RCC_Private_Constants
aravindsv 0:ba7650f404af 105 * @{
aravindsv 0:ba7650f404af 106 */
aravindsv 1:ebce2ad32f95 107 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)500) /* .5 s */
aravindsv 0:ba7650f404af 108
aravindsv 0:ba7650f404af 109 /* Private macro -------------------------------------------------------------*/
aravindsv 0:ba7650f404af 110 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
aravindsv 0:ba7650f404af 111 #define MCO1_GPIO_PORT GPIOA
aravindsv 0:ba7650f404af 112 #define MCO1_PIN GPIO_PIN_8
aravindsv 0:ba7650f404af 113
aravindsv 0:ba7650f404af 114 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
aravindsv 0:ba7650f404af 115 #define MCO2_GPIO_PORT GPIOC
aravindsv 0:ba7650f404af 116 #define MCO2_PIN GPIO_PIN_9
aravindsv 0:ba7650f404af 117 /**
aravindsv 0:ba7650f404af 118 * @}
aravindsv 0:ba7650f404af 119 */
aravindsv 0:ba7650f404af 120
aravindsv 0:ba7650f404af 121 /* Private variables ---------------------------------------------------------*/
aravindsv 0:ba7650f404af 122 /** @defgroup RCC_Private_Variables RCC Private Variables
aravindsv 0:ba7650f404af 123 * @{
aravindsv 0:ba7650f404af 124 */
aravindsv 0:ba7650f404af 125 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
aravindsv 0:ba7650f404af 126 /**
aravindsv 0:ba7650f404af 127 * @}
aravindsv 0:ba7650f404af 128 */
aravindsv 0:ba7650f404af 129
aravindsv 0:ba7650f404af 130 /* Private function prototypes -----------------------------------------------*/
aravindsv 0:ba7650f404af 131 /* Private functions ---------------------------------------------------------*/
aravindsv 0:ba7650f404af 132
aravindsv 0:ba7650f404af 133 /** @defgroup RCC_Exported_Functions RCC Exported Functions
aravindsv 0:ba7650f404af 134 * @{
aravindsv 0:ba7650f404af 135 */
aravindsv 0:ba7650f404af 136
aravindsv 0:ba7650f404af 137 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
aravindsv 0:ba7650f404af 138 * @brief Initialization and Configuration functions
aravindsv 0:ba7650f404af 139 *
aravindsv 0:ba7650f404af 140 @verbatim
aravindsv 0:ba7650f404af 141 ===============================================================================
aravindsv 0:ba7650f404af 142 ##### Initialization and de-initialization functions #####
aravindsv 0:ba7650f404af 143 ===============================================================================
aravindsv 0:ba7650f404af 144 [..]
aravindsv 0:ba7650f404af 145 This section provides functions allowing to configure the internal/external oscillators
aravindsv 0:ba7650f404af 146 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
aravindsv 0:ba7650f404af 147 and APB2).
aravindsv 0:ba7650f404af 148
aravindsv 0:ba7650f404af 149 [..] Internal/external clock and PLL configuration
aravindsv 0:ba7650f404af 150 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
aravindsv 0:ba7650f404af 151 the PLL as System clock source.
aravindsv 0:ba7650f404af 152
aravindsv 0:ba7650f404af 153 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
aravindsv 0:ba7650f404af 154 clock source.
aravindsv 0:ba7650f404af 155
aravindsv 0:ba7650f404af 156 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
aravindsv 0:ba7650f404af 157 through the PLL as System clock source. Can be used also as RTC clock source.
aravindsv 0:ba7650f404af 158
aravindsv 0:ba7650f404af 159 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
aravindsv 0:ba7650f404af 160
aravindsv 0:ba7650f404af 161 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
aravindsv 0:ba7650f404af 162 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
aravindsv 0:ba7650f404af 163 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
aravindsv 0:ba7650f404af 164 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
aravindsv 0:ba7650f404af 165
aravindsv 0:ba7650f404af 166 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
aravindsv 0:ba7650f404af 167 and if a HSE clock failure occurs(HSE used directly or through PLL as System
aravindsv 0:ba7650f404af 168 clock source), the System clocks automatically switched to HSI and an interrupt
aravindsv 0:ba7650f404af 169 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
aravindsv 0:ba7650f404af 170 (Non-Maskable Interrupt) exception vector.
aravindsv 0:ba7650f404af 171
aravindsv 0:ba7650f404af 172 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
aravindsv 0:ba7650f404af 173 clock (through a configurable prescaler) on PA8 pin.
aravindsv 0:ba7650f404af 174
aravindsv 0:ba7650f404af 175 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
aravindsv 0:ba7650f404af 176 clock (through a configurable prescaler) on PC9 pin.
aravindsv 0:ba7650f404af 177
aravindsv 0:ba7650f404af 178 [..] System, AHB and APB busses clocks configuration
aravindsv 0:ba7650f404af 179 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
aravindsv 0:ba7650f404af 180 HSE and PLL.
aravindsv 0:ba7650f404af 181 The AHB clock (HCLK) is derived from System clock through configurable
aravindsv 0:ba7650f404af 182 prescaler and used to clock the CPU, memory and peripherals mapped
aravindsv 0:ba7650f404af 183 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
aravindsv 0:ba7650f404af 184 from AHB clock through configurable prescalers and used to clock
aravindsv 0:ba7650f404af 185 the peripherals mapped on these busses. You can use
aravindsv 0:ba7650f404af 186 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
aravindsv 0:ba7650f404af 187
aravindsv 0:ba7650f404af 188 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
aravindsv 0:ba7650f404af 189 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
aravindsv 0:ba7650f404af 190 from an external clock mapped on the I2S_CKIN pin.
aravindsv 0:ba7650f404af 191 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
aravindsv 0:ba7650f404af 192 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
aravindsv 0:ba7650f404af 193 from an external clock mapped on the I2S_CKIN pin.
aravindsv 0:ba7650f404af 194 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
aravindsv 0:ba7650f404af 195 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
aravindsv 0:ba7650f404af 196 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
aravindsv 0:ba7650f404af 197 macros to configure this clock.
aravindsv 0:ba7650f404af 198 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
aravindsv 0:ba7650f404af 199 to work correctly, while the SDIO require a frequency equal or lower than
aravindsv 0:ba7650f404af 200 to 48. This clock is derived of the main PLL through PLLQ divider.
aravindsv 0:ba7650f404af 201 (+@) IWDG clock which is always the LSI clock.
aravindsv 0:ba7650f404af 202
aravindsv 0:ba7650f404af 203 (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
aravindsv 0:ba7650f404af 204 frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
aravindsv 0:ba7650f404af 205 Depending on the device voltage range, the maximum frequency should
aravindsv 0:ba7650f404af 206 be adapted accordingly (refer to the product datasheets for more details).
aravindsv 0:ba7650f404af 207
aravindsv 0:ba7650f404af 208 (#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
aravindsv 0:ba7650f404af 209 of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
aravindsv 0:ba7650f404af 210 Depending on the device voltage range, the maximum frequency should
aravindsv 0:ba7650f404af 211 be adapted accordingly (refer to the product datasheets for more details).
aravindsv 0:ba7650f404af 212
aravindsv 0:ba7650f404af 213 (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
aravindsv 0:ba7650f404af 214 PCLK2 84 MHz and PCLK1 42 MHz.
aravindsv 0:ba7650f404af 215 Depending on the device voltage range, the maximum frequency should
aravindsv 0:ba7650f404af 216 be adapted accordingly (refer to the product datasheets for more details).
aravindsv 0:ba7650f404af 217 @endverbatim
aravindsv 0:ba7650f404af 218 * @{
aravindsv 0:ba7650f404af 219 */
aravindsv 0:ba7650f404af 220
aravindsv 0:ba7650f404af 221 /**
aravindsv 0:ba7650f404af 222 * @brief Resets the RCC clock configuration to the default reset state.
aravindsv 0:ba7650f404af 223 * @note The default reset state of the clock configuration is given below:
aravindsv 0:ba7650f404af 224 * - HSI ON and used as system clock source
aravindsv 0:ba7650f404af 225 * - HSE, PLL and PLLI2S OFF
aravindsv 0:ba7650f404af 226 * - AHB, APB1 and APB2 prescaler set to 1.
aravindsv 0:ba7650f404af 227 * - CSS, MCO1 and MCO2 OFF
aravindsv 0:ba7650f404af 228 * - All interrupts disabled
aravindsv 0:ba7650f404af 229 * @note This function doesn't modify the configuration of the
aravindsv 0:ba7650f404af 230 * - Peripheral clocks
aravindsv 0:ba7650f404af 231 * - LSI, LSE and RTC clocks
aravindsv 0:ba7650f404af 232 * @retval None
aravindsv 0:ba7650f404af 233 */
aravindsv 0:ba7650f404af 234 void HAL_RCC_DeInit(void)
aravindsv 0:ba7650f404af 235 {
aravindsv 0:ba7650f404af 236 /* Set HSION bit */
aravindsv 0:ba7650f404af 237 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
aravindsv 0:ba7650f404af 238
aravindsv 0:ba7650f404af 239 /* Reset CFGR register */
aravindsv 0:ba7650f404af 240 CLEAR_REG(RCC->CFGR);
aravindsv 0:ba7650f404af 241
aravindsv 0:ba7650f404af 242 /* Reset HSEON, CSSON, PLLON, PLLI2S */
aravindsv 0:ba7650f404af 243 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
aravindsv 0:ba7650f404af 244
aravindsv 0:ba7650f404af 245 /* Reset PLLCFGR register */
aravindsv 0:ba7650f404af 246 CLEAR_REG(RCC->PLLCFGR);
aravindsv 0:ba7650f404af 247 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
aravindsv 0:ba7650f404af 248
aravindsv 0:ba7650f404af 249 /* Reset PLLI2SCFGR register */
aravindsv 0:ba7650f404af 250 CLEAR_REG(RCC->PLLI2SCFGR);
aravindsv 0:ba7650f404af 251 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
aravindsv 0:ba7650f404af 252
aravindsv 0:ba7650f404af 253 /* Reset HSEBYP bit */
aravindsv 0:ba7650f404af 254 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
aravindsv 0:ba7650f404af 255
aravindsv 0:ba7650f404af 256 /* Disable all interrupts */
aravindsv 0:ba7650f404af 257 CLEAR_REG(RCC->CIR);
aravindsv 0:ba7650f404af 258 }
aravindsv 0:ba7650f404af 259
aravindsv 0:ba7650f404af 260 /**
aravindsv 0:ba7650f404af 261 * @brief Initializes the RCC Oscillators according to the specified parameters in the
aravindsv 0:ba7650f404af 262 * RCC_OscInitTypeDef.
aravindsv 0:ba7650f404af 263 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
aravindsv 0:ba7650f404af 264 * contains the configuration information for the RCC Oscillators.
aravindsv 0:ba7650f404af 265 * @note The PLL is not disabled when used as system clock.
aravindsv 0:ba7650f404af 266 * @retval HAL status
aravindsv 0:ba7650f404af 267 */
aravindsv 0:ba7650f404af 268 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
aravindsv 0:ba7650f404af 269 {
aravindsv 0:ba7650f404af 270 uint32_t tickstart = 0;
aravindsv 0:ba7650f404af 271
aravindsv 0:ba7650f404af 272 /* Check the parameters */
aravindsv 0:ba7650f404af 273 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
aravindsv 0:ba7650f404af 274 /*------------------------------- HSE Configuration ------------------------*/
aravindsv 0:ba7650f404af 275 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
aravindsv 0:ba7650f404af 276 {
aravindsv 0:ba7650f404af 277 /* Check the parameters */
aravindsv 0:ba7650f404af 278 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
aravindsv 0:ba7650f404af 279 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
aravindsv 0:ba7650f404af 280 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
aravindsv 0:ba7650f404af 281 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
aravindsv 0:ba7650f404af 282 {
aravindsv 0:ba7650f404af 283 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
aravindsv 0:ba7650f404af 284 {
aravindsv 0:ba7650f404af 285 return HAL_ERROR;
aravindsv 0:ba7650f404af 286 }
aravindsv 0:ba7650f404af 287 }
aravindsv 0:ba7650f404af 288 else
aravindsv 0:ba7650f404af 289 {
aravindsv 0:ba7650f404af 290 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
aravindsv 0:ba7650f404af 291 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
aravindsv 0:ba7650f404af 292
aravindsv 0:ba7650f404af 293 /* Get Start Tick*/
aravindsv 0:ba7650f404af 294 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 295
aravindsv 0:ba7650f404af 296 /* Wait till HSE is disabled */
aravindsv 0:ba7650f404af 297 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
aravindsv 0:ba7650f404af 298 {
aravindsv 0:ba7650f404af 299 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 300 {
aravindsv 0:ba7650f404af 301 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 302 }
aravindsv 0:ba7650f404af 303 }
aravindsv 0:ba7650f404af 304
aravindsv 0:ba7650f404af 305 /* Set the new HSE configuration ---------------------------------------*/
aravindsv 0:ba7650f404af 306 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
aravindsv 0:ba7650f404af 307
aravindsv 0:ba7650f404af 308 /* Check the HSE State */
aravindsv 0:ba7650f404af 309 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
aravindsv 0:ba7650f404af 310 {
aravindsv 0:ba7650f404af 311 /* Get Start Tick*/
aravindsv 0:ba7650f404af 312 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 313
aravindsv 0:ba7650f404af 314 /* Wait till HSE is ready */
aravindsv 0:ba7650f404af 315 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
aravindsv 0:ba7650f404af 316 {
aravindsv 0:ba7650f404af 317 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 318 {
aravindsv 0:ba7650f404af 319 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 320 }
aravindsv 0:ba7650f404af 321 }
aravindsv 0:ba7650f404af 322 }
aravindsv 0:ba7650f404af 323 else
aravindsv 0:ba7650f404af 324 {
aravindsv 0:ba7650f404af 325 /* Get Start Tick*/
aravindsv 0:ba7650f404af 326 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 327
aravindsv 0:ba7650f404af 328 /* Wait till HSE is bypassed or disabled */
aravindsv 0:ba7650f404af 329 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
aravindsv 0:ba7650f404af 330 {
aravindsv 0:ba7650f404af 331 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 332 {
aravindsv 0:ba7650f404af 333 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 334 }
aravindsv 0:ba7650f404af 335 }
aravindsv 0:ba7650f404af 336 }
aravindsv 0:ba7650f404af 337 }
aravindsv 0:ba7650f404af 338 }
aravindsv 0:ba7650f404af 339 /*----------------------------- HSI Configuration --------------------------*/
aravindsv 0:ba7650f404af 340 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
aravindsv 0:ba7650f404af 341 {
aravindsv 0:ba7650f404af 342 /* Check the parameters */
aravindsv 0:ba7650f404af 343 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
aravindsv 0:ba7650f404af 344 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
aravindsv 0:ba7650f404af 345
aravindsv 0:ba7650f404af 346 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
aravindsv 0:ba7650f404af 347 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
aravindsv 0:ba7650f404af 348 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
aravindsv 0:ba7650f404af 349 {
aravindsv 0:ba7650f404af 350 /* When HSI is used as system clock it will not disabled */
aravindsv 0:ba7650f404af 351 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
aravindsv 0:ba7650f404af 352 {
aravindsv 0:ba7650f404af 353 return HAL_ERROR;
aravindsv 0:ba7650f404af 354 }
aravindsv 0:ba7650f404af 355 /* Otherwise, just the calibration is allowed */
aravindsv 0:ba7650f404af 356 else
aravindsv 0:ba7650f404af 357 {
aravindsv 0:ba7650f404af 358 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
aravindsv 0:ba7650f404af 359 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
aravindsv 0:ba7650f404af 360 }
aravindsv 0:ba7650f404af 361 }
aravindsv 0:ba7650f404af 362 else
aravindsv 0:ba7650f404af 363 {
aravindsv 0:ba7650f404af 364 /* Check the HSI State */
aravindsv 0:ba7650f404af 365 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
aravindsv 0:ba7650f404af 366 {
aravindsv 0:ba7650f404af 367 /* Enable the Internal High Speed oscillator (HSI). */
aravindsv 0:ba7650f404af 368 __HAL_RCC_HSI_ENABLE();
aravindsv 0:ba7650f404af 369
aravindsv 0:ba7650f404af 370 /* Get Start Tick*/
aravindsv 0:ba7650f404af 371 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 372
aravindsv 0:ba7650f404af 373 /* Wait till HSI is ready */
aravindsv 0:ba7650f404af 374 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
aravindsv 0:ba7650f404af 375 {
aravindsv 0:ba7650f404af 376 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 377 {
aravindsv 0:ba7650f404af 378 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 379 }
aravindsv 0:ba7650f404af 380 }
aravindsv 0:ba7650f404af 381
aravindsv 0:ba7650f404af 382 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
aravindsv 0:ba7650f404af 383 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
aravindsv 0:ba7650f404af 384 }
aravindsv 0:ba7650f404af 385 else
aravindsv 0:ba7650f404af 386 {
aravindsv 0:ba7650f404af 387 /* Disable the Internal High Speed oscillator (HSI). */
aravindsv 0:ba7650f404af 388 __HAL_RCC_HSI_DISABLE();
aravindsv 0:ba7650f404af 389
aravindsv 0:ba7650f404af 390 /* Get Start Tick*/
aravindsv 0:ba7650f404af 391 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 392
aravindsv 0:ba7650f404af 393 /* Wait till HSI is ready */
aravindsv 0:ba7650f404af 394 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
aravindsv 0:ba7650f404af 395 {
aravindsv 0:ba7650f404af 396 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 397 {
aravindsv 0:ba7650f404af 398 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 399 }
aravindsv 0:ba7650f404af 400 }
aravindsv 0:ba7650f404af 401 }
aravindsv 0:ba7650f404af 402 }
aravindsv 0:ba7650f404af 403 }
aravindsv 0:ba7650f404af 404 /*------------------------------ LSI Configuration -------------------------*/
aravindsv 0:ba7650f404af 405 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
aravindsv 0:ba7650f404af 406 {
aravindsv 0:ba7650f404af 407 /* Check the parameters */
aravindsv 0:ba7650f404af 408 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
aravindsv 0:ba7650f404af 409
aravindsv 0:ba7650f404af 410 /* Check the LSI State */
aravindsv 0:ba7650f404af 411 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
aravindsv 0:ba7650f404af 412 {
aravindsv 0:ba7650f404af 413 /* Enable the Internal Low Speed oscillator (LSI). */
aravindsv 0:ba7650f404af 414 __HAL_RCC_LSI_ENABLE();
aravindsv 0:ba7650f404af 415
aravindsv 0:ba7650f404af 416 /* Get Start Tick*/
aravindsv 0:ba7650f404af 417 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 418
aravindsv 0:ba7650f404af 419 /* Wait till LSI is ready */
aravindsv 0:ba7650f404af 420 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
aravindsv 0:ba7650f404af 421 {
aravindsv 0:ba7650f404af 422 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 423 {
aravindsv 0:ba7650f404af 424 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 425 }
aravindsv 0:ba7650f404af 426 }
aravindsv 0:ba7650f404af 427 }
aravindsv 0:ba7650f404af 428 else
aravindsv 0:ba7650f404af 429 {
aravindsv 0:ba7650f404af 430 /* Disable the Internal Low Speed oscillator (LSI). */
aravindsv 0:ba7650f404af 431 __HAL_RCC_LSI_DISABLE();
aravindsv 0:ba7650f404af 432
aravindsv 0:ba7650f404af 433 /* Get Start Tick*/
aravindsv 0:ba7650f404af 434 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 435
aravindsv 0:ba7650f404af 436 /* Wait till LSI is ready */
aravindsv 0:ba7650f404af 437 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
aravindsv 0:ba7650f404af 438 {
aravindsv 0:ba7650f404af 439 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 440 {
aravindsv 0:ba7650f404af 441 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 442 }
aravindsv 0:ba7650f404af 443 }
aravindsv 0:ba7650f404af 444 }
aravindsv 0:ba7650f404af 445 }
aravindsv 0:ba7650f404af 446 /*------------------------------ LSE Configuration -------------------------*/
aravindsv 0:ba7650f404af 447 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
aravindsv 0:ba7650f404af 448 {
aravindsv 0:ba7650f404af 449 /* Check the parameters */
aravindsv 0:ba7650f404af 450 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
aravindsv 0:ba7650f404af 451
aravindsv 0:ba7650f404af 452 /* Enable Power Clock*/
aravindsv 0:ba7650f404af 453 __HAL_RCC_PWR_CLK_ENABLE();
aravindsv 0:ba7650f404af 454
aravindsv 0:ba7650f404af 455 /* Enable write access to Backup domain */
aravindsv 0:ba7650f404af 456 PWR->CR |= PWR_CR_DBP;
aravindsv 0:ba7650f404af 457
aravindsv 0:ba7650f404af 458 /* Wait for Backup domain Write protection disable */
aravindsv 0:ba7650f404af 459 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 460
aravindsv 0:ba7650f404af 461 while((PWR->CR & PWR_CR_DBP) == RESET)
aravindsv 0:ba7650f404af 462 {
aravindsv 0:ba7650f404af 463 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 464 {
aravindsv 0:ba7650f404af 465 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 466 }
aravindsv 0:ba7650f404af 467 }
aravindsv 0:ba7650f404af 468
aravindsv 0:ba7650f404af 469 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
aravindsv 0:ba7650f404af 470 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
aravindsv 0:ba7650f404af 471
aravindsv 0:ba7650f404af 472 /* Get Start Tick*/
aravindsv 0:ba7650f404af 473 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 474
aravindsv 0:ba7650f404af 475 /* Wait till LSE is ready */
aravindsv 0:ba7650f404af 476 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
aravindsv 0:ba7650f404af 477 {
aravindsv 0:ba7650f404af 478 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 479 {
aravindsv 0:ba7650f404af 480 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 481 }
aravindsv 0:ba7650f404af 482 }
aravindsv 0:ba7650f404af 483
aravindsv 0:ba7650f404af 484 /* Set the new LSE configuration -----------------------------------------*/
aravindsv 0:ba7650f404af 485 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
aravindsv 0:ba7650f404af 486 /* Check the LSE State */
aravindsv 0:ba7650f404af 487 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
aravindsv 0:ba7650f404af 488 {
aravindsv 0:ba7650f404af 489 /* Get Start Tick*/
aravindsv 0:ba7650f404af 490 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 491
aravindsv 0:ba7650f404af 492 /* Wait till LSE is ready */
aravindsv 0:ba7650f404af 493 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
aravindsv 0:ba7650f404af 494 {
aravindsv 0:ba7650f404af 495 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 496 {
aravindsv 0:ba7650f404af 497 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 498 }
aravindsv 0:ba7650f404af 499 }
aravindsv 0:ba7650f404af 500 }
aravindsv 0:ba7650f404af 501 else
aravindsv 0:ba7650f404af 502 {
aravindsv 0:ba7650f404af 503 /* Get Start Tick*/
aravindsv 0:ba7650f404af 504 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 505
aravindsv 0:ba7650f404af 506 /* Wait till LSE is ready */
aravindsv 0:ba7650f404af 507 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
aravindsv 0:ba7650f404af 508 {
aravindsv 0:ba7650f404af 509 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 510 {
aravindsv 0:ba7650f404af 511 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 512 }
aravindsv 0:ba7650f404af 513 }
aravindsv 0:ba7650f404af 514 }
aravindsv 0:ba7650f404af 515 }
aravindsv 0:ba7650f404af 516 /*-------------------------------- PLL Configuration -----------------------*/
aravindsv 0:ba7650f404af 517 /* Check the parameters */
aravindsv 0:ba7650f404af 518 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
aravindsv 0:ba7650f404af 519 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
aravindsv 0:ba7650f404af 520 {
aravindsv 0:ba7650f404af 521 /* Check if the PLL is used as system clock or not */
aravindsv 0:ba7650f404af 522 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
aravindsv 0:ba7650f404af 523 {
aravindsv 0:ba7650f404af 524 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
aravindsv 0:ba7650f404af 525 {
aravindsv 0:ba7650f404af 526 /* Check the parameters */
aravindsv 0:ba7650f404af 527 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
aravindsv 0:ba7650f404af 528 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
aravindsv 0:ba7650f404af 529 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
aravindsv 0:ba7650f404af 530 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
aravindsv 0:ba7650f404af 531 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
aravindsv 0:ba7650f404af 532
aravindsv 0:ba7650f404af 533 /* Disable the main PLL. */
aravindsv 0:ba7650f404af 534 __HAL_RCC_PLL_DISABLE();
aravindsv 0:ba7650f404af 535
aravindsv 0:ba7650f404af 536 /* Get Start Tick*/
aravindsv 0:ba7650f404af 537 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 538
aravindsv 0:ba7650f404af 539 /* Wait till PLL is ready */
aravindsv 0:ba7650f404af 540 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
aravindsv 0:ba7650f404af 541 {
aravindsv 0:ba7650f404af 542 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 543 {
aravindsv 0:ba7650f404af 544 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 545 }
aravindsv 0:ba7650f404af 546 }
aravindsv 0:ba7650f404af 547
aravindsv 0:ba7650f404af 548 /* Configure the main PLL clock source, multiplication and division factors. */
aravindsv 0:ba7650f404af 549 WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
aravindsv 0:ba7650f404af 550 RCC_OscInitStruct->PLL.PLLM | \
aravindsv 0:ba7650f404af 551 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
aravindsv 0:ba7650f404af 552 (((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
aravindsv 0:ba7650f404af 553 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
aravindsv 0:ba7650f404af 554 /* Enable the main PLL. */
aravindsv 0:ba7650f404af 555 __HAL_RCC_PLL_ENABLE();
aravindsv 0:ba7650f404af 556
aravindsv 0:ba7650f404af 557 /* Get Start Tick*/
aravindsv 0:ba7650f404af 558 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 559
aravindsv 0:ba7650f404af 560 /* Wait till PLL is ready */
aravindsv 0:ba7650f404af 561 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
aravindsv 0:ba7650f404af 562 {
aravindsv 0:ba7650f404af 563 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 564 {
aravindsv 0:ba7650f404af 565 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 566 }
aravindsv 0:ba7650f404af 567 }
aravindsv 0:ba7650f404af 568 }
aravindsv 0:ba7650f404af 569 else
aravindsv 0:ba7650f404af 570 {
aravindsv 0:ba7650f404af 571 /* Disable the main PLL. */
aravindsv 0:ba7650f404af 572 __HAL_RCC_PLL_DISABLE();
aravindsv 0:ba7650f404af 573
aravindsv 0:ba7650f404af 574 /* Get Start Tick*/
aravindsv 0:ba7650f404af 575 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 576
aravindsv 0:ba7650f404af 577 /* Wait till PLL is ready */
aravindsv 0:ba7650f404af 578 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
aravindsv 0:ba7650f404af 579 {
aravindsv 0:ba7650f404af 580 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 581 {
aravindsv 0:ba7650f404af 582 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 583 }
aravindsv 0:ba7650f404af 584 }
aravindsv 0:ba7650f404af 585 }
aravindsv 0:ba7650f404af 586 }
aravindsv 0:ba7650f404af 587 else
aravindsv 0:ba7650f404af 588 {
aravindsv 0:ba7650f404af 589 return HAL_ERROR;
aravindsv 0:ba7650f404af 590 }
aravindsv 0:ba7650f404af 591 }
aravindsv 0:ba7650f404af 592 return HAL_OK;
aravindsv 0:ba7650f404af 593 }
aravindsv 0:ba7650f404af 594
aravindsv 0:ba7650f404af 595 /**
aravindsv 0:ba7650f404af 596 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
aravindsv 0:ba7650f404af 597 * parameters in the RCC_ClkInitStruct.
aravindsv 0:ba7650f404af 598 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
aravindsv 0:ba7650f404af 599 * contains the configuration information for the RCC peripheral.
aravindsv 0:ba7650f404af 600 * @param FLatency: FLASH Latency, this parameter depend on device selected
aravindsv 0:ba7650f404af 601 *
aravindsv 0:ba7650f404af 602 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
aravindsv 0:ba7650f404af 603 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
aravindsv 0:ba7650f404af 604 *
aravindsv 0:ba7650f404af 605 * @note The HSI is used (enabled by hardware) as system clock source after
aravindsv 0:ba7650f404af 606 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
aravindsv 0:ba7650f404af 607 * of failure of the HSE used directly or indirectly as system clock
aravindsv 0:ba7650f404af 608 * (if the Clock Security System CSS is enabled).
aravindsv 0:ba7650f404af 609 *
aravindsv 0:ba7650f404af 610 * @note A switch from one clock source to another occurs only if the target
aravindsv 0:ba7650f404af 611 * clock source is ready (clock stable after startup delay or PLL locked).
aravindsv 0:ba7650f404af 612 * If a clock source which is not yet ready is selected, the switch will
aravindsv 0:ba7650f404af 613 * occur when the clock source will be ready.
aravindsv 0:ba7650f404af 614 *
aravindsv 0:ba7650f404af 615 * @note Depending on the device voltage range, the software has to set correctly
aravindsv 0:ba7650f404af 616 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
aravindsv 0:ba7650f404af 617 * (for more details refer to section above "Initialization/de-initialization functions")
aravindsv 0:ba7650f404af 618 * @retval None
aravindsv 0:ba7650f404af 619 */
aravindsv 0:ba7650f404af 620 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
aravindsv 0:ba7650f404af 621 {
aravindsv 0:ba7650f404af 622 uint32_t tickstart = 0;
aravindsv 0:ba7650f404af 623
aravindsv 0:ba7650f404af 624 /* Check the parameters */
aravindsv 0:ba7650f404af 625 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
aravindsv 0:ba7650f404af 626 assert_param(IS_FLASH_LATENCY(FLatency));
aravindsv 0:ba7650f404af 627
aravindsv 0:ba7650f404af 628 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
aravindsv 0:ba7650f404af 629 must be correctly programmed according to the frequency of the CPU clock
aravindsv 0:ba7650f404af 630 (HCLK) and the supply voltage of the device. */
aravindsv 0:ba7650f404af 631
aravindsv 0:ba7650f404af 632 /* Increasing the CPU frequency */
aravindsv 0:ba7650f404af 633 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
aravindsv 0:ba7650f404af 634 {
aravindsv 0:ba7650f404af 635 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
aravindsv 0:ba7650f404af 636 __HAL_FLASH_SET_LATENCY(FLatency);
aravindsv 0:ba7650f404af 637
aravindsv 0:ba7650f404af 638 /* Check that the new number of wait states is taken into account to access the Flash
aravindsv 0:ba7650f404af 639 memory by reading the FLASH_ACR register */
aravindsv 0:ba7650f404af 640 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
aravindsv 0:ba7650f404af 641 {
aravindsv 0:ba7650f404af 642 return HAL_ERROR;
aravindsv 0:ba7650f404af 643 }
aravindsv 0:ba7650f404af 644
aravindsv 0:ba7650f404af 645 /*-------------------------- HCLK Configuration --------------------------*/
aravindsv 0:ba7650f404af 646 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
aravindsv 0:ba7650f404af 647 {
aravindsv 0:ba7650f404af 648 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
aravindsv 0:ba7650f404af 649 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
aravindsv 0:ba7650f404af 650 }
aravindsv 0:ba7650f404af 651
aravindsv 0:ba7650f404af 652 /*------------------------- SYSCLK Configuration ---------------------------*/
aravindsv 0:ba7650f404af 653 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
aravindsv 0:ba7650f404af 654 {
aravindsv 0:ba7650f404af 655 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
aravindsv 0:ba7650f404af 656
aravindsv 0:ba7650f404af 657 /* HSE is selected as System Clock Source */
aravindsv 0:ba7650f404af 658 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
aravindsv 0:ba7650f404af 659 {
aravindsv 0:ba7650f404af 660 /* Check the HSE ready flag */
aravindsv 0:ba7650f404af 661 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
aravindsv 0:ba7650f404af 662 {
aravindsv 0:ba7650f404af 663 return HAL_ERROR;
aravindsv 0:ba7650f404af 664 }
aravindsv 0:ba7650f404af 665 }
aravindsv 0:ba7650f404af 666 /* PLL is selected as System Clock Source */
aravindsv 0:ba7650f404af 667 else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
aravindsv 0:ba7650f404af 668 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
aravindsv 0:ba7650f404af 669 {
aravindsv 0:ba7650f404af 670 /* Check the PLL ready flag */
aravindsv 0:ba7650f404af 671 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
aravindsv 0:ba7650f404af 672 {
aravindsv 0:ba7650f404af 673 return HAL_ERROR;
aravindsv 0:ba7650f404af 674 }
aravindsv 0:ba7650f404af 675 }
aravindsv 0:ba7650f404af 676 /* HSI is selected as System Clock Source */
aravindsv 0:ba7650f404af 677 else
aravindsv 0:ba7650f404af 678 {
aravindsv 0:ba7650f404af 679 /* Check the HSI ready flag */
aravindsv 0:ba7650f404af 680 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
aravindsv 0:ba7650f404af 681 {
aravindsv 0:ba7650f404af 682 return HAL_ERROR;
aravindsv 0:ba7650f404af 683 }
aravindsv 0:ba7650f404af 684 }
aravindsv 0:ba7650f404af 685
aravindsv 0:ba7650f404af 686 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
aravindsv 0:ba7650f404af 687 /* Get Start Tick*/
aravindsv 0:ba7650f404af 688 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 689
aravindsv 0:ba7650f404af 690 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
aravindsv 0:ba7650f404af 691 {
aravindsv 0:ba7650f404af 692 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
aravindsv 0:ba7650f404af 693 {
aravindsv 0:ba7650f404af 694 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 695 {
aravindsv 0:ba7650f404af 696 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 697 }
aravindsv 0:ba7650f404af 698 }
aravindsv 0:ba7650f404af 699 }
aravindsv 0:ba7650f404af 700 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
aravindsv 0:ba7650f404af 701 {
aravindsv 0:ba7650f404af 702 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
aravindsv 0:ba7650f404af 703 {
aravindsv 0:ba7650f404af 704 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 705 {
aravindsv 0:ba7650f404af 706 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 707 }
aravindsv 0:ba7650f404af 708 }
aravindsv 0:ba7650f404af 709 }
aravindsv 0:ba7650f404af 710 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
aravindsv 0:ba7650f404af 711 {
aravindsv 0:ba7650f404af 712 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
aravindsv 0:ba7650f404af 713 {
aravindsv 0:ba7650f404af 714 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 715 {
aravindsv 0:ba7650f404af 716 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 717 }
aravindsv 0:ba7650f404af 718 }
aravindsv 0:ba7650f404af 719 }
aravindsv 0:ba7650f404af 720 else
aravindsv 0:ba7650f404af 721 {
aravindsv 0:ba7650f404af 722 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
aravindsv 0:ba7650f404af 723 {
aravindsv 0:ba7650f404af 724 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 725 {
aravindsv 0:ba7650f404af 726 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 727 }
aravindsv 0:ba7650f404af 728 }
aravindsv 0:ba7650f404af 729 }
aravindsv 0:ba7650f404af 730 }
aravindsv 0:ba7650f404af 731 }
aravindsv 0:ba7650f404af 732 /* Decreasing the CPU frequency */
aravindsv 0:ba7650f404af 733 else
aravindsv 0:ba7650f404af 734 {
aravindsv 0:ba7650f404af 735 /*-------------------------- HCLK Configuration --------------------------*/
aravindsv 0:ba7650f404af 736 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
aravindsv 0:ba7650f404af 737 {
aravindsv 0:ba7650f404af 738 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
aravindsv 0:ba7650f404af 739 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
aravindsv 0:ba7650f404af 740 }
aravindsv 0:ba7650f404af 741
aravindsv 0:ba7650f404af 742 /*------------------------- SYSCLK Configuration -------------------------*/
aravindsv 0:ba7650f404af 743 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
aravindsv 0:ba7650f404af 744 {
aravindsv 0:ba7650f404af 745 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
aravindsv 0:ba7650f404af 746
aravindsv 0:ba7650f404af 747 /* HSE is selected as System Clock Source */
aravindsv 0:ba7650f404af 748 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
aravindsv 0:ba7650f404af 749 {
aravindsv 0:ba7650f404af 750 /* Check the HSE ready flag */
aravindsv 0:ba7650f404af 751 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
aravindsv 0:ba7650f404af 752 {
aravindsv 0:ba7650f404af 753 return HAL_ERROR;
aravindsv 0:ba7650f404af 754 }
aravindsv 0:ba7650f404af 755 }
aravindsv 0:ba7650f404af 756 /* PLL is selected as System Clock Source */
aravindsv 0:ba7650f404af 757 else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
aravindsv 0:ba7650f404af 758 (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
aravindsv 0:ba7650f404af 759 {
aravindsv 0:ba7650f404af 760 /* Check the PLL ready flag */
aravindsv 0:ba7650f404af 761 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
aravindsv 0:ba7650f404af 762 {
aravindsv 0:ba7650f404af 763 return HAL_ERROR;
aravindsv 0:ba7650f404af 764 }
aravindsv 0:ba7650f404af 765 }
aravindsv 0:ba7650f404af 766 /* HSI is selected as System Clock Source */
aravindsv 0:ba7650f404af 767 else
aravindsv 0:ba7650f404af 768 {
aravindsv 0:ba7650f404af 769 /* Check the HSI ready flag */
aravindsv 0:ba7650f404af 770 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
aravindsv 0:ba7650f404af 771 {
aravindsv 0:ba7650f404af 772 return HAL_ERROR;
aravindsv 0:ba7650f404af 773 }
aravindsv 0:ba7650f404af 774 }
aravindsv 0:ba7650f404af 775 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
aravindsv 0:ba7650f404af 776 /* Get Start Tick*/
aravindsv 0:ba7650f404af 777 tickstart = HAL_GetTick();
aravindsv 0:ba7650f404af 778
aravindsv 0:ba7650f404af 779 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
aravindsv 0:ba7650f404af 780 {
aravindsv 0:ba7650f404af 781 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
aravindsv 0:ba7650f404af 782 {
aravindsv 0:ba7650f404af 783 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 784 {
aravindsv 0:ba7650f404af 785 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 786 }
aravindsv 0:ba7650f404af 787 }
aravindsv 0:ba7650f404af 788 }
aravindsv 0:ba7650f404af 789 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
aravindsv 0:ba7650f404af 790 {
aravindsv 0:ba7650f404af 791 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
aravindsv 0:ba7650f404af 792 {
aravindsv 0:ba7650f404af 793 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 794 {
aravindsv 0:ba7650f404af 795 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 796 }
aravindsv 0:ba7650f404af 797 }
aravindsv 0:ba7650f404af 798 }
aravindsv 0:ba7650f404af 799 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
aravindsv 0:ba7650f404af 800 {
aravindsv 0:ba7650f404af 801 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
aravindsv 0:ba7650f404af 802 {
aravindsv 0:ba7650f404af 803 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 804 {
aravindsv 0:ba7650f404af 805 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 806 }
aravindsv 0:ba7650f404af 807 }
aravindsv 0:ba7650f404af 808 }
aravindsv 0:ba7650f404af 809 else
aravindsv 0:ba7650f404af 810 {
aravindsv 0:ba7650f404af 811 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
aravindsv 0:ba7650f404af 812 {
aravindsv 0:ba7650f404af 813 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
aravindsv 0:ba7650f404af 814 {
aravindsv 0:ba7650f404af 815 return HAL_TIMEOUT;
aravindsv 0:ba7650f404af 816 }
aravindsv 0:ba7650f404af 817 }
aravindsv 0:ba7650f404af 818 }
aravindsv 0:ba7650f404af 819 }
aravindsv 0:ba7650f404af 820
aravindsv 0:ba7650f404af 821 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
aravindsv 0:ba7650f404af 822 __HAL_FLASH_SET_LATENCY(FLatency);
aravindsv 0:ba7650f404af 823
aravindsv 0:ba7650f404af 824 /* Check that the new number of wait states is taken into account to access the Flash
aravindsv 0:ba7650f404af 825 memory by reading the FLASH_ACR register */
aravindsv 0:ba7650f404af 826 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
aravindsv 0:ba7650f404af 827 {
aravindsv 0:ba7650f404af 828 return HAL_ERROR;
aravindsv 0:ba7650f404af 829 }
aravindsv 0:ba7650f404af 830 }
aravindsv 0:ba7650f404af 831
aravindsv 0:ba7650f404af 832 /*-------------------------- PCLK1 Configuration ---------------------------*/
aravindsv 0:ba7650f404af 833 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
aravindsv 0:ba7650f404af 834 {
aravindsv 0:ba7650f404af 835 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
aravindsv 0:ba7650f404af 836 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
aravindsv 0:ba7650f404af 837 }
aravindsv 0:ba7650f404af 838
aravindsv 0:ba7650f404af 839 /*-------------------------- PCLK2 Configuration ---------------------------*/
aravindsv 0:ba7650f404af 840 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
aravindsv 0:ba7650f404af 841 {
aravindsv 0:ba7650f404af 842 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
aravindsv 0:ba7650f404af 843 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
aravindsv 0:ba7650f404af 844 }
aravindsv 0:ba7650f404af 845
aravindsv 0:ba7650f404af 846 /* Configure the source of time base considering new system clocks settings*/
aravindsv 0:ba7650f404af 847 HAL_InitTick (TICK_INT_PRIORITY);
aravindsv 0:ba7650f404af 848
aravindsv 0:ba7650f404af 849 return HAL_OK;
aravindsv 0:ba7650f404af 850 }
aravindsv 0:ba7650f404af 851
aravindsv 0:ba7650f404af 852 /**
aravindsv 0:ba7650f404af 853 * @}
aravindsv 0:ba7650f404af 854 */
aravindsv 0:ba7650f404af 855
aravindsv 0:ba7650f404af 856 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
aravindsv 0:ba7650f404af 857 * @brief RCC clocks control functions
aravindsv 0:ba7650f404af 858 *
aravindsv 0:ba7650f404af 859 @verbatim
aravindsv 0:ba7650f404af 860 ===============================================================================
aravindsv 0:ba7650f404af 861 ##### Peripheral Control functions #####
aravindsv 0:ba7650f404af 862 ===============================================================================
aravindsv 0:ba7650f404af 863 [..]
aravindsv 0:ba7650f404af 864 This subsection provides a set of functions allowing to control the RCC Clocks
aravindsv 0:ba7650f404af 865 frequencies.
aravindsv 0:ba7650f404af 866
aravindsv 0:ba7650f404af 867 @endverbatim
aravindsv 0:ba7650f404af 868 * @{
aravindsv 0:ba7650f404af 869 */
aravindsv 0:ba7650f404af 870
aravindsv 0:ba7650f404af 871 /**
aravindsv 0:ba7650f404af 872 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
aravindsv 0:ba7650f404af 873 * @note PA8/PC9 should be configured in alternate function mode.
aravindsv 0:ba7650f404af 874 * @param RCC_MCOx: specifies the output direction for the clock source.
aravindsv 0:ba7650f404af 875 * This parameter can be one of the following values:
aravindsv 0:ba7650f404af 876 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
aravindsv 0:ba7650f404af 877 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
aravindsv 0:ba7650f404af 878 * @param RCC_MCOSource: specifies the clock source to output.
aravindsv 0:ba7650f404af 879 * This parameter can be one of the following values:
aravindsv 0:ba7650f404af 880 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
aravindsv 0:ba7650f404af 881 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
aravindsv 0:ba7650f404af 882 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
aravindsv 0:ba7650f404af 883 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
aravindsv 0:ba7650f404af 884 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
aravindsv 0:ba7650f404af 885 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
aravindsv 0:ba7650f404af 886 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
aravindsv 0:ba7650f404af 887 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
aravindsv 0:ba7650f404af 888 * @param RCC_MCODiv: specifies the MCOx prescaler.
aravindsv 0:ba7650f404af 889 * This parameter can be one of the following values:
aravindsv 0:ba7650f404af 890 * @arg RCC_MCODIV_1: no division applied to MCOx clock
aravindsv 0:ba7650f404af 891 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
aravindsv 0:ba7650f404af 892 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
aravindsv 0:ba7650f404af 893 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
aravindsv 0:ba7650f404af 894 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
aravindsv 0:ba7650f404af 895 * @retval None
aravindsv 0:ba7650f404af 896 */
aravindsv 0:ba7650f404af 897 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
aravindsv 0:ba7650f404af 898 {
aravindsv 0:ba7650f404af 899 GPIO_InitTypeDef GPIO_InitStruct;
aravindsv 0:ba7650f404af 900 /* Check the parameters */
aravindsv 0:ba7650f404af 901 assert_param(IS_RCC_MCO(RCC_MCOx));
aravindsv 0:ba7650f404af 902 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
aravindsv 0:ba7650f404af 903 /* RCC_MCO1 */
aravindsv 0:ba7650f404af 904 if(RCC_MCOx == RCC_MCO1)
aravindsv 0:ba7650f404af 905 {
aravindsv 0:ba7650f404af 906 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
aravindsv 0:ba7650f404af 907
aravindsv 0:ba7650f404af 908 /* MCO1 Clock Enable */
aravindsv 0:ba7650f404af 909 __MCO1_CLK_ENABLE();
aravindsv 0:ba7650f404af 910
aravindsv 0:ba7650f404af 911 /* Configure the MCO1 pin in alternate function mode */
aravindsv 0:ba7650f404af 912 GPIO_InitStruct.Pin = MCO1_PIN;
aravindsv 0:ba7650f404af 913 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
aravindsv 0:ba7650f404af 914 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
aravindsv 0:ba7650f404af 915 GPIO_InitStruct.Pull = GPIO_NOPULL;
aravindsv 0:ba7650f404af 916 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
aravindsv 0:ba7650f404af 917 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
aravindsv 0:ba7650f404af 918
aravindsv 0:ba7650f404af 919 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
aravindsv 0:ba7650f404af 920 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
aravindsv 0:ba7650f404af 921 }
aravindsv 0:ba7650f404af 922 else
aravindsv 0:ba7650f404af 923 {
aravindsv 0:ba7650f404af 924 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
aravindsv 0:ba7650f404af 925
aravindsv 0:ba7650f404af 926 /* MCO2 Clock Enable */
aravindsv 0:ba7650f404af 927 __MCO2_CLK_ENABLE();
aravindsv 0:ba7650f404af 928
aravindsv 0:ba7650f404af 929 /* Configure the MCO2 pin in alternate function mode */
aravindsv 0:ba7650f404af 930 GPIO_InitStruct.Pin = MCO2_PIN;
aravindsv 0:ba7650f404af 931 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
aravindsv 0:ba7650f404af 932 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
aravindsv 0:ba7650f404af 933 GPIO_InitStruct.Pull = GPIO_NOPULL;
aravindsv 0:ba7650f404af 934 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
aravindsv 0:ba7650f404af 935 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
aravindsv 0:ba7650f404af 936
aravindsv 0:ba7650f404af 937 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
aravindsv 0:ba7650f404af 938 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
aravindsv 0:ba7650f404af 939 }
aravindsv 0:ba7650f404af 940 }
aravindsv 0:ba7650f404af 941
aravindsv 0:ba7650f404af 942 /**
aravindsv 0:ba7650f404af 943 * @brief Enables the Clock Security System.
aravindsv 0:ba7650f404af 944 * @note If a failure is detected on the HSE oscillator clock, this oscillator
aravindsv 0:ba7650f404af 945 * is automatically disabled and an interrupt is generated to inform the
aravindsv 0:ba7650f404af 946 * software about the failure (Clock Security System Interrupt, CSSI),
aravindsv 0:ba7650f404af 947 * allowing the MCU to perform rescue operations. The CSSI is linked to
aravindsv 0:ba7650f404af 948 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
aravindsv 0:ba7650f404af 949 * @retval None
aravindsv 0:ba7650f404af 950 */
aravindsv 0:ba7650f404af 951 void HAL_RCC_EnableCSS(void)
aravindsv 0:ba7650f404af 952 {
aravindsv 0:ba7650f404af 953 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
aravindsv 0:ba7650f404af 954 }
aravindsv 0:ba7650f404af 955
aravindsv 0:ba7650f404af 956 /**
aravindsv 0:ba7650f404af 957 * @brief Disables the Clock Security System.
aravindsv 0:ba7650f404af 958 * @retval None
aravindsv 0:ba7650f404af 959 */
aravindsv 0:ba7650f404af 960 void HAL_RCC_DisableCSS(void)
aravindsv 0:ba7650f404af 961 {
aravindsv 0:ba7650f404af 962 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
aravindsv 0:ba7650f404af 963 }
aravindsv 0:ba7650f404af 964
aravindsv 0:ba7650f404af 965 /**
aravindsv 0:ba7650f404af 966 * @brief Returns the SYSCLK frequency
aravindsv 0:ba7650f404af 967 *
aravindsv 0:ba7650f404af 968 * @note The system frequency computed by this function is not the real
aravindsv 0:ba7650f404af 969 * frequency in the chip. It is calculated based on the predefined
aravindsv 0:ba7650f404af 970 * constant and the selected clock source:
aravindsv 0:ba7650f404af 971 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
aravindsv 0:ba7650f404af 972 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
aravindsv 0:ba7650f404af 973 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
aravindsv 0:ba7650f404af 974 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
aravindsv 0:ba7650f404af 975 * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
aravindsv 0:ba7650f404af 976 * 16 MHz) but the real value may vary depending on the variations
aravindsv 0:ba7650f404af 977 * in voltage and temperature.
aravindsv 0:ba7650f404af 978 * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
aravindsv 0:ba7650f404af 979 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
aravindsv 0:ba7650f404af 980 * frequency of the crystal used. Otherwise, this function may
aravindsv 0:ba7650f404af 981 * have wrong result.
aravindsv 0:ba7650f404af 982 *
aravindsv 0:ba7650f404af 983 * @note The result of this function could be not correct when using fractional
aravindsv 0:ba7650f404af 984 * value for HSE crystal.
aravindsv 0:ba7650f404af 985 *
aravindsv 0:ba7650f404af 986 * @note This function can be used by the user application to compute the
aravindsv 0:ba7650f404af 987 * baudrate for the communication peripherals or configure other parameters.
aravindsv 0:ba7650f404af 988 *
aravindsv 0:ba7650f404af 989 * @note Each time SYSCLK changes, this function must be called to update the
aravindsv 0:ba7650f404af 990 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
aravindsv 0:ba7650f404af 991 *
aravindsv 0:ba7650f404af 992 *
aravindsv 0:ba7650f404af 993 * @retval SYSCLK frequency
aravindsv 0:ba7650f404af 994 */
aravindsv 0:ba7650f404af 995 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
aravindsv 0:ba7650f404af 996 {
aravindsv 0:ba7650f404af 997 uint32_t pllm = 0, pllvco = 0, pllp = 0;
aravindsv 0:ba7650f404af 998 uint32_t sysclockfreq = 0;
aravindsv 0:ba7650f404af 999
aravindsv 0:ba7650f404af 1000 /* Get SYSCLK source -------------------------------------------------------*/
aravindsv 0:ba7650f404af 1001 switch (RCC->CFGR & RCC_CFGR_SWS)
aravindsv 0:ba7650f404af 1002 {
aravindsv 0:ba7650f404af 1003 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
aravindsv 0:ba7650f404af 1004 {
aravindsv 0:ba7650f404af 1005 sysclockfreq = HSI_VALUE;
aravindsv 0:ba7650f404af 1006 break;
aravindsv 0:ba7650f404af 1007 }
aravindsv 0:ba7650f404af 1008 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
aravindsv 0:ba7650f404af 1009 {
aravindsv 0:ba7650f404af 1010 sysclockfreq = HSE_VALUE;
aravindsv 0:ba7650f404af 1011 break;
aravindsv 0:ba7650f404af 1012 }
aravindsv 0:ba7650f404af 1013 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
aravindsv 0:ba7650f404af 1014 {
aravindsv 0:ba7650f404af 1015 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
aravindsv 0:ba7650f404af 1016 SYSCLK = PLL_VCO / PLLP */
aravindsv 0:ba7650f404af 1017 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
aravindsv 0:ba7650f404af 1018 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
aravindsv 0:ba7650f404af 1019 {
aravindsv 0:ba7650f404af 1020 /* HSE used as PLL clock source */
aravindsv 0:ba7650f404af 1021 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
aravindsv 0:ba7650f404af 1022 }
aravindsv 0:ba7650f404af 1023 else
aravindsv 0:ba7650f404af 1024 {
aravindsv 0:ba7650f404af 1025 /* HSI used as PLL clock source */
aravindsv 0:ba7650f404af 1026 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
aravindsv 0:ba7650f404af 1027 }
aravindsv 0:ba7650f404af 1028 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
aravindsv 0:ba7650f404af 1029
aravindsv 0:ba7650f404af 1030 sysclockfreq = pllvco/pllp;
aravindsv 0:ba7650f404af 1031 break;
aravindsv 0:ba7650f404af 1032 }
aravindsv 0:ba7650f404af 1033 default:
aravindsv 0:ba7650f404af 1034 {
aravindsv 0:ba7650f404af 1035 sysclockfreq = HSI_VALUE;
aravindsv 0:ba7650f404af 1036 break;
aravindsv 0:ba7650f404af 1037 }
aravindsv 0:ba7650f404af 1038 }
aravindsv 0:ba7650f404af 1039 return sysclockfreq;
aravindsv 0:ba7650f404af 1040 }
aravindsv 0:ba7650f404af 1041
aravindsv 0:ba7650f404af 1042 /**
aravindsv 0:ba7650f404af 1043 * @brief Returns the HCLK frequency
aravindsv 0:ba7650f404af 1044 * @note Each time HCLK changes, this function must be called to update the
aravindsv 0:ba7650f404af 1045 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
aravindsv 0:ba7650f404af 1046 *
aravindsv 0:ba7650f404af 1047 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
aravindsv 0:ba7650f404af 1048 * and updated within this function
aravindsv 0:ba7650f404af 1049 * @retval HCLK frequency
aravindsv 0:ba7650f404af 1050 */
aravindsv 0:ba7650f404af 1051 uint32_t HAL_RCC_GetHCLKFreq(void)
aravindsv 0:ba7650f404af 1052 {
aravindsv 0:ba7650f404af 1053 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
aravindsv 0:ba7650f404af 1054 return SystemCoreClock;
aravindsv 0:ba7650f404af 1055 }
aravindsv 0:ba7650f404af 1056
aravindsv 0:ba7650f404af 1057 /**
aravindsv 0:ba7650f404af 1058 * @brief Returns the PCLK1 frequency
aravindsv 0:ba7650f404af 1059 * @note Each time PCLK1 changes, this function must be called to update the
aravindsv 0:ba7650f404af 1060 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
aravindsv 0:ba7650f404af 1061 * @retval PCLK1 frequency
aravindsv 0:ba7650f404af 1062 */
aravindsv 0:ba7650f404af 1063 uint32_t HAL_RCC_GetPCLK1Freq(void)
aravindsv 0:ba7650f404af 1064 {
aravindsv 0:ba7650f404af 1065 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
aravindsv 0:ba7650f404af 1066 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
aravindsv 0:ba7650f404af 1067 }
aravindsv 0:ba7650f404af 1068
aravindsv 0:ba7650f404af 1069 /**
aravindsv 0:ba7650f404af 1070 * @brief Returns the PCLK2 frequency
aravindsv 0:ba7650f404af 1071 * @note Each time PCLK2 changes, this function must be called to update the
aravindsv 0:ba7650f404af 1072 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
aravindsv 0:ba7650f404af 1073 * @retval PCLK2 frequency
aravindsv 0:ba7650f404af 1074 */
aravindsv 0:ba7650f404af 1075 uint32_t HAL_RCC_GetPCLK2Freq(void)
aravindsv 0:ba7650f404af 1076 {
aravindsv 0:ba7650f404af 1077 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
aravindsv 0:ba7650f404af 1078 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
aravindsv 0:ba7650f404af 1079 }
aravindsv 0:ba7650f404af 1080
aravindsv 0:ba7650f404af 1081 /**
aravindsv 0:ba7650f404af 1082 * @brief Configures the RCC_OscInitStruct according to the internal
aravindsv 0:ba7650f404af 1083 * RCC configuration registers.
aravindsv 0:ba7650f404af 1084 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
aravindsv 0:ba7650f404af 1085 * will be configured.
aravindsv 0:ba7650f404af 1086 * @retval None
aravindsv 0:ba7650f404af 1087 */
aravindsv 0:ba7650f404af 1088 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
aravindsv 0:ba7650f404af 1089 {
aravindsv 0:ba7650f404af 1090 /* Set all possible values for the Oscillator type parameter ---------------*/
aravindsv 0:ba7650f404af 1091 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
aravindsv 0:ba7650f404af 1092
aravindsv 0:ba7650f404af 1093 /* Get the HSE configuration -----------------------------------------------*/
aravindsv 0:ba7650f404af 1094 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
aravindsv 0:ba7650f404af 1095 {
aravindsv 0:ba7650f404af 1096 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
aravindsv 0:ba7650f404af 1097 }
aravindsv 0:ba7650f404af 1098 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
aravindsv 0:ba7650f404af 1099 {
aravindsv 0:ba7650f404af 1100 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
aravindsv 0:ba7650f404af 1101 }
aravindsv 0:ba7650f404af 1102 else
aravindsv 0:ba7650f404af 1103 {
aravindsv 0:ba7650f404af 1104 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
aravindsv 0:ba7650f404af 1105 }
aravindsv 0:ba7650f404af 1106
aravindsv 0:ba7650f404af 1107 /* Get the HSI configuration -----------------------------------------------*/
aravindsv 0:ba7650f404af 1108 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
aravindsv 0:ba7650f404af 1109 {
aravindsv 0:ba7650f404af 1110 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
aravindsv 0:ba7650f404af 1111 }
aravindsv 0:ba7650f404af 1112 else
aravindsv 0:ba7650f404af 1113 {
aravindsv 0:ba7650f404af 1114 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
aravindsv 0:ba7650f404af 1115 }
aravindsv 0:ba7650f404af 1116
aravindsv 0:ba7650f404af 1117 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
aravindsv 0:ba7650f404af 1118
aravindsv 0:ba7650f404af 1119 /* Get the LSE configuration -----------------------------------------------*/
aravindsv 0:ba7650f404af 1120 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
aravindsv 0:ba7650f404af 1121 {
aravindsv 0:ba7650f404af 1122 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
aravindsv 0:ba7650f404af 1123 }
aravindsv 0:ba7650f404af 1124 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
aravindsv 0:ba7650f404af 1125 {
aravindsv 0:ba7650f404af 1126 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
aravindsv 0:ba7650f404af 1127 }
aravindsv 0:ba7650f404af 1128 else
aravindsv 0:ba7650f404af 1129 {
aravindsv 0:ba7650f404af 1130 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
aravindsv 0:ba7650f404af 1131 }
aravindsv 0:ba7650f404af 1132
aravindsv 0:ba7650f404af 1133 /* Get the LSI configuration -----------------------------------------------*/
aravindsv 0:ba7650f404af 1134 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
aravindsv 0:ba7650f404af 1135 {
aravindsv 0:ba7650f404af 1136 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
aravindsv 0:ba7650f404af 1137 }
aravindsv 0:ba7650f404af 1138 else
aravindsv 0:ba7650f404af 1139 {
aravindsv 0:ba7650f404af 1140 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
aravindsv 0:ba7650f404af 1141 }
aravindsv 0:ba7650f404af 1142
aravindsv 0:ba7650f404af 1143 /* Get the PLL configuration -----------------------------------------------*/
aravindsv 0:ba7650f404af 1144 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
aravindsv 0:ba7650f404af 1145 {
aravindsv 0:ba7650f404af 1146 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
aravindsv 0:ba7650f404af 1147 }
aravindsv 0:ba7650f404af 1148 else
aravindsv 0:ba7650f404af 1149 {
aravindsv 0:ba7650f404af 1150 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
aravindsv 0:ba7650f404af 1151 }
aravindsv 0:ba7650f404af 1152 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
aravindsv 0:ba7650f404af 1153 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
aravindsv 0:ba7650f404af 1154 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
aravindsv 0:ba7650f404af 1155 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
aravindsv 0:ba7650f404af 1156 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
aravindsv 0:ba7650f404af 1157 }
aravindsv 0:ba7650f404af 1158
aravindsv 0:ba7650f404af 1159 /**
aravindsv 0:ba7650f404af 1160 * @brief Configures the RCC_ClkInitStruct according to the internal
aravindsv 0:ba7650f404af 1161 * RCC configuration registers.
aravindsv 0:ba7650f404af 1162 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
aravindsv 0:ba7650f404af 1163 * will be configured.
aravindsv 0:ba7650f404af 1164 * @param pFLatency: Pointer on the Flash Latency.
aravindsv 0:ba7650f404af 1165 * @retval None
aravindsv 0:ba7650f404af 1166 */
aravindsv 0:ba7650f404af 1167 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
aravindsv 0:ba7650f404af 1168 {
aravindsv 0:ba7650f404af 1169 /* Set all possible values for the Clock type parameter --------------------*/
aravindsv 0:ba7650f404af 1170 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
aravindsv 0:ba7650f404af 1171
aravindsv 0:ba7650f404af 1172 /* Get the SYSCLK configuration --------------------------------------------*/
aravindsv 0:ba7650f404af 1173 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
aravindsv 0:ba7650f404af 1174
aravindsv 0:ba7650f404af 1175 /* Get the HCLK configuration ----------------------------------------------*/
aravindsv 0:ba7650f404af 1176 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
aravindsv 0:ba7650f404af 1177
aravindsv 0:ba7650f404af 1178 /* Get the APB1 configuration ----------------------------------------------*/
aravindsv 0:ba7650f404af 1179 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
aravindsv 0:ba7650f404af 1180
aravindsv 0:ba7650f404af 1181 /* Get the APB2 configuration ----------------------------------------------*/
aravindsv 0:ba7650f404af 1182 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
aravindsv 0:ba7650f404af 1183
aravindsv 0:ba7650f404af 1184 /* Get the Flash Wait State (Latency) configuration ------------------------*/
aravindsv 0:ba7650f404af 1185 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
aravindsv 0:ba7650f404af 1186 }
aravindsv 0:ba7650f404af 1187
aravindsv 0:ba7650f404af 1188 /**
aravindsv 0:ba7650f404af 1189 * @brief This function handles the RCC CSS interrupt request.
aravindsv 0:ba7650f404af 1190 * @note This API should be called under the NMI_Handler().
aravindsv 0:ba7650f404af 1191 * @retval None
aravindsv 0:ba7650f404af 1192 */
aravindsv 0:ba7650f404af 1193 void HAL_RCC_NMI_IRQHandler(void)
aravindsv 0:ba7650f404af 1194 {
aravindsv 0:ba7650f404af 1195 /* Check RCC CSSF flag */
aravindsv 0:ba7650f404af 1196 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
aravindsv 0:ba7650f404af 1197 {
aravindsv 0:ba7650f404af 1198 /* RCC Clock Security System interrupt user callback */
aravindsv 0:ba7650f404af 1199 HAL_RCC_CSSCallback();
aravindsv 0:ba7650f404af 1200
aravindsv 0:ba7650f404af 1201 /* Clear RCC CSS pending bit */
aravindsv 0:ba7650f404af 1202 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
aravindsv 0:ba7650f404af 1203 }
aravindsv 0:ba7650f404af 1204 }
aravindsv 0:ba7650f404af 1205
aravindsv 0:ba7650f404af 1206 /**
aravindsv 0:ba7650f404af 1207 * @brief RCC Clock Security System interrupt callback
aravindsv 0:ba7650f404af 1208 * @retval None
aravindsv 0:ba7650f404af 1209 */
aravindsv 0:ba7650f404af 1210 __weak void HAL_RCC_CSSCallback(void)
aravindsv 0:ba7650f404af 1211 {
aravindsv 0:ba7650f404af 1212 /* NOTE : This function Should not be modified, when the callback is needed,
aravindsv 0:ba7650f404af 1213 the HAL_RCC_CSSCallback could be implemented in the user file
aravindsv 0:ba7650f404af 1214 */
aravindsv 0:ba7650f404af 1215 }
aravindsv 0:ba7650f404af 1216
aravindsv 0:ba7650f404af 1217 /**
aravindsv 0:ba7650f404af 1218 * @}
aravindsv 0:ba7650f404af 1219 */
aravindsv 0:ba7650f404af 1220
aravindsv 0:ba7650f404af 1221 /**
aravindsv 0:ba7650f404af 1222 * @}
aravindsv 0:ba7650f404af 1223 */
aravindsv 0:ba7650f404af 1224
aravindsv 0:ba7650f404af 1225 #endif /* HAL_RCC_MODULE_ENABLED */
aravindsv 0:ba7650f404af 1226 /**
aravindsv 0:ba7650f404af 1227 * @}
aravindsv 0:ba7650f404af 1228 */
aravindsv 0:ba7650f404af 1229
aravindsv 0:ba7650f404af 1230 /**
aravindsv 0:ba7650f404af 1231 * @}
aravindsv 0:ba7650f404af 1232 */
aravindsv 0:ba7650f404af 1233
aravindsv 0:ba7650f404af 1234 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/