Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/cmsis/TARGET_STM/TARGET_STM32F4XX/stm32f4xx.h@0:ba7650f404af, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 02:26:59 2015 +0000
Revision:
0:ba7650f404af
Reduced HSE_STARTUP_TIMEOUT to 500 ms, fixed some compiler warnings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 /**
aravindsv 0:ba7650f404af 2 ******************************************************************************
aravindsv 0:ba7650f404af 3 * @file stm32f4xx.h
aravindsv 0:ba7650f404af 4 * @author MCD Application Team
aravindsv 0:ba7650f404af 5 * @version V1.1.0
aravindsv 0:ba7650f404af 6 * @date 11-January-2013
aravindsv 0:ba7650f404af 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
aravindsv 0:ba7650f404af 8 * This file contains all the peripheral register's definitions, bits
aravindsv 0:ba7650f404af 9 * definitions and memory mapping for STM32F4xx devices.
aravindsv 0:ba7650f404af 10 *
aravindsv 0:ba7650f404af 11 * The file is the unique include file that the application programmer
aravindsv 0:ba7650f404af 12 * is using in the C source code, usually in main.c. This file contains:
aravindsv 0:ba7650f404af 13 * - Configuration section that allows to select:
aravindsv 0:ba7650f404af 14 * - The device used in the target application
aravindsv 0:ba7650f404af 15 * - To use or not the peripheral's drivers in application code(i.e.
aravindsv 0:ba7650f404af 16 * code will be based on direct access to peripheral's registers
aravindsv 0:ba7650f404af 17 * rather than drivers API), this option is controlled by
aravindsv 0:ba7650f404af 18 * "#define USE_STDPERIPH_DRIVER"
aravindsv 0:ba7650f404af 19 * - To change few application-specific parameters such as the HSE
aravindsv 0:ba7650f404af 20 * crystal frequency
aravindsv 0:ba7650f404af 21 * - Data structures and the address mapping for all peripherals
aravindsv 0:ba7650f404af 22 * - Peripheral's registers declarations and bits definition
aravindsv 0:ba7650f404af 23 * - Macros to access peripheral's registers hardware
aravindsv 0:ba7650f404af 24 *
aravindsv 0:ba7650f404af 25 ******************************************************************************
aravindsv 0:ba7650f404af 26 * @attention
aravindsv 0:ba7650f404af 27 *
aravindsv 0:ba7650f404af 28 * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
aravindsv 0:ba7650f404af 29 *
aravindsv 0:ba7650f404af 30 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
aravindsv 0:ba7650f404af 31 * You may not use this file except in compliance with the License.
aravindsv 0:ba7650f404af 32 * You may obtain a copy of the License at:
aravindsv 0:ba7650f404af 33 *
aravindsv 0:ba7650f404af 34 * http://www.st.com/software_license_agreement_liberty_v2
aravindsv 0:ba7650f404af 35 *
aravindsv 0:ba7650f404af 36 * Unless required by applicable law or agreed to in writing, software
aravindsv 0:ba7650f404af 37 * distributed under the License is distributed on an "AS IS" BASIS,
aravindsv 0:ba7650f404af 38 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
aravindsv 0:ba7650f404af 39 * See the License for the specific language governing permissions and
aravindsv 0:ba7650f404af 40 * limitations under the License.
aravindsv 0:ba7650f404af 41 *
aravindsv 0:ba7650f404af 42 ******************************************************************************
aravindsv 0:ba7650f404af 43 */
aravindsv 0:ba7650f404af 44
aravindsv 0:ba7650f404af 45 /** @addtogroup CMSIS
aravindsv 0:ba7650f404af 46 * @{
aravindsv 0:ba7650f404af 47 */
aravindsv 0:ba7650f404af 48
aravindsv 0:ba7650f404af 49 /** @addtogroup stm32f4xx
aravindsv 0:ba7650f404af 50 * @{
aravindsv 0:ba7650f404af 51 */
aravindsv 0:ba7650f404af 52
aravindsv 0:ba7650f404af 53 #ifndef __STM32F4xx_H
aravindsv 0:ba7650f404af 54 #define __STM32F4xx_H
aravindsv 0:ba7650f404af 55
aravindsv 0:ba7650f404af 56 #ifdef __cplusplus
aravindsv 0:ba7650f404af 57 extern "C" {
aravindsv 0:ba7650f404af 58 #endif /* __cplusplus */
aravindsv 0:ba7650f404af 59
aravindsv 0:ba7650f404af 60 /** @addtogroup Library_configuration_section
aravindsv 0:ba7650f404af 61 * @{
aravindsv 0:ba7650f404af 62 */
aravindsv 0:ba7650f404af 63
aravindsv 0:ba7650f404af 64 /* Uncomment the line below according to the target STM32 device used in your
aravindsv 0:ba7650f404af 65 application
aravindsv 0:ba7650f404af 66 */
aravindsv 0:ba7650f404af 67
aravindsv 0:ba7650f404af 68 #if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X)
aravindsv 0:ba7650f404af 69 #define STM32F40XX /*!< STM32F40xx/41xx Devices */
aravindsv 0:ba7650f404af 70 /* #define STM32F427X */ /*!< STM32F427x/437x Devices*/
aravindsv 0:ba7650f404af 71 #endif
aravindsv 0:ba7650f404af 72
aravindsv 0:ba7650f404af 73
aravindsv 0:ba7650f404af 74 /* Tip: To avoid modifying this file each time you need to switch between these
aravindsv 0:ba7650f404af 75 devices, you can define the device in your toolchain compiler preprocessor.
aravindsv 0:ba7650f404af 76 */
aravindsv 0:ba7650f404af 77
aravindsv 0:ba7650f404af 78 #if !defined (STM32F4XX) && !defined (STM32F40XX) && !defined (STM32F427X)
aravindsv 0:ba7650f404af 79 #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
aravindsv 0:ba7650f404af 80 #endif
aravindsv 0:ba7650f404af 81
aravindsv 0:ba7650f404af 82 #if !defined (USE_STDPERIPH_DRIVER)
aravindsv 0:ba7650f404af 83 /**
aravindsv 0:ba7650f404af 84 * @brief Comment the line below if you will not use the peripherals drivers.
aravindsv 0:ba7650f404af 85 In this case, these drivers will not be included and the application code will
aravindsv 0:ba7650f404af 86 be based on direct access to peripherals registers
aravindsv 0:ba7650f404af 87 */
aravindsv 0:ba7650f404af 88 /*#define USE_STDPERIPH_DRIVER */
aravindsv 0:ba7650f404af 89 #endif /* USE_STDPERIPH_DRIVER */
aravindsv 0:ba7650f404af 90
aravindsv 0:ba7650f404af 91 /**
aravindsv 0:ba7650f404af 92 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
aravindsv 0:ba7650f404af 93 used in your application
aravindsv 0:ba7650f404af 94
aravindsv 0:ba7650f404af 95 Tip: To avoid modifying this file each time you need to use different HSE, you
aravindsv 0:ba7650f404af 96 can define the HSE value in your toolchain compiler preprocessor.
aravindsv 0:ba7650f404af 97 */
aravindsv 0:ba7650f404af 98
aravindsv 0:ba7650f404af 99 #if !defined (HSE_VALUE)
aravindsv 0:ba7650f404af 100 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
aravindsv 0:ba7650f404af 101 #endif /* HSE_VALUE */
aravindsv 0:ba7650f404af 102
aravindsv 0:ba7650f404af 103 /**
aravindsv 0:ba7650f404af 104 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
aravindsv 0:ba7650f404af 105 Timeout value
aravindsv 0:ba7650f404af 106 */
aravindsv 0:ba7650f404af 107 #if !defined (HSE_STARTUP_TIMEOUT)
aravindsv 0:ba7650f404af 108 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
aravindsv 0:ba7650f404af 109 #endif /* HSE_STARTUP_TIMEOUT */
aravindsv 0:ba7650f404af 110
aravindsv 0:ba7650f404af 111 #if !defined (HSI_VALUE)
aravindsv 0:ba7650f404af 112 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
aravindsv 0:ba7650f404af 113 #endif /* HSI_VALUE */
aravindsv 0:ba7650f404af 114
aravindsv 0:ba7650f404af 115 /**
aravindsv 0:ba7650f404af 116 * @brief STM32F4XX Standard Peripherals Library version number V1.1.0
aravindsv 0:ba7650f404af 117 */
aravindsv 0:ba7650f404af 118 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
aravindsv 0:ba7650f404af 119 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
aravindsv 0:ba7650f404af 120 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
aravindsv 0:ba7650f404af 121 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
aravindsv 0:ba7650f404af 122 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
aravindsv 0:ba7650f404af 123 |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
aravindsv 0:ba7650f404af 124 |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
aravindsv 0:ba7650f404af 125 |(__STM32F4XX_STDPERIPH_VERSION_RC))
aravindsv 0:ba7650f404af 126
aravindsv 0:ba7650f404af 127 /**
aravindsv 0:ba7650f404af 128 * @}
aravindsv 0:ba7650f404af 129 */
aravindsv 0:ba7650f404af 130
aravindsv 0:ba7650f404af 131 /** @addtogroup Configuration_section_for_CMSIS
aravindsv 0:ba7650f404af 132 * @{
aravindsv 0:ba7650f404af 133 */
aravindsv 0:ba7650f404af 134
aravindsv 0:ba7650f404af 135 /**
aravindsv 0:ba7650f404af 136 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
aravindsv 0:ba7650f404af 137 */
aravindsv 0:ba7650f404af 138 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
aravindsv 0:ba7650f404af 139 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
aravindsv 0:ba7650f404af 140 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
aravindsv 0:ba7650f404af 141 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
aravindsv 0:ba7650f404af 142 #define __FPU_PRESENT 1 /*!< FPU present */
aravindsv 0:ba7650f404af 143
aravindsv 0:ba7650f404af 144 /**
aravindsv 0:ba7650f404af 145 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
aravindsv 0:ba7650f404af 146 * in @ref Library_configuration_section
aravindsv 0:ba7650f404af 147 */
aravindsv 0:ba7650f404af 148 typedef enum IRQn
aravindsv 0:ba7650f404af 149 {
aravindsv 0:ba7650f404af 150 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
aravindsv 0:ba7650f404af 151 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
aravindsv 0:ba7650f404af 152 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
aravindsv 0:ba7650f404af 153 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
aravindsv 0:ba7650f404af 154 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
aravindsv 0:ba7650f404af 155 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
aravindsv 0:ba7650f404af 156 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
aravindsv 0:ba7650f404af 157 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
aravindsv 0:ba7650f404af 158 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
aravindsv 0:ba7650f404af 159 /****** STM32 specific Interrupt Numbers **********************************************************************/
aravindsv 0:ba7650f404af 160 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
aravindsv 0:ba7650f404af 161 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
aravindsv 0:ba7650f404af 162 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
aravindsv 0:ba7650f404af 163 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
aravindsv 0:ba7650f404af 164 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
aravindsv 0:ba7650f404af 165 RCC_IRQn = 5, /*!< RCC global Interrupt */
aravindsv 0:ba7650f404af 166 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
aravindsv 0:ba7650f404af 167 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
aravindsv 0:ba7650f404af 168 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
aravindsv 0:ba7650f404af 169 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
aravindsv 0:ba7650f404af 170 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
aravindsv 0:ba7650f404af 171 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
aravindsv 0:ba7650f404af 172 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
aravindsv 0:ba7650f404af 173 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
aravindsv 0:ba7650f404af 174 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
aravindsv 0:ba7650f404af 175 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
aravindsv 0:ba7650f404af 176 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
aravindsv 0:ba7650f404af 177 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
aravindsv 0:ba7650f404af 178 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
aravindsv 0:ba7650f404af 179 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
aravindsv 0:ba7650f404af 180 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
aravindsv 0:ba7650f404af 181 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
aravindsv 0:ba7650f404af 182 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
aravindsv 0:ba7650f404af 183 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
aravindsv 0:ba7650f404af 184 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
aravindsv 0:ba7650f404af 185 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
aravindsv 0:ba7650f404af 186 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
aravindsv 0:ba7650f404af 187 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
aravindsv 0:ba7650f404af 188 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
aravindsv 0:ba7650f404af 189 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
aravindsv 0:ba7650f404af 190 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
aravindsv 0:ba7650f404af 191 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
aravindsv 0:ba7650f404af 192 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
aravindsv 0:ba7650f404af 193 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
aravindsv 0:ba7650f404af 194 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
aravindsv 0:ba7650f404af 195 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
aravindsv 0:ba7650f404af 196 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
aravindsv 0:ba7650f404af 197 USART1_IRQn = 37, /*!< USART1 global Interrupt */
aravindsv 0:ba7650f404af 198 USART2_IRQn = 38, /*!< USART2 global Interrupt */
aravindsv 0:ba7650f404af 199 USART3_IRQn = 39, /*!< USART3 global Interrupt */
aravindsv 0:ba7650f404af 200 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
aravindsv 0:ba7650f404af 201 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
aravindsv 0:ba7650f404af 202 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
aravindsv 0:ba7650f404af 203 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
aravindsv 0:ba7650f404af 204 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
aravindsv 0:ba7650f404af 205 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
aravindsv 0:ba7650f404af 206 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
aravindsv 0:ba7650f404af 207 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
aravindsv 0:ba7650f404af 208 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
aravindsv 0:ba7650f404af 209 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
aravindsv 0:ba7650f404af 210 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
aravindsv 0:ba7650f404af 211 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
aravindsv 0:ba7650f404af 212 UART4_IRQn = 52, /*!< UART4 global Interrupt */
aravindsv 0:ba7650f404af 213 UART5_IRQn = 53, /*!< UART5 global Interrupt */
aravindsv 0:ba7650f404af 214 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
aravindsv 0:ba7650f404af 215 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
aravindsv 0:ba7650f404af 216 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
aravindsv 0:ba7650f404af 217 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
aravindsv 0:ba7650f404af 218 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
aravindsv 0:ba7650f404af 219 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
aravindsv 0:ba7650f404af 220 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
aravindsv 0:ba7650f404af 221 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
aravindsv 0:ba7650f404af 222 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
aravindsv 0:ba7650f404af 223 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
aravindsv 0:ba7650f404af 224 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
aravindsv 0:ba7650f404af 225 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
aravindsv 0:ba7650f404af 226 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
aravindsv 0:ba7650f404af 227 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
aravindsv 0:ba7650f404af 228 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
aravindsv 0:ba7650f404af 229 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
aravindsv 0:ba7650f404af 230 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
aravindsv 0:ba7650f404af 231 USART6_IRQn = 71, /*!< USART6 global interrupt */
aravindsv 0:ba7650f404af 232 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
aravindsv 0:ba7650f404af 233 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
aravindsv 0:ba7650f404af 234 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
aravindsv 0:ba7650f404af 235 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
aravindsv 0:ba7650f404af 236 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
aravindsv 0:ba7650f404af 237 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
aravindsv 0:ba7650f404af 238 DCMI_IRQn = 78, /*!< DCMI global interrupt */
aravindsv 0:ba7650f404af 239 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
aravindsv 0:ba7650f404af 240 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
aravindsv 0:ba7650f404af 241
aravindsv 0:ba7650f404af 242 #ifdef STM32F40XX
aravindsv 0:ba7650f404af 243 FPU_IRQn = 81 /*!< FPU global interrupt */
aravindsv 0:ba7650f404af 244 #endif /* STM32F40XX */
aravindsv 0:ba7650f404af 245
aravindsv 0:ba7650f404af 246 #ifdef STM32F427X
aravindsv 0:ba7650f404af 247 FPU_IRQn = 81, /*!< FPU global interrupt */
aravindsv 0:ba7650f404af 248 UART7_IRQn = 82, /*!< UART7 global interrupt */
aravindsv 0:ba7650f404af 249 UART8_IRQn = 83, /*!< UART8 global interrupt */
aravindsv 0:ba7650f404af 250 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
aravindsv 0:ba7650f404af 251 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
aravindsv 0:ba7650f404af 252 SPI6_IRQn = 86 /*!< SPI6 global Interrupt */
aravindsv 0:ba7650f404af 253 #endif /* STM32F427X */
aravindsv 0:ba7650f404af 254
aravindsv 0:ba7650f404af 255 } IRQn_Type;
aravindsv 0:ba7650f404af 256
aravindsv 0:ba7650f404af 257 /**
aravindsv 0:ba7650f404af 258 * @}
aravindsv 0:ba7650f404af 259 */
aravindsv 0:ba7650f404af 260
aravindsv 0:ba7650f404af 261 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
aravindsv 0:ba7650f404af 262 #include "system_stm32f4xx.h"
aravindsv 0:ba7650f404af 263 #include <stdint.h>
aravindsv 0:ba7650f404af 264
aravindsv 0:ba7650f404af 265 /** @addtogroup Exported_types
aravindsv 0:ba7650f404af 266 * @{
aravindsv 0:ba7650f404af 267 */
aravindsv 0:ba7650f404af 268 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
aravindsv 0:ba7650f404af 269 typedef int32_t s32;
aravindsv 0:ba7650f404af 270 typedef int16_t s16;
aravindsv 0:ba7650f404af 271 typedef int8_t s8;
aravindsv 0:ba7650f404af 272
aravindsv 0:ba7650f404af 273 typedef const int32_t sc32; /*!< Read Only */
aravindsv 0:ba7650f404af 274 typedef const int16_t sc16; /*!< Read Only */
aravindsv 0:ba7650f404af 275 typedef const int8_t sc8; /*!< Read Only */
aravindsv 0:ba7650f404af 276
aravindsv 0:ba7650f404af 277 typedef __IO int32_t vs32;
aravindsv 0:ba7650f404af 278 typedef __IO int16_t vs16;
aravindsv 0:ba7650f404af 279 typedef __IO int8_t vs8;
aravindsv 0:ba7650f404af 280
aravindsv 0:ba7650f404af 281 typedef __I int32_t vsc32; /*!< Read Only */
aravindsv 0:ba7650f404af 282 typedef __I int16_t vsc16; /*!< Read Only */
aravindsv 0:ba7650f404af 283 typedef __I int8_t vsc8; /*!< Read Only */
aravindsv 0:ba7650f404af 284
aravindsv 0:ba7650f404af 285 typedef uint32_t u32;
aravindsv 0:ba7650f404af 286 typedef uint16_t u16;
aravindsv 0:ba7650f404af 287 typedef uint8_t u8;
aravindsv 0:ba7650f404af 288
aravindsv 0:ba7650f404af 289 typedef const uint32_t uc32; /*!< Read Only */
aravindsv 0:ba7650f404af 290 typedef const uint16_t uc16; /*!< Read Only */
aravindsv 0:ba7650f404af 291 typedef const uint8_t uc8; /*!< Read Only */
aravindsv 0:ba7650f404af 292
aravindsv 0:ba7650f404af 293 typedef __IO uint32_t vu32;
aravindsv 0:ba7650f404af 294 typedef __IO uint16_t vu16;
aravindsv 0:ba7650f404af 295 typedef __IO uint8_t vu8;
aravindsv 0:ba7650f404af 296
aravindsv 0:ba7650f404af 297 typedef __I uint32_t vuc32; /*!< Read Only */
aravindsv 0:ba7650f404af 298 typedef __I uint16_t vuc16; /*!< Read Only */
aravindsv 0:ba7650f404af 299 typedef __I uint8_t vuc8; /*!< Read Only */
aravindsv 0:ba7650f404af 300
aravindsv 0:ba7650f404af 301 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
aravindsv 0:ba7650f404af 302
aravindsv 0:ba7650f404af 303 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
aravindsv 0:ba7650f404af 304 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
aravindsv 0:ba7650f404af 305
aravindsv 0:ba7650f404af 306 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
aravindsv 0:ba7650f404af 307
aravindsv 0:ba7650f404af 308 /**
aravindsv 0:ba7650f404af 309 * @}
aravindsv 0:ba7650f404af 310 */
aravindsv 0:ba7650f404af 311
aravindsv 0:ba7650f404af 312 /** @addtogroup Peripheral_registers_structures
aravindsv 0:ba7650f404af 313 * @{
aravindsv 0:ba7650f404af 314 */
aravindsv 0:ba7650f404af 315
aravindsv 0:ba7650f404af 316 /**
aravindsv 0:ba7650f404af 317 * @brief Analog to Digital Converter
aravindsv 0:ba7650f404af 318 */
aravindsv 0:ba7650f404af 319
aravindsv 0:ba7650f404af 320 typedef struct
aravindsv 0:ba7650f404af 321 {
aravindsv 0:ba7650f404af 322 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 323 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
aravindsv 0:ba7650f404af 324 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
aravindsv 0:ba7650f404af 325 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
aravindsv 0:ba7650f404af 326 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
aravindsv 0:ba7650f404af 327 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
aravindsv 0:ba7650f404af 328 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
aravindsv 0:ba7650f404af 329 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
aravindsv 0:ba7650f404af 330 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
aravindsv 0:ba7650f404af 331 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
aravindsv 0:ba7650f404af 332 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
aravindsv 0:ba7650f404af 333 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
aravindsv 0:ba7650f404af 334 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
aravindsv 0:ba7650f404af 335 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
aravindsv 0:ba7650f404af 336 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
aravindsv 0:ba7650f404af 337 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
aravindsv 0:ba7650f404af 338 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
aravindsv 0:ba7650f404af 339 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
aravindsv 0:ba7650f404af 340 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
aravindsv 0:ba7650f404af 341 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
aravindsv 0:ba7650f404af 342 } ADC_TypeDef;
aravindsv 0:ba7650f404af 343
aravindsv 0:ba7650f404af 344 typedef struct
aravindsv 0:ba7650f404af 345 {
aravindsv 0:ba7650f404af 346 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
aravindsv 0:ba7650f404af 347 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
aravindsv 0:ba7650f404af 348 __IO uint32_t CDR; /*!< ADC common regular data register for dual
aravindsv 0:ba7650f404af 349 AND triple modes, Address offset: ADC1 base address + 0x308 */
aravindsv 0:ba7650f404af 350 } ADC_Common_TypeDef;
aravindsv 0:ba7650f404af 351
aravindsv 0:ba7650f404af 352
aravindsv 0:ba7650f404af 353 /**
aravindsv 0:ba7650f404af 354 * @brief Controller Area Network TxMailBox
aravindsv 0:ba7650f404af 355 */
aravindsv 0:ba7650f404af 356
aravindsv 0:ba7650f404af 357 typedef struct
aravindsv 0:ba7650f404af 358 {
aravindsv 0:ba7650f404af 359 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
aravindsv 0:ba7650f404af 360 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
aravindsv 0:ba7650f404af 361 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
aravindsv 0:ba7650f404af 362 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
aravindsv 0:ba7650f404af 363 } CAN_TxMailBox_TypeDef;
aravindsv 0:ba7650f404af 364
aravindsv 0:ba7650f404af 365 /**
aravindsv 0:ba7650f404af 366 * @brief Controller Area Network FIFOMailBox
aravindsv 0:ba7650f404af 367 */
aravindsv 0:ba7650f404af 368
aravindsv 0:ba7650f404af 369 typedef struct
aravindsv 0:ba7650f404af 370 {
aravindsv 0:ba7650f404af 371 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
aravindsv 0:ba7650f404af 372 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
aravindsv 0:ba7650f404af 373 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
aravindsv 0:ba7650f404af 374 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
aravindsv 0:ba7650f404af 375 } CAN_FIFOMailBox_TypeDef;
aravindsv 0:ba7650f404af 376
aravindsv 0:ba7650f404af 377 /**
aravindsv 0:ba7650f404af 378 * @brief Controller Area Network FilterRegister
aravindsv 0:ba7650f404af 379 */
aravindsv 0:ba7650f404af 380
aravindsv 0:ba7650f404af 381 typedef struct
aravindsv 0:ba7650f404af 382 {
aravindsv 0:ba7650f404af 383 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
aravindsv 0:ba7650f404af 384 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
aravindsv 0:ba7650f404af 385 } CAN_FilterRegister_TypeDef;
aravindsv 0:ba7650f404af 386
aravindsv 0:ba7650f404af 387 /**
aravindsv 0:ba7650f404af 388 * @brief Controller Area Network
aravindsv 0:ba7650f404af 389 */
aravindsv 0:ba7650f404af 390
aravindsv 0:ba7650f404af 391 typedef struct
aravindsv 0:ba7650f404af 392 {
aravindsv 0:ba7650f404af 393 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 394 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 395 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 396 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 397 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 398 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 399 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 400 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 401 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
aravindsv 0:ba7650f404af 402 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
aravindsv 0:ba7650f404af 403 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
aravindsv 0:ba7650f404af 404 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
aravindsv 0:ba7650f404af 405 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
aravindsv 0:ba7650f404af 406 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
aravindsv 0:ba7650f404af 407 uint32_t RESERVED2; /*!< Reserved, 0x208 */
aravindsv 0:ba7650f404af 408 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
aravindsv 0:ba7650f404af 409 uint32_t RESERVED3; /*!< Reserved, 0x210 */
aravindsv 0:ba7650f404af 410 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
aravindsv 0:ba7650f404af 411 uint32_t RESERVED4; /*!< Reserved, 0x218 */
aravindsv 0:ba7650f404af 412 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
aravindsv 0:ba7650f404af 413 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
aravindsv 0:ba7650f404af 414 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
aravindsv 0:ba7650f404af 415 } CAN_TypeDef;
aravindsv 0:ba7650f404af 416
aravindsv 0:ba7650f404af 417 /**
aravindsv 0:ba7650f404af 418 * @brief CRC calculation unit
aravindsv 0:ba7650f404af 419 */
aravindsv 0:ba7650f404af 420
aravindsv 0:ba7650f404af 421 typedef struct
aravindsv 0:ba7650f404af 422 {
aravindsv 0:ba7650f404af 423 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 424 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 425 uint8_t RESERVED0; /*!< Reserved, 0x05 */
aravindsv 0:ba7650f404af 426 uint16_t RESERVED1; /*!< Reserved, 0x06 */
aravindsv 0:ba7650f404af 427 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 428 } CRC_TypeDef;
aravindsv 0:ba7650f404af 429
aravindsv 0:ba7650f404af 430 /**
aravindsv 0:ba7650f404af 431 * @brief Digital to Analog Converter
aravindsv 0:ba7650f404af 432 */
aravindsv 0:ba7650f404af 433
aravindsv 0:ba7650f404af 434 typedef struct
aravindsv 0:ba7650f404af 435 {
aravindsv 0:ba7650f404af 436 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 437 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 438 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 439 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 440 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 441 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 442 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 443 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 444 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 445 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
aravindsv 0:ba7650f404af 446 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
aravindsv 0:ba7650f404af 447 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
aravindsv 0:ba7650f404af 448 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
aravindsv 0:ba7650f404af 449 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
aravindsv 0:ba7650f404af 450 } DAC_TypeDef;
aravindsv 0:ba7650f404af 451
aravindsv 0:ba7650f404af 452 /**
aravindsv 0:ba7650f404af 453 * @brief Debug MCU
aravindsv 0:ba7650f404af 454 */
aravindsv 0:ba7650f404af 455
aravindsv 0:ba7650f404af 456 typedef struct
aravindsv 0:ba7650f404af 457 {
aravindsv 0:ba7650f404af 458 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
aravindsv 0:ba7650f404af 459 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 460 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 461 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 462 }DBGMCU_TypeDef;
aravindsv 0:ba7650f404af 463
aravindsv 0:ba7650f404af 464 /**
aravindsv 0:ba7650f404af 465 * @brief DCMI
aravindsv 0:ba7650f404af 466 */
aravindsv 0:ba7650f404af 467
aravindsv 0:ba7650f404af 468 typedef struct
aravindsv 0:ba7650f404af 469 {
aravindsv 0:ba7650f404af 470 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
aravindsv 0:ba7650f404af 471 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 472 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 473 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 474 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 475 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 476 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 477 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 478 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
aravindsv 0:ba7650f404af 479 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
aravindsv 0:ba7650f404af 480 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
aravindsv 0:ba7650f404af 481 } DCMI_TypeDef;
aravindsv 0:ba7650f404af 482
aravindsv 0:ba7650f404af 483 /**
aravindsv 0:ba7650f404af 484 * @brief DMA Controller
aravindsv 0:ba7650f404af 485 */
aravindsv 0:ba7650f404af 486
aravindsv 0:ba7650f404af 487 typedef struct
aravindsv 0:ba7650f404af 488 {
aravindsv 0:ba7650f404af 489 __IO uint32_t CR; /*!< DMA stream x configuration register */
aravindsv 0:ba7650f404af 490 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
aravindsv 0:ba7650f404af 491 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
aravindsv 0:ba7650f404af 492 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
aravindsv 0:ba7650f404af 493 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
aravindsv 0:ba7650f404af 494 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
aravindsv 0:ba7650f404af 495 } DMA_Stream_TypeDef;
aravindsv 0:ba7650f404af 496
aravindsv 0:ba7650f404af 497 typedef struct
aravindsv 0:ba7650f404af 498 {
aravindsv 0:ba7650f404af 499 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 500 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 501 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 502 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 503 } DMA_TypeDef;
aravindsv 0:ba7650f404af 504
aravindsv 0:ba7650f404af 505 /**
aravindsv 0:ba7650f404af 506 * @brief Ethernet MAC
aravindsv 0:ba7650f404af 507 */
aravindsv 0:ba7650f404af 508
aravindsv 0:ba7650f404af 509 typedef struct
aravindsv 0:ba7650f404af 510 {
aravindsv 0:ba7650f404af 511 __IO uint32_t MACCR;
aravindsv 0:ba7650f404af 512 __IO uint32_t MACFFR;
aravindsv 0:ba7650f404af 513 __IO uint32_t MACHTHR;
aravindsv 0:ba7650f404af 514 __IO uint32_t MACHTLR;
aravindsv 0:ba7650f404af 515 __IO uint32_t MACMIIAR;
aravindsv 0:ba7650f404af 516 __IO uint32_t MACMIIDR;
aravindsv 0:ba7650f404af 517 __IO uint32_t MACFCR;
aravindsv 0:ba7650f404af 518 __IO uint32_t MACVLANTR; /* 8 */
aravindsv 0:ba7650f404af 519 uint32_t RESERVED0[2];
aravindsv 0:ba7650f404af 520 __IO uint32_t MACRWUFFR; /* 11 */
aravindsv 0:ba7650f404af 521 __IO uint32_t MACPMTCSR;
aravindsv 0:ba7650f404af 522 uint32_t RESERVED1[2];
aravindsv 0:ba7650f404af 523 __IO uint32_t MACSR; /* 15 */
aravindsv 0:ba7650f404af 524 __IO uint32_t MACIMR;
aravindsv 0:ba7650f404af 525 __IO uint32_t MACA0HR;
aravindsv 0:ba7650f404af 526 __IO uint32_t MACA0LR;
aravindsv 0:ba7650f404af 527 __IO uint32_t MACA1HR;
aravindsv 0:ba7650f404af 528 __IO uint32_t MACA1LR;
aravindsv 0:ba7650f404af 529 __IO uint32_t MACA2HR;
aravindsv 0:ba7650f404af 530 __IO uint32_t MACA2LR;
aravindsv 0:ba7650f404af 531 __IO uint32_t MACA3HR;
aravindsv 0:ba7650f404af 532 __IO uint32_t MACA3LR; /* 24 */
aravindsv 0:ba7650f404af 533 uint32_t RESERVED2[40];
aravindsv 0:ba7650f404af 534 __IO uint32_t MMCCR; /* 65 */
aravindsv 0:ba7650f404af 535 __IO uint32_t MMCRIR;
aravindsv 0:ba7650f404af 536 __IO uint32_t MMCTIR;
aravindsv 0:ba7650f404af 537 __IO uint32_t MMCRIMR;
aravindsv 0:ba7650f404af 538 __IO uint32_t MMCTIMR; /* 69 */
aravindsv 0:ba7650f404af 539 uint32_t RESERVED3[14];
aravindsv 0:ba7650f404af 540 __IO uint32_t MMCTGFSCCR; /* 84 */
aravindsv 0:ba7650f404af 541 __IO uint32_t MMCTGFMSCCR;
aravindsv 0:ba7650f404af 542 uint32_t RESERVED4[5];
aravindsv 0:ba7650f404af 543 __IO uint32_t MMCTGFCR;
aravindsv 0:ba7650f404af 544 uint32_t RESERVED5[10];
aravindsv 0:ba7650f404af 545 __IO uint32_t MMCRFCECR;
aravindsv 0:ba7650f404af 546 __IO uint32_t MMCRFAECR;
aravindsv 0:ba7650f404af 547 uint32_t RESERVED6[10];
aravindsv 0:ba7650f404af 548 __IO uint32_t MMCRGUFCR;
aravindsv 0:ba7650f404af 549 uint32_t RESERVED7[334];
aravindsv 0:ba7650f404af 550 __IO uint32_t PTPTSCR;
aravindsv 0:ba7650f404af 551 __IO uint32_t PTPSSIR;
aravindsv 0:ba7650f404af 552 __IO uint32_t PTPTSHR;
aravindsv 0:ba7650f404af 553 __IO uint32_t PTPTSLR;
aravindsv 0:ba7650f404af 554 __IO uint32_t PTPTSHUR;
aravindsv 0:ba7650f404af 555 __IO uint32_t PTPTSLUR;
aravindsv 0:ba7650f404af 556 __IO uint32_t PTPTSAR;
aravindsv 0:ba7650f404af 557 __IO uint32_t PTPTTHR;
aravindsv 0:ba7650f404af 558 __IO uint32_t PTPTTLR;
aravindsv 0:ba7650f404af 559 __IO uint32_t RESERVED8;
aravindsv 0:ba7650f404af 560 __IO uint32_t PTPTSSR;
aravindsv 0:ba7650f404af 561 uint32_t RESERVED9[565];
aravindsv 0:ba7650f404af 562 __IO uint32_t DMABMR;
aravindsv 0:ba7650f404af 563 __IO uint32_t DMATPDR;
aravindsv 0:ba7650f404af 564 __IO uint32_t DMARPDR;
aravindsv 0:ba7650f404af 565 __IO uint32_t DMARDLAR;
aravindsv 0:ba7650f404af 566 __IO uint32_t DMATDLAR;
aravindsv 0:ba7650f404af 567 __IO uint32_t DMASR;
aravindsv 0:ba7650f404af 568 __IO uint32_t DMAOMR;
aravindsv 0:ba7650f404af 569 __IO uint32_t DMAIER;
aravindsv 0:ba7650f404af 570 __IO uint32_t DMAMFBOCR;
aravindsv 0:ba7650f404af 571 __IO uint32_t DMARSWTR;
aravindsv 0:ba7650f404af 572 uint32_t RESERVED10[8];
aravindsv 0:ba7650f404af 573 __IO uint32_t DMACHTDR;
aravindsv 0:ba7650f404af 574 __IO uint32_t DMACHRDR;
aravindsv 0:ba7650f404af 575 __IO uint32_t DMACHTBAR;
aravindsv 0:ba7650f404af 576 __IO uint32_t DMACHRBAR;
aravindsv 0:ba7650f404af 577 } ETH_TypeDef;
aravindsv 0:ba7650f404af 578
aravindsv 0:ba7650f404af 579 /**
aravindsv 0:ba7650f404af 580 * @brief External Interrupt/Event Controller
aravindsv 0:ba7650f404af 581 */
aravindsv 0:ba7650f404af 582
aravindsv 0:ba7650f404af 583 typedef struct
aravindsv 0:ba7650f404af 584 {
aravindsv 0:ba7650f404af 585 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 586 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 587 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 588 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 589 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 590 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 591 } EXTI_TypeDef;
aravindsv 0:ba7650f404af 592
aravindsv 0:ba7650f404af 593 /**
aravindsv 0:ba7650f404af 594 * @brief FLASH Registers
aravindsv 0:ba7650f404af 595 */
aravindsv 0:ba7650f404af 596
aravindsv 0:ba7650f404af 597 typedef struct
aravindsv 0:ba7650f404af 598 {
aravindsv 0:ba7650f404af 599 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 600 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 601 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 602 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 603 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 604 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
aravindsv 0:ba7650f404af 605 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
aravindsv 0:ba7650f404af 606 } FLASH_TypeDef;
aravindsv 0:ba7650f404af 607
aravindsv 0:ba7650f404af 608 /**
aravindsv 0:ba7650f404af 609 * @brief Flexible Static Memory Controller
aravindsv 0:ba7650f404af 610 */
aravindsv 0:ba7650f404af 611
aravindsv 0:ba7650f404af 612 typedef struct
aravindsv 0:ba7650f404af 613 {
aravindsv 0:ba7650f404af 614 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
aravindsv 0:ba7650f404af 615 } FSMC_Bank1_TypeDef;
aravindsv 0:ba7650f404af 616
aravindsv 0:ba7650f404af 617 /**
aravindsv 0:ba7650f404af 618 * @brief Flexible Static Memory Controller Bank1E
aravindsv 0:ba7650f404af 619 */
aravindsv 0:ba7650f404af 620
aravindsv 0:ba7650f404af 621 typedef struct
aravindsv 0:ba7650f404af 622 {
aravindsv 0:ba7650f404af 623 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
aravindsv 0:ba7650f404af 624 } FSMC_Bank1E_TypeDef;
aravindsv 0:ba7650f404af 625
aravindsv 0:ba7650f404af 626 /**
aravindsv 0:ba7650f404af 627 * @brief Flexible Static Memory Controller Bank2
aravindsv 0:ba7650f404af 628 */
aravindsv 0:ba7650f404af 629
aravindsv 0:ba7650f404af 630 typedef struct
aravindsv 0:ba7650f404af 631 {
aravindsv 0:ba7650f404af 632 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
aravindsv 0:ba7650f404af 633 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
aravindsv 0:ba7650f404af 634 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
aravindsv 0:ba7650f404af 635 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
aravindsv 0:ba7650f404af 636 uint32_t RESERVED0; /*!< Reserved, 0x70 */
aravindsv 0:ba7650f404af 637 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
aravindsv 0:ba7650f404af 638 } FSMC_Bank2_TypeDef;
aravindsv 0:ba7650f404af 639
aravindsv 0:ba7650f404af 640 /**
aravindsv 0:ba7650f404af 641 * @brief Flexible Static Memory Controller Bank3
aravindsv 0:ba7650f404af 642 */
aravindsv 0:ba7650f404af 643
aravindsv 0:ba7650f404af 644 typedef struct
aravindsv 0:ba7650f404af 645 {
aravindsv 0:ba7650f404af 646 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
aravindsv 0:ba7650f404af 647 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
aravindsv 0:ba7650f404af 648 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
aravindsv 0:ba7650f404af 649 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
aravindsv 0:ba7650f404af 650 uint32_t RESERVED0; /*!< Reserved, 0x90 */
aravindsv 0:ba7650f404af 651 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
aravindsv 0:ba7650f404af 652 } FSMC_Bank3_TypeDef;
aravindsv 0:ba7650f404af 653
aravindsv 0:ba7650f404af 654 /**
aravindsv 0:ba7650f404af 655 * @brief Flexible Static Memory Controller Bank4
aravindsv 0:ba7650f404af 656 */
aravindsv 0:ba7650f404af 657
aravindsv 0:ba7650f404af 658 typedef struct
aravindsv 0:ba7650f404af 659 {
aravindsv 0:ba7650f404af 660 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
aravindsv 0:ba7650f404af 661 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
aravindsv 0:ba7650f404af 662 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
aravindsv 0:ba7650f404af 663 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
aravindsv 0:ba7650f404af 664 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
aravindsv 0:ba7650f404af 665 } FSMC_Bank4_TypeDef;
aravindsv 0:ba7650f404af 666
aravindsv 0:ba7650f404af 667 /**
aravindsv 0:ba7650f404af 668 * @brief General Purpose I/O
aravindsv 0:ba7650f404af 669 */
aravindsv 0:ba7650f404af 670
aravindsv 0:ba7650f404af 671 typedef struct
aravindsv 0:ba7650f404af 672 {
aravindsv 0:ba7650f404af 673 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 674 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 675 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 676 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 677 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 678 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 679 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 680 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
aravindsv 0:ba7650f404af 681 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 682 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
aravindsv 0:ba7650f404af 683 } GPIO_TypeDef;
aravindsv 0:ba7650f404af 684
aravindsv 0:ba7650f404af 685 /**
aravindsv 0:ba7650f404af 686 * @brief System configuration controller
aravindsv 0:ba7650f404af 687 */
aravindsv 0:ba7650f404af 688
aravindsv 0:ba7650f404af 689 typedef struct
aravindsv 0:ba7650f404af 690 {
aravindsv 0:ba7650f404af 691 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 692 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 693 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
aravindsv 0:ba7650f404af 694 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
aravindsv 0:ba7650f404af 695 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 696 } SYSCFG_TypeDef;
aravindsv 0:ba7650f404af 697
aravindsv 0:ba7650f404af 698 /**
aravindsv 0:ba7650f404af 699 * @brief Inter-integrated Circuit Interface
aravindsv 0:ba7650f404af 700 */
aravindsv 0:ba7650f404af 701
aravindsv 0:ba7650f404af 702 typedef struct
aravindsv 0:ba7650f404af 703 {
aravindsv 0:ba7650f404af 704 __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
aravindsv 0:ba7650f404af 705 uint16_t RESERVED0; /*!< Reserved, 0x02 */
aravindsv 0:ba7650f404af 706 __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
aravindsv 0:ba7650f404af 707 uint16_t RESERVED1; /*!< Reserved, 0x06 */
aravindsv 0:ba7650f404af 708 __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
aravindsv 0:ba7650f404af 709 uint16_t RESERVED2; /*!< Reserved, 0x0A */
aravindsv 0:ba7650f404af 710 __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
aravindsv 0:ba7650f404af 711 uint16_t RESERVED3; /*!< Reserved, 0x0E */
aravindsv 0:ba7650f404af 712 __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 713 uint16_t RESERVED4; /*!< Reserved, 0x12 */
aravindsv 0:ba7650f404af 714 __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
aravindsv 0:ba7650f404af 715 uint16_t RESERVED5; /*!< Reserved, 0x16 */
aravindsv 0:ba7650f404af 716 __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
aravindsv 0:ba7650f404af 717 uint16_t RESERVED6; /*!< Reserved, 0x1A */
aravindsv 0:ba7650f404af 718 __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 719 uint16_t RESERVED7; /*!< Reserved, 0x1E */
aravindsv 0:ba7650f404af 720 __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 721 uint16_t RESERVED8; /*!< Reserved, 0x22 */
aravindsv 0:ba7650f404af 722 __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
aravindsv 0:ba7650f404af 723 uint16_t RESERVED9; /*!< Reserved, 0x26 */
aravindsv 0:ba7650f404af 724 } I2C_TypeDef;
aravindsv 0:ba7650f404af 725
aravindsv 0:ba7650f404af 726 /**
aravindsv 0:ba7650f404af 727 * @brief Independent WATCHDOG
aravindsv 0:ba7650f404af 728 */
aravindsv 0:ba7650f404af 729
aravindsv 0:ba7650f404af 730 typedef struct
aravindsv 0:ba7650f404af 731 {
aravindsv 0:ba7650f404af 732 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 733 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 734 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 735 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 736 } IWDG_TypeDef;
aravindsv 0:ba7650f404af 737
aravindsv 0:ba7650f404af 738 /**
aravindsv 0:ba7650f404af 739 * @brief Power Control
aravindsv 0:ba7650f404af 740 */
aravindsv 0:ba7650f404af 741
aravindsv 0:ba7650f404af 742 typedef struct
aravindsv 0:ba7650f404af 743 {
aravindsv 0:ba7650f404af 744 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 745 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 746 } PWR_TypeDef;
aravindsv 0:ba7650f404af 747
aravindsv 0:ba7650f404af 748 /**
aravindsv 0:ba7650f404af 749 * @brief Reset and Clock Control
aravindsv 0:ba7650f404af 750 */
aravindsv 0:ba7650f404af 751
aravindsv 0:ba7650f404af 752 typedef struct
aravindsv 0:ba7650f404af 753 {
aravindsv 0:ba7650f404af 754 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 755 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 756 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 757 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 758 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 759 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 760 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 761 uint32_t RESERVED0; /*!< Reserved, 0x1C */
aravindsv 0:ba7650f404af 762 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 763 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
aravindsv 0:ba7650f404af 764 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
aravindsv 0:ba7650f404af 765 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
aravindsv 0:ba7650f404af 766 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
aravindsv 0:ba7650f404af 767 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
aravindsv 0:ba7650f404af 768 uint32_t RESERVED2; /*!< Reserved, 0x3C */
aravindsv 0:ba7650f404af 769 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
aravindsv 0:ba7650f404af 770 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
aravindsv 0:ba7650f404af 771 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
aravindsv 0:ba7650f404af 772 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
aravindsv 0:ba7650f404af 773 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
aravindsv 0:ba7650f404af 774 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
aravindsv 0:ba7650f404af 775 uint32_t RESERVED4; /*!< Reserved, 0x5C */
aravindsv 0:ba7650f404af 776 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
aravindsv 0:ba7650f404af 777 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
aravindsv 0:ba7650f404af 778 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
aravindsv 0:ba7650f404af 779 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
aravindsv 0:ba7650f404af 780 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
aravindsv 0:ba7650f404af 781 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
aravindsv 0:ba7650f404af 782 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
aravindsv 0:ba7650f404af 783 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
aravindsv 0:ba7650f404af 784
aravindsv 0:ba7650f404af 785 #ifdef STM32F427X
aravindsv 0:ba7650f404af 786 uint32_t RESERVED7; /*!< Reserved, 0x88 */
aravindsv 0:ba7650f404af 787 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
aravindsv 0:ba7650f404af 788 #endif /* STM32F427X */
aravindsv 0:ba7650f404af 789
aravindsv 0:ba7650f404af 790 } RCC_TypeDef;
aravindsv 0:ba7650f404af 791
aravindsv 0:ba7650f404af 792 /**
aravindsv 0:ba7650f404af 793 * @brief Real-Time Clock
aravindsv 0:ba7650f404af 794 */
aravindsv 0:ba7650f404af 795
aravindsv 0:ba7650f404af 796 typedef struct
aravindsv 0:ba7650f404af 797 {
aravindsv 0:ba7650f404af 798 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 799 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 800 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 801 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 802 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 803 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 804 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 805 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 806 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 807 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
aravindsv 0:ba7650f404af 808 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
aravindsv 0:ba7650f404af 809 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
aravindsv 0:ba7650f404af 810 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
aravindsv 0:ba7650f404af 811 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
aravindsv 0:ba7650f404af 812 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
aravindsv 0:ba7650f404af 813 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
aravindsv 0:ba7650f404af 814 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
aravindsv 0:ba7650f404af 815 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
aravindsv 0:ba7650f404af 816 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
aravindsv 0:ba7650f404af 817 uint32_t RESERVED7; /*!< Reserved, 0x4C */
aravindsv 0:ba7650f404af 818 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
aravindsv 0:ba7650f404af 819 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
aravindsv 0:ba7650f404af 820 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
aravindsv 0:ba7650f404af 821 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
aravindsv 0:ba7650f404af 822 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
aravindsv 0:ba7650f404af 823 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
aravindsv 0:ba7650f404af 824 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
aravindsv 0:ba7650f404af 825 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
aravindsv 0:ba7650f404af 826 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
aravindsv 0:ba7650f404af 827 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
aravindsv 0:ba7650f404af 828 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
aravindsv 0:ba7650f404af 829 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
aravindsv 0:ba7650f404af 830 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
aravindsv 0:ba7650f404af 831 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
aravindsv 0:ba7650f404af 832 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
aravindsv 0:ba7650f404af 833 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
aravindsv 0:ba7650f404af 834 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
aravindsv 0:ba7650f404af 835 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
aravindsv 0:ba7650f404af 836 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
aravindsv 0:ba7650f404af 837 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
aravindsv 0:ba7650f404af 838 } RTC_TypeDef;
aravindsv 0:ba7650f404af 839
aravindsv 0:ba7650f404af 840 /**
aravindsv 0:ba7650f404af 841 * @brief SD host Interface
aravindsv 0:ba7650f404af 842 */
aravindsv 0:ba7650f404af 843
aravindsv 0:ba7650f404af 844 typedef struct
aravindsv 0:ba7650f404af 845 {
aravindsv 0:ba7650f404af 846 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 847 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 848 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 849 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 850 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 851 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 852 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 853 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 854 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 855 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
aravindsv 0:ba7650f404af 856 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
aravindsv 0:ba7650f404af 857 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
aravindsv 0:ba7650f404af 858 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
aravindsv 0:ba7650f404af 859 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
aravindsv 0:ba7650f404af 860 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
aravindsv 0:ba7650f404af 861 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
aravindsv 0:ba7650f404af 862 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
aravindsv 0:ba7650f404af 863 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
aravindsv 0:ba7650f404af 864 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
aravindsv 0:ba7650f404af 865 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
aravindsv 0:ba7650f404af 866 } SDIO_TypeDef;
aravindsv 0:ba7650f404af 867
aravindsv 0:ba7650f404af 868 /**
aravindsv 0:ba7650f404af 869 * @brief Serial Peripheral Interface
aravindsv 0:ba7650f404af 870 */
aravindsv 0:ba7650f404af 871
aravindsv 0:ba7650f404af 872 typedef struct
aravindsv 0:ba7650f404af 873 {
aravindsv 0:ba7650f404af 874 __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
aravindsv 0:ba7650f404af 875 uint16_t RESERVED0; /*!< Reserved, 0x02 */
aravindsv 0:ba7650f404af 876 __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
aravindsv 0:ba7650f404af 877 uint16_t RESERVED1; /*!< Reserved, 0x06 */
aravindsv 0:ba7650f404af 878 __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 879 uint16_t RESERVED2; /*!< Reserved, 0x0A */
aravindsv 0:ba7650f404af 880 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 881 uint16_t RESERVED3; /*!< Reserved, 0x0E */
aravindsv 0:ba7650f404af 882 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
aravindsv 0:ba7650f404af 883 uint16_t RESERVED4; /*!< Reserved, 0x12 */
aravindsv 0:ba7650f404af 884 __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
aravindsv 0:ba7650f404af 885 uint16_t RESERVED5; /*!< Reserved, 0x16 */
aravindsv 0:ba7650f404af 886 __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
aravindsv 0:ba7650f404af 887 uint16_t RESERVED6; /*!< Reserved, 0x1A */
aravindsv 0:ba7650f404af 888 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 889 uint16_t RESERVED7; /*!< Reserved, 0x1E */
aravindsv 0:ba7650f404af 890 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 891 uint16_t RESERVED8; /*!< Reserved, 0x22 */
aravindsv 0:ba7650f404af 892 } SPI_TypeDef;
aravindsv 0:ba7650f404af 893
aravindsv 0:ba7650f404af 894 /**
aravindsv 0:ba7650f404af 895 * @brief TIM
aravindsv 0:ba7650f404af 896 */
aravindsv 0:ba7650f404af 897
aravindsv 0:ba7650f404af 898 typedef struct
aravindsv 0:ba7650f404af 899 {
aravindsv 0:ba7650f404af 900 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
aravindsv 0:ba7650f404af 901 uint16_t RESERVED0; /*!< Reserved, 0x02 */
aravindsv 0:ba7650f404af 902 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
aravindsv 0:ba7650f404af 903 uint16_t RESERVED1; /*!< Reserved, 0x06 */
aravindsv 0:ba7650f404af 904 __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 905 uint16_t RESERVED2; /*!< Reserved, 0x0A */
aravindsv 0:ba7650f404af 906 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 907 uint16_t RESERVED3; /*!< Reserved, 0x0E */
aravindsv 0:ba7650f404af 908 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 909 uint16_t RESERVED4; /*!< Reserved, 0x12 */
aravindsv 0:ba7650f404af 910 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 911 uint16_t RESERVED5; /*!< Reserved, 0x16 */
aravindsv 0:ba7650f404af 912 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
aravindsv 0:ba7650f404af 913 uint16_t RESERVED6; /*!< Reserved, 0x1A */
aravindsv 0:ba7650f404af 914 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
aravindsv 0:ba7650f404af 915 uint16_t RESERVED7; /*!< Reserved, 0x1E */
aravindsv 0:ba7650f404af 916 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 917 uint16_t RESERVED8; /*!< Reserved, 0x22 */
aravindsv 0:ba7650f404af 918 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
aravindsv 0:ba7650f404af 919 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
aravindsv 0:ba7650f404af 920 uint16_t RESERVED9; /*!< Reserved, 0x2A */
aravindsv 0:ba7650f404af 921 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
aravindsv 0:ba7650f404af 922 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
aravindsv 0:ba7650f404af 923 uint16_t RESERVED10; /*!< Reserved, 0x32 */
aravindsv 0:ba7650f404af 924 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
aravindsv 0:ba7650f404af 925 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
aravindsv 0:ba7650f404af 926 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
aravindsv 0:ba7650f404af 927 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
aravindsv 0:ba7650f404af 928 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
aravindsv 0:ba7650f404af 929 uint16_t RESERVED11; /*!< Reserved, 0x46 */
aravindsv 0:ba7650f404af 930 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
aravindsv 0:ba7650f404af 931 uint16_t RESERVED12; /*!< Reserved, 0x4A */
aravindsv 0:ba7650f404af 932 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
aravindsv 0:ba7650f404af 933 uint16_t RESERVED13; /*!< Reserved, 0x4E */
aravindsv 0:ba7650f404af 934 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
aravindsv 0:ba7650f404af 935 uint16_t RESERVED14; /*!< Reserved, 0x52 */
aravindsv 0:ba7650f404af 936 } TIM_TypeDef;
aravindsv 0:ba7650f404af 937
aravindsv 0:ba7650f404af 938 /**
aravindsv 0:ba7650f404af 939 * @brief Universal Synchronous Asynchronous Receiver Transmitter
aravindsv 0:ba7650f404af 940 */
aravindsv 0:ba7650f404af 941
aravindsv 0:ba7650f404af 942 typedef struct
aravindsv 0:ba7650f404af 943 {
aravindsv 0:ba7650f404af 944 __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 945 uint16_t RESERVED0; /*!< Reserved, 0x02 */
aravindsv 0:ba7650f404af 946 __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 947 uint16_t RESERVED1; /*!< Reserved, 0x06 */
aravindsv 0:ba7650f404af 948 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 949 uint16_t RESERVED2; /*!< Reserved, 0x0A */
aravindsv 0:ba7650f404af 950 __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
aravindsv 0:ba7650f404af 951 uint16_t RESERVED3; /*!< Reserved, 0x0E */
aravindsv 0:ba7650f404af 952 __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
aravindsv 0:ba7650f404af 953 uint16_t RESERVED4; /*!< Reserved, 0x12 */
aravindsv 0:ba7650f404af 954 __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
aravindsv 0:ba7650f404af 955 uint16_t RESERVED5; /*!< Reserved, 0x16 */
aravindsv 0:ba7650f404af 956 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 957 uint16_t RESERVED6; /*!< Reserved, 0x1A */
aravindsv 0:ba7650f404af 958 } USART_TypeDef;
aravindsv 0:ba7650f404af 959
aravindsv 0:ba7650f404af 960 /**
aravindsv 0:ba7650f404af 961 * @brief Window WATCHDOG
aravindsv 0:ba7650f404af 962 */
aravindsv 0:ba7650f404af 963
aravindsv 0:ba7650f404af 964 typedef struct
aravindsv 0:ba7650f404af 965 {
aravindsv 0:ba7650f404af 966 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 967 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 968 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 969 } WWDG_TypeDef;
aravindsv 0:ba7650f404af 970
aravindsv 0:ba7650f404af 971 /**
aravindsv 0:ba7650f404af 972 * @brief Crypto Processor
aravindsv 0:ba7650f404af 973 */
aravindsv 0:ba7650f404af 974
aravindsv 0:ba7650f404af 975 typedef struct
aravindsv 0:ba7650f404af 976 {
aravindsv 0:ba7650f404af 977 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 978 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 979 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 980 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
aravindsv 0:ba7650f404af 981 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
aravindsv 0:ba7650f404af 982 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
aravindsv 0:ba7650f404af 983 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
aravindsv 0:ba7650f404af 984 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
aravindsv 0:ba7650f404af 985 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
aravindsv 0:ba7650f404af 986 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
aravindsv 0:ba7650f404af 987 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
aravindsv 0:ba7650f404af 988 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
aravindsv 0:ba7650f404af 989 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
aravindsv 0:ba7650f404af 990 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
aravindsv 0:ba7650f404af 991 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
aravindsv 0:ba7650f404af 992 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
aravindsv 0:ba7650f404af 993 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
aravindsv 0:ba7650f404af 994 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
aravindsv 0:ba7650f404af 995 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
aravindsv 0:ba7650f404af 996 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
aravindsv 0:ba7650f404af 997 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
aravindsv 0:ba7650f404af 998 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
aravindsv 0:ba7650f404af 999 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
aravindsv 0:ba7650f404af 1000 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
aravindsv 0:ba7650f404af 1001 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
aravindsv 0:ba7650f404af 1002 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
aravindsv 0:ba7650f404af 1003 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
aravindsv 0:ba7650f404af 1004 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
aravindsv 0:ba7650f404af 1005 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
aravindsv 0:ba7650f404af 1006 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
aravindsv 0:ba7650f404af 1007 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
aravindsv 0:ba7650f404af 1008 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
aravindsv 0:ba7650f404af 1009 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
aravindsv 0:ba7650f404af 1010 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
aravindsv 0:ba7650f404af 1011 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
aravindsv 0:ba7650f404af 1012 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
aravindsv 0:ba7650f404af 1013 } CRYP_TypeDef;
aravindsv 0:ba7650f404af 1014
aravindsv 0:ba7650f404af 1015 /**
aravindsv 0:ba7650f404af 1016 * @brief HASH
aravindsv 0:ba7650f404af 1017 */
aravindsv 0:ba7650f404af 1018
aravindsv 0:ba7650f404af 1019 typedef struct
aravindsv 0:ba7650f404af 1020 {
aravindsv 0:ba7650f404af 1021 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 1022 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 1023 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 1024 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
aravindsv 0:ba7650f404af 1025 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
aravindsv 0:ba7650f404af 1026 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
aravindsv 0:ba7650f404af 1027 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
aravindsv 0:ba7650f404af 1028 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
aravindsv 0:ba7650f404af 1029 } HASH_TypeDef;
aravindsv 0:ba7650f404af 1030
aravindsv 0:ba7650f404af 1031 /**
aravindsv 0:ba7650f404af 1032 * @brief HASH_DIGEST
aravindsv 0:ba7650f404af 1033 */
aravindsv 0:ba7650f404af 1034
aravindsv 0:ba7650f404af 1035 typedef struct
aravindsv 0:ba7650f404af 1036 {
aravindsv 0:ba7650f404af 1037 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
aravindsv 0:ba7650f404af 1038 } HASH_DIGEST_TypeDef;
aravindsv 0:ba7650f404af 1039
aravindsv 0:ba7650f404af 1040 /**
aravindsv 0:ba7650f404af 1041 * @brief RNG
aravindsv 0:ba7650f404af 1042 */
aravindsv 0:ba7650f404af 1043
aravindsv 0:ba7650f404af 1044 typedef struct
aravindsv 0:ba7650f404af 1045 {
aravindsv 0:ba7650f404af 1046 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
aravindsv 0:ba7650f404af 1047 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
aravindsv 0:ba7650f404af 1048 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
aravindsv 0:ba7650f404af 1049 } RNG_TypeDef;
aravindsv 0:ba7650f404af 1050
aravindsv 0:ba7650f404af 1051 /**
aravindsv 0:ba7650f404af 1052 * @}
aravindsv 0:ba7650f404af 1053 */
aravindsv 0:ba7650f404af 1054
aravindsv 0:ba7650f404af 1055 /** @addtogroup Peripheral_memory_map
aravindsv 0:ba7650f404af 1056 * @{
aravindsv 0:ba7650f404af 1057 */
aravindsv 0:ba7650f404af 1058 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
aravindsv 0:ba7650f404af 1059 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
aravindsv 0:ba7650f404af 1060 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
aravindsv 0:ba7650f404af 1061 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
aravindsv 0:ba7650f404af 1062 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
aravindsv 0:ba7650f404af 1063 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
aravindsv 0:ba7650f404af 1064 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
aravindsv 0:ba7650f404af 1065 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
aravindsv 0:ba7650f404af 1066
aravindsv 0:ba7650f404af 1067 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
aravindsv 0:ba7650f404af 1068 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
aravindsv 0:ba7650f404af 1069 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
aravindsv 0:ba7650f404af 1070 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
aravindsv 0:ba7650f404af 1071 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
aravindsv 0:ba7650f404af 1072 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
aravindsv 0:ba7650f404af 1073
aravindsv 0:ba7650f404af 1074 /* Legacy defines */
aravindsv 0:ba7650f404af 1075 #define SRAM_BASE SRAM1_BASE
aravindsv 0:ba7650f404af 1076 #define SRAM_BB_BASE SRAM1_BB_BASE
aravindsv 0:ba7650f404af 1077
aravindsv 0:ba7650f404af 1078 /*!< Peripheral memory map */
aravindsv 0:ba7650f404af 1079 #define APB1PERIPH_BASE PERIPH_BASE
aravindsv 0:ba7650f404af 1080 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
aravindsv 0:ba7650f404af 1081 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
aravindsv 0:ba7650f404af 1082 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
aravindsv 0:ba7650f404af 1083
aravindsv 0:ba7650f404af 1084 /*!< APB1 peripherals */
aravindsv 0:ba7650f404af 1085 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
aravindsv 0:ba7650f404af 1086 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
aravindsv 0:ba7650f404af 1087 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
aravindsv 0:ba7650f404af 1088 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
aravindsv 0:ba7650f404af 1089 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
aravindsv 0:ba7650f404af 1090 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
aravindsv 0:ba7650f404af 1091 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
aravindsv 0:ba7650f404af 1092 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
aravindsv 0:ba7650f404af 1093 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
aravindsv 0:ba7650f404af 1094 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
aravindsv 0:ba7650f404af 1095 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
aravindsv 0:ba7650f404af 1096 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
aravindsv 0:ba7650f404af 1097 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
aravindsv 0:ba7650f404af 1098 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
aravindsv 0:ba7650f404af 1099 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
aravindsv 0:ba7650f404af 1100 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
aravindsv 0:ba7650f404af 1101 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
aravindsv 0:ba7650f404af 1102 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
aravindsv 0:ba7650f404af 1103 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
aravindsv 0:ba7650f404af 1104 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
aravindsv 0:ba7650f404af 1105 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
aravindsv 0:ba7650f404af 1106 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
aravindsv 0:ba7650f404af 1107 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
aravindsv 0:ba7650f404af 1108 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
aravindsv 0:ba7650f404af 1109 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
aravindsv 0:ba7650f404af 1110 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
aravindsv 0:ba7650f404af 1111 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
aravindsv 0:ba7650f404af 1112 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
aravindsv 0:ba7650f404af 1113 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
aravindsv 0:ba7650f404af 1114
aravindsv 0:ba7650f404af 1115 /*!< APB2 peripherals */
aravindsv 0:ba7650f404af 1116 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
aravindsv 0:ba7650f404af 1117 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
aravindsv 0:ba7650f404af 1118 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
aravindsv 0:ba7650f404af 1119 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
aravindsv 0:ba7650f404af 1120 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
aravindsv 0:ba7650f404af 1121 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
aravindsv 0:ba7650f404af 1122 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
aravindsv 0:ba7650f404af 1123 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
aravindsv 0:ba7650f404af 1124 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
aravindsv 0:ba7650f404af 1125 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
aravindsv 0:ba7650f404af 1126 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
aravindsv 0:ba7650f404af 1127 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
aravindsv 0:ba7650f404af 1128 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
aravindsv 0:ba7650f404af 1129 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
aravindsv 0:ba7650f404af 1130 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
aravindsv 0:ba7650f404af 1131 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
aravindsv 0:ba7650f404af 1132 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
aravindsv 0:ba7650f404af 1133 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
aravindsv 0:ba7650f404af 1134
aravindsv 0:ba7650f404af 1135 /*!< AHB1 peripherals */
aravindsv 0:ba7650f404af 1136 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
aravindsv 0:ba7650f404af 1137 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
aravindsv 0:ba7650f404af 1138 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
aravindsv 0:ba7650f404af 1139 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
aravindsv 0:ba7650f404af 1140 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
aravindsv 0:ba7650f404af 1141 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
aravindsv 0:ba7650f404af 1142 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
aravindsv 0:ba7650f404af 1143 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
aravindsv 0:ba7650f404af 1144 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
aravindsv 0:ba7650f404af 1145
aravindsv 0:ba7650f404af 1146 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
aravindsv 0:ba7650f404af 1147 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
aravindsv 0:ba7650f404af 1148 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
aravindsv 0:ba7650f404af 1149 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
aravindsv 0:ba7650f404af 1150 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
aravindsv 0:ba7650f404af 1151 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
aravindsv 0:ba7650f404af 1152 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
aravindsv 0:ba7650f404af 1153 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
aravindsv 0:ba7650f404af 1154 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
aravindsv 0:ba7650f404af 1155 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
aravindsv 0:ba7650f404af 1156 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
aravindsv 0:ba7650f404af 1157 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
aravindsv 0:ba7650f404af 1158 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
aravindsv 0:ba7650f404af 1159 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
aravindsv 0:ba7650f404af 1160 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
aravindsv 0:ba7650f404af 1161 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
aravindsv 0:ba7650f404af 1162 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
aravindsv 0:ba7650f404af 1163 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
aravindsv 0:ba7650f404af 1164 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
aravindsv 0:ba7650f404af 1165 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
aravindsv 0:ba7650f404af 1166 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
aravindsv 0:ba7650f404af 1167 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
aravindsv 0:ba7650f404af 1168 #define ETH_MAC_BASE (ETH_BASE)
aravindsv 0:ba7650f404af 1169 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
aravindsv 0:ba7650f404af 1170 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
aravindsv 0:ba7650f404af 1171 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
aravindsv 0:ba7650f404af 1172
aravindsv 0:ba7650f404af 1173 /*!< AHB2 peripherals */
aravindsv 0:ba7650f404af 1174 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
aravindsv 0:ba7650f404af 1175 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
aravindsv 0:ba7650f404af 1176 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
aravindsv 0:ba7650f404af 1177 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
aravindsv 0:ba7650f404af 1178 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
aravindsv 0:ba7650f404af 1179
aravindsv 0:ba7650f404af 1180 /*!< FSMC Bankx registers base address */
aravindsv 0:ba7650f404af 1181 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
aravindsv 0:ba7650f404af 1182 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
aravindsv 0:ba7650f404af 1183 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
aravindsv 0:ba7650f404af 1184 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
aravindsv 0:ba7650f404af 1185 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
aravindsv 0:ba7650f404af 1186
aravindsv 0:ba7650f404af 1187 /* Debug MCU registers base address */
aravindsv 0:ba7650f404af 1188 #define DBGMCU_BASE ((uint32_t )0xE0042000)
aravindsv 0:ba7650f404af 1189
aravindsv 0:ba7650f404af 1190 /**
aravindsv 0:ba7650f404af 1191 * @}
aravindsv 0:ba7650f404af 1192 */
aravindsv 0:ba7650f404af 1193
aravindsv 0:ba7650f404af 1194 /** @addtogroup Peripheral_declaration
aravindsv 0:ba7650f404af 1195 * @{
aravindsv 0:ba7650f404af 1196 */
aravindsv 0:ba7650f404af 1197 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
aravindsv 0:ba7650f404af 1198 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
aravindsv 0:ba7650f404af 1199 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
aravindsv 0:ba7650f404af 1200 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
aravindsv 0:ba7650f404af 1201 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
aravindsv 0:ba7650f404af 1202 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
aravindsv 0:ba7650f404af 1203 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
aravindsv 0:ba7650f404af 1204 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
aravindsv 0:ba7650f404af 1205 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
aravindsv 0:ba7650f404af 1206 #define RTC ((RTC_TypeDef *) RTC_BASE)
aravindsv 0:ba7650f404af 1207 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
aravindsv 0:ba7650f404af 1208 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
aravindsv 0:ba7650f404af 1209 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
aravindsv 0:ba7650f404af 1210 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
aravindsv 0:ba7650f404af 1211 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
aravindsv 0:ba7650f404af 1212 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
aravindsv 0:ba7650f404af 1213 #define USART2 ((USART_TypeDef *) USART2_BASE)
aravindsv 0:ba7650f404af 1214 #define USART3 ((USART_TypeDef *) USART3_BASE)
aravindsv 0:ba7650f404af 1215 #define UART4 ((USART_TypeDef *) UART4_BASE)
aravindsv 0:ba7650f404af 1216 #define UART5 ((USART_TypeDef *) UART5_BASE)
aravindsv 0:ba7650f404af 1217 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
aravindsv 0:ba7650f404af 1218 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
aravindsv 0:ba7650f404af 1219 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
aravindsv 0:ba7650f404af 1220 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
aravindsv 0:ba7650f404af 1221 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
aravindsv 0:ba7650f404af 1222 #define PWR ((PWR_TypeDef *) PWR_BASE)
aravindsv 0:ba7650f404af 1223 #define DAC ((DAC_TypeDef *) DAC_BASE)
aravindsv 0:ba7650f404af 1224 #define UART7 ((USART_TypeDef *) UART7_BASE)
aravindsv 0:ba7650f404af 1225 #define UART8 ((USART_TypeDef *) UART8_BASE)
aravindsv 0:ba7650f404af 1226 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
aravindsv 0:ba7650f404af 1227 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
aravindsv 0:ba7650f404af 1228 #define USART1 ((USART_TypeDef *) USART1_BASE)
aravindsv 0:ba7650f404af 1229 #define USART6 ((USART_TypeDef *) USART6_BASE)
aravindsv 0:ba7650f404af 1230 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
aravindsv 0:ba7650f404af 1231 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
aravindsv 0:ba7650f404af 1232 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
aravindsv 0:ba7650f404af 1233 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
aravindsv 0:ba7650f404af 1234 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
aravindsv 0:ba7650f404af 1235 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
aravindsv 0:ba7650f404af 1236 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
aravindsv 0:ba7650f404af 1237 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
aravindsv 0:ba7650f404af 1238 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
aravindsv 0:ba7650f404af 1239 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
aravindsv 0:ba7650f404af 1240 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
aravindsv 0:ba7650f404af 1241 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
aravindsv 0:ba7650f404af 1242 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
aravindsv 0:ba7650f404af 1243 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
aravindsv 0:ba7650f404af 1244
aravindsv 0:ba7650f404af 1245 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
aravindsv 0:ba7650f404af 1246 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
aravindsv 0:ba7650f404af 1247 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
aravindsv 0:ba7650f404af 1248 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
aravindsv 0:ba7650f404af 1249 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
aravindsv 0:ba7650f404af 1250 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
aravindsv 0:ba7650f404af 1251 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
aravindsv 0:ba7650f404af 1252 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
aravindsv 0:ba7650f404af 1253 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
aravindsv 0:ba7650f404af 1254
aravindsv 0:ba7650f404af 1255 #define CRC ((CRC_TypeDef *) CRC_BASE)
aravindsv 0:ba7650f404af 1256 #define RCC ((RCC_TypeDef *) RCC_BASE)
aravindsv 0:ba7650f404af 1257 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
aravindsv 0:ba7650f404af 1258 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
aravindsv 0:ba7650f404af 1259 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
aravindsv 0:ba7650f404af 1260 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
aravindsv 0:ba7650f404af 1261 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
aravindsv 0:ba7650f404af 1262 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
aravindsv 0:ba7650f404af 1263 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
aravindsv 0:ba7650f404af 1264 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
aravindsv 0:ba7650f404af 1265 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
aravindsv 0:ba7650f404af 1266 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
aravindsv 0:ba7650f404af 1267 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
aravindsv 0:ba7650f404af 1268 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
aravindsv 0:ba7650f404af 1269 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
aravindsv 0:ba7650f404af 1270 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
aravindsv 0:ba7650f404af 1271 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
aravindsv 0:ba7650f404af 1272 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
aravindsv 0:ba7650f404af 1273 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
aravindsv 0:ba7650f404af 1274 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
aravindsv 0:ba7650f404af 1275 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
aravindsv 0:ba7650f404af 1276 #define ETH ((ETH_TypeDef *) ETH_BASE)
aravindsv 0:ba7650f404af 1277 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
aravindsv 0:ba7650f404af 1278 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
aravindsv 0:ba7650f404af 1279 #define HASH ((HASH_TypeDef *) HASH_BASE)
aravindsv 0:ba7650f404af 1280 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
aravindsv 0:ba7650f404af 1281 #define RNG ((RNG_TypeDef *) RNG_BASE)
aravindsv 0:ba7650f404af 1282 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
aravindsv 0:ba7650f404af 1283 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
aravindsv 0:ba7650f404af 1284 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
aravindsv 0:ba7650f404af 1285 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
aravindsv 0:ba7650f404af 1286 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
aravindsv 0:ba7650f404af 1287 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
aravindsv 0:ba7650f404af 1288
aravindsv 0:ba7650f404af 1289 /**
aravindsv 0:ba7650f404af 1290 * @}
aravindsv 0:ba7650f404af 1291 */
aravindsv 0:ba7650f404af 1292
aravindsv 0:ba7650f404af 1293 /** @addtogroup Exported_constants
aravindsv 0:ba7650f404af 1294 * @{
aravindsv 0:ba7650f404af 1295 */
aravindsv 0:ba7650f404af 1296
aravindsv 0:ba7650f404af 1297 /** @addtogroup Peripheral_Registers_Bits_Definition
aravindsv 0:ba7650f404af 1298 * @{
aravindsv 0:ba7650f404af 1299 */
aravindsv 0:ba7650f404af 1300
aravindsv 0:ba7650f404af 1301 /******************************************************************************/
aravindsv 0:ba7650f404af 1302 /* Peripheral Registers_Bits_Definition */
aravindsv 0:ba7650f404af 1303 /******************************************************************************/
aravindsv 0:ba7650f404af 1304
aravindsv 0:ba7650f404af 1305 /******************************************************************************/
aravindsv 0:ba7650f404af 1306 /* */
aravindsv 0:ba7650f404af 1307 /* Analog to Digital Converter */
aravindsv 0:ba7650f404af 1308 /* */
aravindsv 0:ba7650f404af 1309 /******************************************************************************/
aravindsv 0:ba7650f404af 1310 /******************** Bit definition for ADC_SR register ********************/
aravindsv 0:ba7650f404af 1311 #define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */
aravindsv 0:ba7650f404af 1312 #define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */
aravindsv 0:ba7650f404af 1313 #define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */
aravindsv 0:ba7650f404af 1314 #define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */
aravindsv 0:ba7650f404af 1315 #define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */
aravindsv 0:ba7650f404af 1316 #define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */
aravindsv 0:ba7650f404af 1317
aravindsv 0:ba7650f404af 1318 /******************* Bit definition for ADC_CR1 register ********************/
aravindsv 0:ba7650f404af 1319 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
aravindsv 0:ba7650f404af 1320 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1321 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1322 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1323 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1324 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1325 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
aravindsv 0:ba7650f404af 1326 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
aravindsv 0:ba7650f404af 1327 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
aravindsv 0:ba7650f404af 1328 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
aravindsv 0:ba7650f404af 1329 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
aravindsv 0:ba7650f404af 1330 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
aravindsv 0:ba7650f404af 1331 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
aravindsv 0:ba7650f404af 1332 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
aravindsv 0:ba7650f404af 1333 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
aravindsv 0:ba7650f404af 1334 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1335 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1336 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1337 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
aravindsv 0:ba7650f404af 1338 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
aravindsv 0:ba7650f404af 1339 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
aravindsv 0:ba7650f404af 1340 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1341 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1342 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
aravindsv 0:ba7650f404af 1343
aravindsv 0:ba7650f404af 1344 /******************* Bit definition for ADC_CR2 register ********************/
aravindsv 0:ba7650f404af 1345 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
aravindsv 0:ba7650f404af 1346 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
aravindsv 0:ba7650f404af 1347 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
aravindsv 0:ba7650f404af 1348 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
aravindsv 0:ba7650f404af 1349 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
aravindsv 0:ba7650f404af 1350 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
aravindsv 0:ba7650f404af 1351 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
aravindsv 0:ba7650f404af 1352 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1353 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1354 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1355 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1356 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
aravindsv 0:ba7650f404af 1357 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1358 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1359 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
aravindsv 0:ba7650f404af 1360 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
aravindsv 0:ba7650f404af 1361 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1362 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1363 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1364 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1365 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
aravindsv 0:ba7650f404af 1366 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1367 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1368 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
aravindsv 0:ba7650f404af 1369
aravindsv 0:ba7650f404af 1370 /****************** Bit definition for ADC_SMPR1 register *******************/
aravindsv 0:ba7650f404af 1371 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
aravindsv 0:ba7650f404af 1372 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1373 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1374 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1375 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
aravindsv 0:ba7650f404af 1376 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1377 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1378 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1379 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
aravindsv 0:ba7650f404af 1380 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1381 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1382 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1383 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
aravindsv 0:ba7650f404af 1384 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1385 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1386 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1387 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
aravindsv 0:ba7650f404af 1388 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1389 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1390 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1391 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
aravindsv 0:ba7650f404af 1392 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1393 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1394 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1395 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
aravindsv 0:ba7650f404af 1396 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1397 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1398 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1399 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
aravindsv 0:ba7650f404af 1400 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1401 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1402 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1403 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
aravindsv 0:ba7650f404af 1404 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1405 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1406 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1407
aravindsv 0:ba7650f404af 1408 /****************** Bit definition for ADC_SMPR2 register *******************/
aravindsv 0:ba7650f404af 1409 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
aravindsv 0:ba7650f404af 1410 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1411 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1412 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1413 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
aravindsv 0:ba7650f404af 1414 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1415 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1416 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1417 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
aravindsv 0:ba7650f404af 1418 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1419 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1420 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1421 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
aravindsv 0:ba7650f404af 1422 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1423 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1424 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1425 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
aravindsv 0:ba7650f404af 1426 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1427 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1428 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1429 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
aravindsv 0:ba7650f404af 1430 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1431 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1432 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1433 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
aravindsv 0:ba7650f404af 1434 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1435 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1436 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1437 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
aravindsv 0:ba7650f404af 1438 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1439 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1440 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1441 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
aravindsv 0:ba7650f404af 1442 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1443 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1444 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1445 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
aravindsv 0:ba7650f404af 1446 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1447 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1448 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1449
aravindsv 0:ba7650f404af 1450 /****************** Bit definition for ADC_JOFR1 register *******************/
aravindsv 0:ba7650f404af 1451 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */
aravindsv 0:ba7650f404af 1452
aravindsv 0:ba7650f404af 1453 /****************** Bit definition for ADC_JOFR2 register *******************/
aravindsv 0:ba7650f404af 1454 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */
aravindsv 0:ba7650f404af 1455
aravindsv 0:ba7650f404af 1456 /****************** Bit definition for ADC_JOFR3 register *******************/
aravindsv 0:ba7650f404af 1457 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */
aravindsv 0:ba7650f404af 1458
aravindsv 0:ba7650f404af 1459 /****************** Bit definition for ADC_JOFR4 register *******************/
aravindsv 0:ba7650f404af 1460 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */
aravindsv 0:ba7650f404af 1461
aravindsv 0:ba7650f404af 1462 /******************* Bit definition for ADC_HTR register ********************/
aravindsv 0:ba7650f404af 1463 #define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */
aravindsv 0:ba7650f404af 1464
aravindsv 0:ba7650f404af 1465 /******************* Bit definition for ADC_LTR register ********************/
aravindsv 0:ba7650f404af 1466 #define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */
aravindsv 0:ba7650f404af 1467
aravindsv 0:ba7650f404af 1468 /******************* Bit definition for ADC_SQR1 register *******************/
aravindsv 0:ba7650f404af 1469 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1470 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1471 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1472 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1473 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1474 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1475 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1476 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1477 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1478 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1479 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1480 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1481 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1482 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1483 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1484 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1485 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1486 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1487 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1488 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1489 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1490 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1491 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1492 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1493 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
aravindsv 0:ba7650f404af 1494 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1495 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1496 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1497 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1498
aravindsv 0:ba7650f404af 1499 /******************* Bit definition for ADC_SQR2 register *******************/
aravindsv 0:ba7650f404af 1500 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1501 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1502 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1503 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1504 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1505 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1506 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1507 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1508 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1509 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1510 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1511 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1512 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1513 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1514 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1515 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1516 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1517 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1518 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1519 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1520 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1521 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1522 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1523 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1524 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1525 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1526 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1527 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1528 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1529 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1530 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1531 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1532 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1533 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1534 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1535 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1536
aravindsv 0:ba7650f404af 1537 /******************* Bit definition for ADC_SQR3 register *******************/
aravindsv 0:ba7650f404af 1538 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
aravindsv 0:ba7650f404af 1539 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1540 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1541 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1542 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1543 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1544 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
aravindsv 0:ba7650f404af 1545 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1546 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1547 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1548 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1549 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1550 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
aravindsv 0:ba7650f404af 1551 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1552 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1553 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1554 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1555 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1556 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1557 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1558 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1559 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1560 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1561 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1562 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1563 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1564 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1565 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1566 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1567 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1568 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
aravindsv 0:ba7650f404af 1569 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1570 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1571 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1572 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1573 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1574
aravindsv 0:ba7650f404af 1575 /******************* Bit definition for ADC_JSQR register *******************/
aravindsv 0:ba7650f404af 1576 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
aravindsv 0:ba7650f404af 1577 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1578 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1579 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1580 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1581 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1582 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
aravindsv 0:ba7650f404af 1583 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1584 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1585 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1586 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1587 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1588 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
aravindsv 0:ba7650f404af 1589 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1590 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1591 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1592 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1593 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1594 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
aravindsv 0:ba7650f404af 1595 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1596 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1597 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1598 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1599 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1600 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
aravindsv 0:ba7650f404af 1601 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1602 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1603
aravindsv 0:ba7650f404af 1604 /******************* Bit definition for ADC_JDR1 register *******************/
aravindsv 0:ba7650f404af 1605 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
aravindsv 0:ba7650f404af 1606
aravindsv 0:ba7650f404af 1607 /******************* Bit definition for ADC_JDR2 register *******************/
aravindsv 0:ba7650f404af 1608 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
aravindsv 0:ba7650f404af 1609
aravindsv 0:ba7650f404af 1610 /******************* Bit definition for ADC_JDR3 register *******************/
aravindsv 0:ba7650f404af 1611 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
aravindsv 0:ba7650f404af 1612
aravindsv 0:ba7650f404af 1613 /******************* Bit definition for ADC_JDR4 register *******************/
aravindsv 0:ba7650f404af 1614 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
aravindsv 0:ba7650f404af 1615
aravindsv 0:ba7650f404af 1616 /******************** Bit definition for ADC_DR register ********************/
aravindsv 0:ba7650f404af 1617 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
aravindsv 0:ba7650f404af 1618 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
aravindsv 0:ba7650f404af 1619
aravindsv 0:ba7650f404af 1620 /******************* Bit definition for ADC_CSR register ********************/
aravindsv 0:ba7650f404af 1621 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
aravindsv 0:ba7650f404af 1622 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
aravindsv 0:ba7650f404af 1623 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
aravindsv 0:ba7650f404af 1624 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
aravindsv 0:ba7650f404af 1625 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
aravindsv 0:ba7650f404af 1626 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
aravindsv 0:ba7650f404af 1627 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
aravindsv 0:ba7650f404af 1628 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
aravindsv 0:ba7650f404af 1629 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
aravindsv 0:ba7650f404af 1630 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
aravindsv 0:ba7650f404af 1631 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
aravindsv 0:ba7650f404af 1632 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
aravindsv 0:ba7650f404af 1633 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
aravindsv 0:ba7650f404af 1634 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
aravindsv 0:ba7650f404af 1635 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
aravindsv 0:ba7650f404af 1636 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
aravindsv 0:ba7650f404af 1637 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
aravindsv 0:ba7650f404af 1638 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
aravindsv 0:ba7650f404af 1639
aravindsv 0:ba7650f404af 1640 /******************* Bit definition for ADC_CCR register ********************/
aravindsv 0:ba7650f404af 1641 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
aravindsv 0:ba7650f404af 1642 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1643 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1644 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1645 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1646 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 1647 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
aravindsv 0:ba7650f404af 1648 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1649 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1650 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1651 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 1652 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
aravindsv 0:ba7650f404af 1653 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
aravindsv 0:ba7650f404af 1654 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1655 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1656 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
aravindsv 0:ba7650f404af 1657 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1658 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1659 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
aravindsv 0:ba7650f404af 1660 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
aravindsv 0:ba7650f404af 1661
aravindsv 0:ba7650f404af 1662 /******************* Bit definition for ADC_CDR register ********************/
aravindsv 0:ba7650f404af 1663 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
aravindsv 0:ba7650f404af 1664 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
aravindsv 0:ba7650f404af 1665
aravindsv 0:ba7650f404af 1666 /******************************************************************************/
aravindsv 0:ba7650f404af 1667 /* */
aravindsv 0:ba7650f404af 1668 /* Controller Area Network */
aravindsv 0:ba7650f404af 1669 /* */
aravindsv 0:ba7650f404af 1670 /******************************************************************************/
aravindsv 0:ba7650f404af 1671 /*!<CAN control and status registers */
aravindsv 0:ba7650f404af 1672 /******************* Bit definition for CAN_MCR register ********************/
aravindsv 0:ba7650f404af 1673 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
aravindsv 0:ba7650f404af 1674 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
aravindsv 0:ba7650f404af 1675 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
aravindsv 0:ba7650f404af 1676 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
aravindsv 0:ba7650f404af 1677 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
aravindsv 0:ba7650f404af 1678 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
aravindsv 0:ba7650f404af 1679 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
aravindsv 0:ba7650f404af 1680 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
aravindsv 0:ba7650f404af 1681 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
aravindsv 0:ba7650f404af 1682
aravindsv 0:ba7650f404af 1683 /******************* Bit definition for CAN_MSR register ********************/
aravindsv 0:ba7650f404af 1684 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
aravindsv 0:ba7650f404af 1685 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
aravindsv 0:ba7650f404af 1686 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
aravindsv 0:ba7650f404af 1687 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
aravindsv 0:ba7650f404af 1688 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
aravindsv 0:ba7650f404af 1689 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
aravindsv 0:ba7650f404af 1690 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
aravindsv 0:ba7650f404af 1691 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
aravindsv 0:ba7650f404af 1692 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
aravindsv 0:ba7650f404af 1693
aravindsv 0:ba7650f404af 1694 /******************* Bit definition for CAN_TSR register ********************/
aravindsv 0:ba7650f404af 1695 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
aravindsv 0:ba7650f404af 1696 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
aravindsv 0:ba7650f404af 1697 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
aravindsv 0:ba7650f404af 1698 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
aravindsv 0:ba7650f404af 1699 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
aravindsv 0:ba7650f404af 1700 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
aravindsv 0:ba7650f404af 1701 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
aravindsv 0:ba7650f404af 1702 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
aravindsv 0:ba7650f404af 1703 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
aravindsv 0:ba7650f404af 1704 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
aravindsv 0:ba7650f404af 1705 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
aravindsv 0:ba7650f404af 1706 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
aravindsv 0:ba7650f404af 1707 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
aravindsv 0:ba7650f404af 1708 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
aravindsv 0:ba7650f404af 1709 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
aravindsv 0:ba7650f404af 1710 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
aravindsv 0:ba7650f404af 1711
aravindsv 0:ba7650f404af 1712 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
aravindsv 0:ba7650f404af 1713 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
aravindsv 0:ba7650f404af 1714 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
aravindsv 0:ba7650f404af 1715 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
aravindsv 0:ba7650f404af 1716
aravindsv 0:ba7650f404af 1717 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
aravindsv 0:ba7650f404af 1718 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
aravindsv 0:ba7650f404af 1719 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
aravindsv 0:ba7650f404af 1720 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
aravindsv 0:ba7650f404af 1721
aravindsv 0:ba7650f404af 1722 /******************* Bit definition for CAN_RF0R register *******************/
aravindsv 0:ba7650f404af 1723 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
aravindsv 0:ba7650f404af 1724 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
aravindsv 0:ba7650f404af 1725 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
aravindsv 0:ba7650f404af 1726 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
aravindsv 0:ba7650f404af 1727
aravindsv 0:ba7650f404af 1728 /******************* Bit definition for CAN_RF1R register *******************/
aravindsv 0:ba7650f404af 1729 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
aravindsv 0:ba7650f404af 1730 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
aravindsv 0:ba7650f404af 1731 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
aravindsv 0:ba7650f404af 1732 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
aravindsv 0:ba7650f404af 1733
aravindsv 0:ba7650f404af 1734 /******************** Bit definition for CAN_IER register *******************/
aravindsv 0:ba7650f404af 1735 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
aravindsv 0:ba7650f404af 1736 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
aravindsv 0:ba7650f404af 1737 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
aravindsv 0:ba7650f404af 1738 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
aravindsv 0:ba7650f404af 1739 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
aravindsv 0:ba7650f404af 1740 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
aravindsv 0:ba7650f404af 1741 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
aravindsv 0:ba7650f404af 1742 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
aravindsv 0:ba7650f404af 1743 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
aravindsv 0:ba7650f404af 1744 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
aravindsv 0:ba7650f404af 1745 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
aravindsv 0:ba7650f404af 1746 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
aravindsv 0:ba7650f404af 1747 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
aravindsv 0:ba7650f404af 1748 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
aravindsv 0:ba7650f404af 1749
aravindsv 0:ba7650f404af 1750 /******************** Bit definition for CAN_ESR register *******************/
aravindsv 0:ba7650f404af 1751 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
aravindsv 0:ba7650f404af 1752 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
aravindsv 0:ba7650f404af 1753 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
aravindsv 0:ba7650f404af 1754
aravindsv 0:ba7650f404af 1755 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
aravindsv 0:ba7650f404af 1756 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 1757 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 1758 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 1759
aravindsv 0:ba7650f404af 1760 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
aravindsv 0:ba7650f404af 1761 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
aravindsv 0:ba7650f404af 1762
aravindsv 0:ba7650f404af 1763 /******************* Bit definition for CAN_BTR register ********************/
aravindsv 0:ba7650f404af 1764 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
aravindsv 0:ba7650f404af 1765 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
aravindsv 0:ba7650f404af 1766 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
aravindsv 0:ba7650f404af 1767 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
aravindsv 0:ba7650f404af 1768 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
aravindsv 0:ba7650f404af 1769 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
aravindsv 0:ba7650f404af 1770
aravindsv 0:ba7650f404af 1771 /*!<Mailbox registers */
aravindsv 0:ba7650f404af 1772 /****************** Bit definition for CAN_TI0R register ********************/
aravindsv 0:ba7650f404af 1773 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
aravindsv 0:ba7650f404af 1774 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
aravindsv 0:ba7650f404af 1775 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
aravindsv 0:ba7650f404af 1776 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
aravindsv 0:ba7650f404af 1777 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
aravindsv 0:ba7650f404af 1778
aravindsv 0:ba7650f404af 1779 /****************** Bit definition for CAN_TDT0R register *******************/
aravindsv 0:ba7650f404af 1780 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
aravindsv 0:ba7650f404af 1781 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
aravindsv 0:ba7650f404af 1782 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
aravindsv 0:ba7650f404af 1783
aravindsv 0:ba7650f404af 1784 /****************** Bit definition for CAN_TDL0R register *******************/
aravindsv 0:ba7650f404af 1785 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
aravindsv 0:ba7650f404af 1786 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
aravindsv 0:ba7650f404af 1787 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
aravindsv 0:ba7650f404af 1788 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
aravindsv 0:ba7650f404af 1789
aravindsv 0:ba7650f404af 1790 /****************** Bit definition for CAN_TDH0R register *******************/
aravindsv 0:ba7650f404af 1791 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
aravindsv 0:ba7650f404af 1792 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
aravindsv 0:ba7650f404af 1793 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
aravindsv 0:ba7650f404af 1794 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
aravindsv 0:ba7650f404af 1795
aravindsv 0:ba7650f404af 1796 /******************* Bit definition for CAN_TI1R register *******************/
aravindsv 0:ba7650f404af 1797 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
aravindsv 0:ba7650f404af 1798 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
aravindsv 0:ba7650f404af 1799 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
aravindsv 0:ba7650f404af 1800 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
aravindsv 0:ba7650f404af 1801 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
aravindsv 0:ba7650f404af 1802
aravindsv 0:ba7650f404af 1803 /******************* Bit definition for CAN_TDT1R register ******************/
aravindsv 0:ba7650f404af 1804 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
aravindsv 0:ba7650f404af 1805 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
aravindsv 0:ba7650f404af 1806 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
aravindsv 0:ba7650f404af 1807
aravindsv 0:ba7650f404af 1808 /******************* Bit definition for CAN_TDL1R register ******************/
aravindsv 0:ba7650f404af 1809 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
aravindsv 0:ba7650f404af 1810 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
aravindsv 0:ba7650f404af 1811 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
aravindsv 0:ba7650f404af 1812 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
aravindsv 0:ba7650f404af 1813
aravindsv 0:ba7650f404af 1814 /******************* Bit definition for CAN_TDH1R register ******************/
aravindsv 0:ba7650f404af 1815 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
aravindsv 0:ba7650f404af 1816 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
aravindsv 0:ba7650f404af 1817 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
aravindsv 0:ba7650f404af 1818 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
aravindsv 0:ba7650f404af 1819
aravindsv 0:ba7650f404af 1820 /******************* Bit definition for CAN_TI2R register *******************/
aravindsv 0:ba7650f404af 1821 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
aravindsv 0:ba7650f404af 1822 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
aravindsv 0:ba7650f404af 1823 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
aravindsv 0:ba7650f404af 1824 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
aravindsv 0:ba7650f404af 1825 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
aravindsv 0:ba7650f404af 1826
aravindsv 0:ba7650f404af 1827 /******************* Bit definition for CAN_TDT2R register ******************/
aravindsv 0:ba7650f404af 1828 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
aravindsv 0:ba7650f404af 1829 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
aravindsv 0:ba7650f404af 1830 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
aravindsv 0:ba7650f404af 1831
aravindsv 0:ba7650f404af 1832 /******************* Bit definition for CAN_TDL2R register ******************/
aravindsv 0:ba7650f404af 1833 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
aravindsv 0:ba7650f404af 1834 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
aravindsv 0:ba7650f404af 1835 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
aravindsv 0:ba7650f404af 1836 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
aravindsv 0:ba7650f404af 1837
aravindsv 0:ba7650f404af 1838 /******************* Bit definition for CAN_TDH2R register ******************/
aravindsv 0:ba7650f404af 1839 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
aravindsv 0:ba7650f404af 1840 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
aravindsv 0:ba7650f404af 1841 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
aravindsv 0:ba7650f404af 1842 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
aravindsv 0:ba7650f404af 1843
aravindsv 0:ba7650f404af 1844 /******************* Bit definition for CAN_RI0R register *******************/
aravindsv 0:ba7650f404af 1845 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
aravindsv 0:ba7650f404af 1846 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
aravindsv 0:ba7650f404af 1847 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
aravindsv 0:ba7650f404af 1848 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
aravindsv 0:ba7650f404af 1849
aravindsv 0:ba7650f404af 1850 /******************* Bit definition for CAN_RDT0R register ******************/
aravindsv 0:ba7650f404af 1851 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
aravindsv 0:ba7650f404af 1852 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
aravindsv 0:ba7650f404af 1853 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
aravindsv 0:ba7650f404af 1854
aravindsv 0:ba7650f404af 1855 /******************* Bit definition for CAN_RDL0R register ******************/
aravindsv 0:ba7650f404af 1856 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
aravindsv 0:ba7650f404af 1857 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
aravindsv 0:ba7650f404af 1858 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
aravindsv 0:ba7650f404af 1859 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
aravindsv 0:ba7650f404af 1860
aravindsv 0:ba7650f404af 1861 /******************* Bit definition for CAN_RDH0R register ******************/
aravindsv 0:ba7650f404af 1862 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
aravindsv 0:ba7650f404af 1863 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
aravindsv 0:ba7650f404af 1864 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
aravindsv 0:ba7650f404af 1865 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
aravindsv 0:ba7650f404af 1866
aravindsv 0:ba7650f404af 1867 /******************* Bit definition for CAN_RI1R register *******************/
aravindsv 0:ba7650f404af 1868 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
aravindsv 0:ba7650f404af 1869 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
aravindsv 0:ba7650f404af 1870 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
aravindsv 0:ba7650f404af 1871 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
aravindsv 0:ba7650f404af 1872
aravindsv 0:ba7650f404af 1873 /******************* Bit definition for CAN_RDT1R register ******************/
aravindsv 0:ba7650f404af 1874 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
aravindsv 0:ba7650f404af 1875 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
aravindsv 0:ba7650f404af 1876 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
aravindsv 0:ba7650f404af 1877
aravindsv 0:ba7650f404af 1878 /******************* Bit definition for CAN_RDL1R register ******************/
aravindsv 0:ba7650f404af 1879 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
aravindsv 0:ba7650f404af 1880 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
aravindsv 0:ba7650f404af 1881 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
aravindsv 0:ba7650f404af 1882 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
aravindsv 0:ba7650f404af 1883
aravindsv 0:ba7650f404af 1884 /******************* Bit definition for CAN_RDH1R register ******************/
aravindsv 0:ba7650f404af 1885 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
aravindsv 0:ba7650f404af 1886 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
aravindsv 0:ba7650f404af 1887 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
aravindsv 0:ba7650f404af 1888 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
aravindsv 0:ba7650f404af 1889
aravindsv 0:ba7650f404af 1890 /*!<CAN filter registers */
aravindsv 0:ba7650f404af 1891 /******************* Bit definition for CAN_FMR register ********************/
aravindsv 0:ba7650f404af 1892 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
aravindsv 0:ba7650f404af 1893
aravindsv 0:ba7650f404af 1894 /******************* Bit definition for CAN_FM1R register *******************/
aravindsv 0:ba7650f404af 1895 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
aravindsv 0:ba7650f404af 1896 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
aravindsv 0:ba7650f404af 1897 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
aravindsv 0:ba7650f404af 1898 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
aravindsv 0:ba7650f404af 1899 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
aravindsv 0:ba7650f404af 1900 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
aravindsv 0:ba7650f404af 1901 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
aravindsv 0:ba7650f404af 1902 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
aravindsv 0:ba7650f404af 1903 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
aravindsv 0:ba7650f404af 1904 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
aravindsv 0:ba7650f404af 1905 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
aravindsv 0:ba7650f404af 1906 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
aravindsv 0:ba7650f404af 1907 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
aravindsv 0:ba7650f404af 1908 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
aravindsv 0:ba7650f404af 1909 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
aravindsv 0:ba7650f404af 1910
aravindsv 0:ba7650f404af 1911 /******************* Bit definition for CAN_FS1R register *******************/
aravindsv 0:ba7650f404af 1912 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
aravindsv 0:ba7650f404af 1913 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
aravindsv 0:ba7650f404af 1914 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
aravindsv 0:ba7650f404af 1915 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
aravindsv 0:ba7650f404af 1916 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
aravindsv 0:ba7650f404af 1917 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
aravindsv 0:ba7650f404af 1918 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
aravindsv 0:ba7650f404af 1919 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
aravindsv 0:ba7650f404af 1920 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
aravindsv 0:ba7650f404af 1921 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
aravindsv 0:ba7650f404af 1922 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
aravindsv 0:ba7650f404af 1923 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
aravindsv 0:ba7650f404af 1924 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
aravindsv 0:ba7650f404af 1925 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
aravindsv 0:ba7650f404af 1926 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
aravindsv 0:ba7650f404af 1927
aravindsv 0:ba7650f404af 1928 /****************** Bit definition for CAN_FFA1R register *******************/
aravindsv 0:ba7650f404af 1929 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
aravindsv 0:ba7650f404af 1930 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
aravindsv 0:ba7650f404af 1931 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
aravindsv 0:ba7650f404af 1932 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
aravindsv 0:ba7650f404af 1933 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
aravindsv 0:ba7650f404af 1934 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
aravindsv 0:ba7650f404af 1935 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
aravindsv 0:ba7650f404af 1936 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
aravindsv 0:ba7650f404af 1937 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
aravindsv 0:ba7650f404af 1938 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
aravindsv 0:ba7650f404af 1939 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
aravindsv 0:ba7650f404af 1940 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
aravindsv 0:ba7650f404af 1941 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
aravindsv 0:ba7650f404af 1942 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
aravindsv 0:ba7650f404af 1943 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
aravindsv 0:ba7650f404af 1944
aravindsv 0:ba7650f404af 1945 /******************* Bit definition for CAN_FA1R register *******************/
aravindsv 0:ba7650f404af 1946 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
aravindsv 0:ba7650f404af 1947 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
aravindsv 0:ba7650f404af 1948 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
aravindsv 0:ba7650f404af 1949 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
aravindsv 0:ba7650f404af 1950 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
aravindsv 0:ba7650f404af 1951 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
aravindsv 0:ba7650f404af 1952 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
aravindsv 0:ba7650f404af 1953 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
aravindsv 0:ba7650f404af 1954 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
aravindsv 0:ba7650f404af 1955 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
aravindsv 0:ba7650f404af 1956 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
aravindsv 0:ba7650f404af 1957 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
aravindsv 0:ba7650f404af 1958 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
aravindsv 0:ba7650f404af 1959 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
aravindsv 0:ba7650f404af 1960 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
aravindsv 0:ba7650f404af 1961
aravindsv 0:ba7650f404af 1962 /******************* Bit definition for CAN_F0R1 register *******************/
aravindsv 0:ba7650f404af 1963 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 1964 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 1965 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 1966 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 1967 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 1968 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 1969 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 1970 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 1971 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 1972 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 1973 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 1974 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 1975 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 1976 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 1977 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 1978 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 1979 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 1980 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 1981 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 1982 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 1983 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 1984 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 1985 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 1986 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 1987 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 1988 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 1989 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 1990 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 1991 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 1992 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 1993 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 1994 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 1995
aravindsv 0:ba7650f404af 1996 /******************* Bit definition for CAN_F1R1 register *******************/
aravindsv 0:ba7650f404af 1997 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 1998 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 1999 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2000 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2001 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2002 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2003 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2004 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2005 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2006 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2007 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2008 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2009 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2010 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2011 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2012 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2013 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2014 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2015 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2016 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2017 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2018 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2019 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2020 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2021 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2022 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2023 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2024 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2025 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2026 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2027 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2028 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2029
aravindsv 0:ba7650f404af 2030 /******************* Bit definition for CAN_F2R1 register *******************/
aravindsv 0:ba7650f404af 2031 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2032 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2033 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2034 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2035 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2036 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2037 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2038 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2039 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2040 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2041 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2042 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2043 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2044 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2045 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2046 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2047 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2048 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2049 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2050 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2051 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2052 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2053 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2054 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2055 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2056 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2057 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2058 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2059 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2060 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2061 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2062 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2063
aravindsv 0:ba7650f404af 2064 /******************* Bit definition for CAN_F3R1 register *******************/
aravindsv 0:ba7650f404af 2065 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2066 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2067 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2068 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2069 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2070 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2071 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2072 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2073 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2074 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2075 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2076 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2077 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2078 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2079 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2080 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2081 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2082 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2083 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2084 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2085 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2086 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2087 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2088 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2089 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2090 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2091 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2092 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2093 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2094 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2095 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2096 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2097
aravindsv 0:ba7650f404af 2098 /******************* Bit definition for CAN_F4R1 register *******************/
aravindsv 0:ba7650f404af 2099 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2100 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2101 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2102 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2103 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2104 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2105 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2106 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2107 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2108 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2109 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2110 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2111 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2112 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2113 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2114 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2115 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2116 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2117 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2118 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2119 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2120 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2121 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2122 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2123 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2124 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2125 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2126 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2127 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2128 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2129 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2130 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2131
aravindsv 0:ba7650f404af 2132 /******************* Bit definition for CAN_F5R1 register *******************/
aravindsv 0:ba7650f404af 2133 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2134 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2135 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2136 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2137 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2138 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2139 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2140 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2141 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2142 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2143 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2144 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2145 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2146 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2147 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2148 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2149 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2150 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2151 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2152 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2153 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2154 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2155 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2156 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2157 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2158 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2159 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2160 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2161 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2162 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2163 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2164 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2165
aravindsv 0:ba7650f404af 2166 /******************* Bit definition for CAN_F6R1 register *******************/
aravindsv 0:ba7650f404af 2167 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2168 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2169 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2170 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2171 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2172 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2173 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2174 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2175 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2176 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2177 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2178 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2179 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2180 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2181 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2182 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2183 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2184 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2185 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2186 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2187 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2188 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2189 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2190 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2191 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2192 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2193 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2194 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2195 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2196 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2197 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2198 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2199
aravindsv 0:ba7650f404af 2200 /******************* Bit definition for CAN_F7R1 register *******************/
aravindsv 0:ba7650f404af 2201 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2202 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2203 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2204 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2205 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2206 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2207 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2208 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2209 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2210 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2211 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2212 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2213 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2214 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2215 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2216 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2217 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2218 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2219 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2220 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2221 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2222 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2223 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2224 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2225 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2226 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2227 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2228 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2229 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2230 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2231 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2232 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2233
aravindsv 0:ba7650f404af 2234 /******************* Bit definition for CAN_F8R1 register *******************/
aravindsv 0:ba7650f404af 2235 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2236 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2237 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2238 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2239 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2240 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2241 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2242 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2243 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2244 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2245 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2246 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2247 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2248 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2249 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2250 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2251 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2252 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2253 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2254 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2255 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2256 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2257 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2258 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2259 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2260 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2261 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2262 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2263 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2264 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2265 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2266 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2267
aravindsv 0:ba7650f404af 2268 /******************* Bit definition for CAN_F9R1 register *******************/
aravindsv 0:ba7650f404af 2269 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2270 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2271 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2272 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2273 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2274 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2275 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2276 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2277 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2278 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2279 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2280 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2281 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2282 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2283 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2284 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2285 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2286 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2287 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2288 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2289 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2290 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2291 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2292 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2293 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2294 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2295 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2296 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2297 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2298 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2299 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2300 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2301
aravindsv 0:ba7650f404af 2302 /******************* Bit definition for CAN_F10R1 register ******************/
aravindsv 0:ba7650f404af 2303 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2304 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2305 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2306 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2307 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2308 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2309 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2310 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2311 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2312 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2313 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2314 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2315 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2316 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2317 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2318 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2319 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2320 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2321 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2322 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2323 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2324 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2325 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2326 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2327 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2328 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2329 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2330 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2331 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2332 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2333 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2334 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2335
aravindsv 0:ba7650f404af 2336 /******************* Bit definition for CAN_F11R1 register ******************/
aravindsv 0:ba7650f404af 2337 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2338 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2339 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2340 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2341 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2342 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2343 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2344 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2345 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2346 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2347 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2348 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2349 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2350 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2351 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2352 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2353 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2354 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2355 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2356 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2357 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2358 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2359 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2360 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2361 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2362 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2363 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2364 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2365 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2366 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2367 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2368 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2369
aravindsv 0:ba7650f404af 2370 /******************* Bit definition for CAN_F12R1 register ******************/
aravindsv 0:ba7650f404af 2371 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2372 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2373 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2374 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2375 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2376 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2377 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2378 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2379 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2380 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2381 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2382 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2383 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2384 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2385 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2386 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2387 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2388 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2389 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2390 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2391 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2392 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2393 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2394 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2395 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2396 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2397 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2398 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2399 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2400 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2401 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2402 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2403
aravindsv 0:ba7650f404af 2404 /******************* Bit definition for CAN_F13R1 register ******************/
aravindsv 0:ba7650f404af 2405 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2406 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2407 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2408 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2409 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2410 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2411 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2412 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2413 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2414 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2415 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2416 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2417 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2418 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2419 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2420 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2421 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2422 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2423 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2424 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2425 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2426 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2427 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2428 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2429 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2430 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2431 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2432 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2433 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2434 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2435 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2436 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2437
aravindsv 0:ba7650f404af 2438 /******************* Bit definition for CAN_F0R2 register *******************/
aravindsv 0:ba7650f404af 2439 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2440 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2441 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2442 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2443 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2444 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2445 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2446 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2447 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2448 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2449 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2450 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2451 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2452 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2453 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2454 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2455 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2456 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2457 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2458 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2459 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2460 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2461 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2462 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2463 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2464 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2465 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2466 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2467 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2468 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2469 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2470 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2471
aravindsv 0:ba7650f404af 2472 /******************* Bit definition for CAN_F1R2 register *******************/
aravindsv 0:ba7650f404af 2473 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2474 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2475 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2476 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2477 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2478 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2479 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2480 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2481 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2482 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2483 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2484 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2485 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2486 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2487 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2488 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2489 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2490 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2491 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2492 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2493 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2494 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2495 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2496 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2497 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2498 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2499 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2500 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2501 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2502 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2503 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2504 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2505
aravindsv 0:ba7650f404af 2506 /******************* Bit definition for CAN_F2R2 register *******************/
aravindsv 0:ba7650f404af 2507 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2508 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2509 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2510 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2511 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2512 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2513 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2514 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2515 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2516 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2517 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2518 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2519 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2520 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2521 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2522 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2523 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2524 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2525 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2526 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2527 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2528 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2529 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2530 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2531 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2532 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2533 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2534 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2535 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2536 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2537 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2538 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2539
aravindsv 0:ba7650f404af 2540 /******************* Bit definition for CAN_F3R2 register *******************/
aravindsv 0:ba7650f404af 2541 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2542 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2543 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2544 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2545 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2546 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2547 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2548 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2549 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2550 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2551 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2552 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2553 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2554 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2555 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2556 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2557 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2558 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2559 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2560 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2561 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2562 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2563 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2564 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2565 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2566 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2567 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2568 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2569 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2570 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2571 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2572 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2573
aravindsv 0:ba7650f404af 2574 /******************* Bit definition for CAN_F4R2 register *******************/
aravindsv 0:ba7650f404af 2575 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2576 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2577 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2578 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2579 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2580 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2581 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2582 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2583 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2584 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2585 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2586 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2587 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2588 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2589 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2590 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2591 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2592 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2593 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2594 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2595 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2596 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2597 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2598 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2599 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2600 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2601 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2602 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2603 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2604 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2605 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2606 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2607
aravindsv 0:ba7650f404af 2608 /******************* Bit definition for CAN_F5R2 register *******************/
aravindsv 0:ba7650f404af 2609 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2610 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2611 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2612 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2613 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2614 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2615 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2616 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2617 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2618 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2619 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2620 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2621 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2622 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2623 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2624 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2625 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2626 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2627 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2628 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2629 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2630 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2631 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2632 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2633 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2634 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2635 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2636 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2637 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2638 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2639 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2640 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2641
aravindsv 0:ba7650f404af 2642 /******************* Bit definition for CAN_F6R2 register *******************/
aravindsv 0:ba7650f404af 2643 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2644 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2645 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2646 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2647 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2648 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2649 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2650 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2651 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2652 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2653 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2654 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2655 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2656 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2657 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2658 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2659 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2660 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2661 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2662 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2663 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2664 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2665 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2666 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2667 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2668 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2669 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2670 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2671 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2672 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2673 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2674 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2675
aravindsv 0:ba7650f404af 2676 /******************* Bit definition for CAN_F7R2 register *******************/
aravindsv 0:ba7650f404af 2677 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2678 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2679 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2680 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2681 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2682 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2683 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2684 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2685 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2686 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2687 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2688 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2689 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2690 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2691 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2692 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2693 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2694 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2695 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2696 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2697 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2698 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2699 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2700 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2701 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2702 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2703 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2704 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2705 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2706 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2707 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2708 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2709
aravindsv 0:ba7650f404af 2710 /******************* Bit definition for CAN_F8R2 register *******************/
aravindsv 0:ba7650f404af 2711 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2712 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2713 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2714 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2715 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2716 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2717 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2718 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2719 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2720 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2721 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2722 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2723 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2724 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2725 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2726 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2727 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2728 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2729 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2730 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2731 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2732 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2733 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2734 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2735 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2736 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2737 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2738 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2739 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2740 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2741 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2742 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2743
aravindsv 0:ba7650f404af 2744 /******************* Bit definition for CAN_F9R2 register *******************/
aravindsv 0:ba7650f404af 2745 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2746 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2747 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2748 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2749 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2750 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2751 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2752 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2753 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2754 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2755 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2756 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2757 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2758 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2759 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2760 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2761 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2762 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2763 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2764 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2765 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2766 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2767 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2768 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2769 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2770 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2771 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2772 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2773 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2774 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2775 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2776 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2777
aravindsv 0:ba7650f404af 2778 /******************* Bit definition for CAN_F10R2 register ******************/
aravindsv 0:ba7650f404af 2779 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2780 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2781 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2782 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2783 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2784 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2785 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2786 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2787 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2788 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2789 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2790 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2791 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2792 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2793 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2794 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2795 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2796 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2797 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2798 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2799 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2800 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2801 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2802 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2803 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2804 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2805 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2806 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2807 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2808 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2809 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2810 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2811
aravindsv 0:ba7650f404af 2812 /******************* Bit definition for CAN_F11R2 register ******************/
aravindsv 0:ba7650f404af 2813 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2814 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2815 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2816 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2817 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2818 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2819 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2820 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2821 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2822 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2823 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2824 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2825 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2826 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2827 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2828 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2829 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2830 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2831 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2832 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2833 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2834 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2835 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2836 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2837 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2838 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2839 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2840 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2841 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2842 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2843 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2844 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2845
aravindsv 0:ba7650f404af 2846 /******************* Bit definition for CAN_F12R2 register ******************/
aravindsv 0:ba7650f404af 2847 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2848 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2849 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2850 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2851 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2852 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2853 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2854 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2855 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2856 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2857 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2858 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2859 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2860 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2861 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2862 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2863 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2864 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2865 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2866 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2867 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2868 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2869 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2870 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2871 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2872 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2873 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2874 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2875 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2876 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2877 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2878 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2879
aravindsv 0:ba7650f404af 2880 /******************* Bit definition for CAN_F13R2 register ******************/
aravindsv 0:ba7650f404af 2881 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
aravindsv 0:ba7650f404af 2882 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
aravindsv 0:ba7650f404af 2883 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
aravindsv 0:ba7650f404af 2884 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
aravindsv 0:ba7650f404af 2885 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
aravindsv 0:ba7650f404af 2886 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
aravindsv 0:ba7650f404af 2887 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
aravindsv 0:ba7650f404af 2888 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
aravindsv 0:ba7650f404af 2889 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
aravindsv 0:ba7650f404af 2890 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
aravindsv 0:ba7650f404af 2891 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
aravindsv 0:ba7650f404af 2892 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
aravindsv 0:ba7650f404af 2893 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
aravindsv 0:ba7650f404af 2894 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
aravindsv 0:ba7650f404af 2895 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
aravindsv 0:ba7650f404af 2896 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
aravindsv 0:ba7650f404af 2897 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
aravindsv 0:ba7650f404af 2898 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
aravindsv 0:ba7650f404af 2899 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
aravindsv 0:ba7650f404af 2900 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
aravindsv 0:ba7650f404af 2901 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
aravindsv 0:ba7650f404af 2902 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
aravindsv 0:ba7650f404af 2903 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
aravindsv 0:ba7650f404af 2904 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
aravindsv 0:ba7650f404af 2905 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
aravindsv 0:ba7650f404af 2906 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
aravindsv 0:ba7650f404af 2907 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
aravindsv 0:ba7650f404af 2908 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
aravindsv 0:ba7650f404af 2909 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
aravindsv 0:ba7650f404af 2910 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
aravindsv 0:ba7650f404af 2911 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
aravindsv 0:ba7650f404af 2912 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
aravindsv 0:ba7650f404af 2913
aravindsv 0:ba7650f404af 2914 /******************************************************************************/
aravindsv 0:ba7650f404af 2915 /* */
aravindsv 0:ba7650f404af 2916 /* CRC calculation unit */
aravindsv 0:ba7650f404af 2917 /* */
aravindsv 0:ba7650f404af 2918 /******************************************************************************/
aravindsv 0:ba7650f404af 2919 /******************* Bit definition for CRC_DR register *********************/
aravindsv 0:ba7650f404af 2920 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
aravindsv 0:ba7650f404af 2921
aravindsv 0:ba7650f404af 2922
aravindsv 0:ba7650f404af 2923 /******************* Bit definition for CRC_IDR register ********************/
aravindsv 0:ba7650f404af 2924 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
aravindsv 0:ba7650f404af 2925
aravindsv 0:ba7650f404af 2926
aravindsv 0:ba7650f404af 2927 /******************** Bit definition for CRC_CR register ********************/
aravindsv 0:ba7650f404af 2928 #define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */
aravindsv 0:ba7650f404af 2929
aravindsv 0:ba7650f404af 2930 /******************************************************************************/
aravindsv 0:ba7650f404af 2931 /* */
aravindsv 0:ba7650f404af 2932 /* Crypto Processor */
aravindsv 0:ba7650f404af 2933 /* */
aravindsv 0:ba7650f404af 2934 /******************************************************************************/
aravindsv 0:ba7650f404af 2935 /******************* Bits definition for CRYP_CR register ********************/
aravindsv 0:ba7650f404af 2936 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 2937
aravindsv 0:ba7650f404af 2938 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
aravindsv 0:ba7650f404af 2939 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 2940 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 2941 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 2942 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
aravindsv 0:ba7650f404af 2943 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 2944 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 2945 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
aravindsv 0:ba7650f404af 2946 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 2947 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
aravindsv 0:ba7650f404af 2948 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
aravindsv 0:ba7650f404af 2949 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
aravindsv 0:ba7650f404af 2950
aravindsv 0:ba7650f404af 2951 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
aravindsv 0:ba7650f404af 2952 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 2953 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 2954 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
aravindsv 0:ba7650f404af 2955 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 2956 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 2957 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 2958 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 2959
aravindsv 0:ba7650f404af 2960 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
aravindsv 0:ba7650f404af 2961 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 2962 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 2963 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 2964
aravindsv 0:ba7650f404af 2965 /****************** Bits definition for CRYP_SR register *********************/
aravindsv 0:ba7650f404af 2966 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 2967 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 2968 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 2969 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 2970 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 2971 /****************** Bits definition for CRYP_DMACR register ******************/
aravindsv 0:ba7650f404af 2972 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 2973 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 2974 /***************** Bits definition for CRYP_IMSCR register ******************/
aravindsv 0:ba7650f404af 2975 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 2976 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 2977 /****************** Bits definition for CRYP_RISR register *******************/
aravindsv 0:ba7650f404af 2978 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 2979 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 2980 /****************** Bits definition for CRYP_MISR register *******************/
aravindsv 0:ba7650f404af 2981 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 2982 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 2983
aravindsv 0:ba7650f404af 2984 /******************************************************************************/
aravindsv 0:ba7650f404af 2985 /* */
aravindsv 0:ba7650f404af 2986 /* Digital to Analog Converter */
aravindsv 0:ba7650f404af 2987 /* */
aravindsv 0:ba7650f404af 2988 /******************************************************************************/
aravindsv 0:ba7650f404af 2989 /******************** Bit definition for DAC_CR register ********************/
aravindsv 0:ba7650f404af 2990 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
aravindsv 0:ba7650f404af 2991 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
aravindsv 0:ba7650f404af 2992 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
aravindsv 0:ba7650f404af 2993
aravindsv 0:ba7650f404af 2994 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
aravindsv 0:ba7650f404af 2995 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
aravindsv 0:ba7650f404af 2996 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
aravindsv 0:ba7650f404af 2997 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
aravindsv 0:ba7650f404af 2998
aravindsv 0:ba7650f404af 2999 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
aravindsv 0:ba7650f404af 3000 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3001 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3002
aravindsv 0:ba7650f404af 3003 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
aravindsv 0:ba7650f404af 3004 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3005 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3006 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3007 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3008
aravindsv 0:ba7650f404af 3009 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
aravindsv 0:ba7650f404af 3010 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
aravindsv 0:ba7650f404af 3011 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
aravindsv 0:ba7650f404af 3012 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
aravindsv 0:ba7650f404af 3013
aravindsv 0:ba7650f404af 3014 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
aravindsv 0:ba7650f404af 3015 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3016 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3017 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3018
aravindsv 0:ba7650f404af 3019 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
aravindsv 0:ba7650f404af 3020 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3021 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3022
aravindsv 0:ba7650f404af 3023 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
aravindsv 0:ba7650f404af 3024 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3025 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3026 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3027 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3028
aravindsv 0:ba7650f404af 3029 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
aravindsv 0:ba7650f404af 3030
aravindsv 0:ba7650f404af 3031 /***************** Bit definition for DAC_SWTRIGR register ******************/
aravindsv 0:ba7650f404af 3032 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
aravindsv 0:ba7650f404af 3033 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
aravindsv 0:ba7650f404af 3034
aravindsv 0:ba7650f404af 3035 /***************** Bit definition for DAC_DHR12R1 register ******************/
aravindsv 0:ba7650f404af 3036 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
aravindsv 0:ba7650f404af 3037
aravindsv 0:ba7650f404af 3038 /***************** Bit definition for DAC_DHR12L1 register ******************/
aravindsv 0:ba7650f404af 3039 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
aravindsv 0:ba7650f404af 3040
aravindsv 0:ba7650f404af 3041 /****************** Bit definition for DAC_DHR8R1 register ******************/
aravindsv 0:ba7650f404af 3042 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
aravindsv 0:ba7650f404af 3043
aravindsv 0:ba7650f404af 3044 /***************** Bit definition for DAC_DHR12R2 register ******************/
aravindsv 0:ba7650f404af 3045 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
aravindsv 0:ba7650f404af 3046
aravindsv 0:ba7650f404af 3047 /***************** Bit definition for DAC_DHR12L2 register ******************/
aravindsv 0:ba7650f404af 3048 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
aravindsv 0:ba7650f404af 3049
aravindsv 0:ba7650f404af 3050 /****************** Bit definition for DAC_DHR8R2 register ******************/
aravindsv 0:ba7650f404af 3051 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
aravindsv 0:ba7650f404af 3052
aravindsv 0:ba7650f404af 3053 /***************** Bit definition for DAC_DHR12RD register ******************/
aravindsv 0:ba7650f404af 3054 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
aravindsv 0:ba7650f404af 3055 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
aravindsv 0:ba7650f404af 3056
aravindsv 0:ba7650f404af 3057 /***************** Bit definition for DAC_DHR12LD register ******************/
aravindsv 0:ba7650f404af 3058 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
aravindsv 0:ba7650f404af 3059 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
aravindsv 0:ba7650f404af 3060
aravindsv 0:ba7650f404af 3061 /****************** Bit definition for DAC_DHR8RD register ******************/
aravindsv 0:ba7650f404af 3062 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
aravindsv 0:ba7650f404af 3063 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
aravindsv 0:ba7650f404af 3064
aravindsv 0:ba7650f404af 3065 /******************* Bit definition for DAC_DOR1 register *******************/
aravindsv 0:ba7650f404af 3066 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
aravindsv 0:ba7650f404af 3067
aravindsv 0:ba7650f404af 3068 /******************* Bit definition for DAC_DOR2 register *******************/
aravindsv 0:ba7650f404af 3069 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
aravindsv 0:ba7650f404af 3070
aravindsv 0:ba7650f404af 3071 /******************** Bit definition for DAC_SR register ********************/
aravindsv 0:ba7650f404af 3072 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
aravindsv 0:ba7650f404af 3073 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
aravindsv 0:ba7650f404af 3074
aravindsv 0:ba7650f404af 3075 /******************************************************************************/
aravindsv 0:ba7650f404af 3076 /* */
aravindsv 0:ba7650f404af 3077 /* Debug MCU */
aravindsv 0:ba7650f404af 3078 /* */
aravindsv 0:ba7650f404af 3079 /******************************************************************************/
aravindsv 0:ba7650f404af 3080
aravindsv 0:ba7650f404af 3081 /******************************************************************************/
aravindsv 0:ba7650f404af 3082 /* */
aravindsv 0:ba7650f404af 3083 /* DCMI */
aravindsv 0:ba7650f404af 3084 /* */
aravindsv 0:ba7650f404af 3085 /******************************************************************************/
aravindsv 0:ba7650f404af 3086 /******************** Bits definition for DCMI_CR register ******************/
aravindsv 0:ba7650f404af 3087 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3088 #define DCMI_CR_CM ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3089 #define DCMI_CR_CROP ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3090 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3091 #define DCMI_CR_ESS ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3092 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3093 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3094 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 3095 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3096 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3097 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3098 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3099 #define DCMI_CR_CRE ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 3100 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 3101
aravindsv 0:ba7650f404af 3102 /******************** Bits definition for DCMI_SR register ******************/
aravindsv 0:ba7650f404af 3103 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3104 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3105 #define DCMI_SR_FNE ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3106
aravindsv 0:ba7650f404af 3107 /******************** Bits definition for DCMI_RISR register ****************/
aravindsv 0:ba7650f404af 3108 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3109 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3110 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3111 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3112 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3113
aravindsv 0:ba7650f404af 3114 /******************** Bits definition for DCMI_IER register *****************/
aravindsv 0:ba7650f404af 3115 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3116 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3117 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3118 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3119 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3120
aravindsv 0:ba7650f404af 3121 /******************** Bits definition for DCMI_MISR register ****************/
aravindsv 0:ba7650f404af 3122 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3123 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3124 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3125 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3126 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3127
aravindsv 0:ba7650f404af 3128 /******************** Bits definition for DCMI_ICR register *****************/
aravindsv 0:ba7650f404af 3129 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3130 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3131 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3132 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3133 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3134
aravindsv 0:ba7650f404af 3135 /******************************************************************************/
aravindsv 0:ba7650f404af 3136 /* */
aravindsv 0:ba7650f404af 3137 /* DMA Controller */
aravindsv 0:ba7650f404af 3138 /* */
aravindsv 0:ba7650f404af 3139 /******************************************************************************/
aravindsv 0:ba7650f404af 3140 /******************** Bits definition for DMA_SxCR register *****************/
aravindsv 0:ba7650f404af 3141 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
aravindsv 0:ba7650f404af 3142 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 3143 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 3144 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 3145 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
aravindsv 0:ba7650f404af 3146 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 3147 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 3148 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
aravindsv 0:ba7650f404af 3149 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 3150 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 3151 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 3152 #define DMA_SxCR_CT ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 3153 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 3154 #define DMA_SxCR_PL ((uint32_t)0x00030000)
aravindsv 0:ba7650f404af 3155 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3156 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 3157 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 3158 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
aravindsv 0:ba7650f404af 3159 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 3160 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 3161 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
aravindsv 0:ba7650f404af 3162 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3163 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 3164 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3165 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3166 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3167 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
aravindsv 0:ba7650f404af 3168 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3169 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 3170 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3171 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3172 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3173 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3174 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3175 #define DMA_SxCR_EN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3176
aravindsv 0:ba7650f404af 3177 /******************** Bits definition for DMA_SxCNDTR register **************/
aravindsv 0:ba7650f404af 3178 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
aravindsv 0:ba7650f404af 3179 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3180 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3181 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3182 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3183 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3184 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3185 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3186 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 3187 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3188 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3189 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3190 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3191 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 3192 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 3193 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 3194 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 3195
aravindsv 0:ba7650f404af 3196 /******************** Bits definition for DMA_SxFCR register ****************/
aravindsv 0:ba7650f404af 3197 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 3198 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
aravindsv 0:ba7650f404af 3199 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3200 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3201 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3202 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3203 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
aravindsv 0:ba7650f404af 3204 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3205 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3206
aravindsv 0:ba7650f404af 3207 /******************** Bits definition for DMA_LISR register *****************/
aravindsv 0:ba7650f404af 3208 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 3209 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 3210 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 3211 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 3212 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 3213 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 3214 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 3215 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 3216 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 3217 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3218 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3219 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3220 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3221 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3222 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3223 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3224 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3225 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3226 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3227 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3228
aravindsv 0:ba7650f404af 3229 /******************** Bits definition for DMA_HISR register *****************/
aravindsv 0:ba7650f404af 3230 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 3231 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 3232 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 3233 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 3234 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 3235 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 3236 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 3237 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 3238 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 3239 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3240 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3241 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3242 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3243 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3244 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3245 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3246 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3247 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3248 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3249 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3250
aravindsv 0:ba7650f404af 3251 /******************** Bits definition for DMA_LIFCR register ****************/
aravindsv 0:ba7650f404af 3252 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 3253 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 3254 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 3255 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 3256 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 3257 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 3258 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 3259 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 3260 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 3261 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3262 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3263 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3264 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3265 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3266 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3267 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3268 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3269 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3270 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3271 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3272
aravindsv 0:ba7650f404af 3273 /******************** Bits definition for DMA_HIFCR register ****************/
aravindsv 0:ba7650f404af 3274 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 3275 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 3276 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 3277 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 3278 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 3279 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 3280 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 3281 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 3282 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 3283 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3284 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3285 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3286 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3287 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3288 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3289 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3290 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3291 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3292 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3293 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3294
aravindsv 0:ba7650f404af 3295
aravindsv 0:ba7650f404af 3296 /******************************************************************************/
aravindsv 0:ba7650f404af 3297 /* */
aravindsv 0:ba7650f404af 3298 /* External Interrupt/Event Controller */
aravindsv 0:ba7650f404af 3299 /* */
aravindsv 0:ba7650f404af 3300 /******************************************************************************/
aravindsv 0:ba7650f404af 3301 /******************* Bit definition for EXTI_IMR register *******************/
aravindsv 0:ba7650f404af 3302 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
aravindsv 0:ba7650f404af 3303 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
aravindsv 0:ba7650f404af 3304 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
aravindsv 0:ba7650f404af 3305 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
aravindsv 0:ba7650f404af 3306 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
aravindsv 0:ba7650f404af 3307 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
aravindsv 0:ba7650f404af 3308 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
aravindsv 0:ba7650f404af 3309 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
aravindsv 0:ba7650f404af 3310 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
aravindsv 0:ba7650f404af 3311 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
aravindsv 0:ba7650f404af 3312 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
aravindsv 0:ba7650f404af 3313 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
aravindsv 0:ba7650f404af 3314 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
aravindsv 0:ba7650f404af 3315 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
aravindsv 0:ba7650f404af 3316 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
aravindsv 0:ba7650f404af 3317 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
aravindsv 0:ba7650f404af 3318 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
aravindsv 0:ba7650f404af 3319 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
aravindsv 0:ba7650f404af 3320 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
aravindsv 0:ba7650f404af 3321 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
aravindsv 0:ba7650f404af 3322
aravindsv 0:ba7650f404af 3323 /******************* Bit definition for EXTI_EMR register *******************/
aravindsv 0:ba7650f404af 3324 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
aravindsv 0:ba7650f404af 3325 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
aravindsv 0:ba7650f404af 3326 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
aravindsv 0:ba7650f404af 3327 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
aravindsv 0:ba7650f404af 3328 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
aravindsv 0:ba7650f404af 3329 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
aravindsv 0:ba7650f404af 3330 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
aravindsv 0:ba7650f404af 3331 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
aravindsv 0:ba7650f404af 3332 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
aravindsv 0:ba7650f404af 3333 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
aravindsv 0:ba7650f404af 3334 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
aravindsv 0:ba7650f404af 3335 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
aravindsv 0:ba7650f404af 3336 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
aravindsv 0:ba7650f404af 3337 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
aravindsv 0:ba7650f404af 3338 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
aravindsv 0:ba7650f404af 3339 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
aravindsv 0:ba7650f404af 3340 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
aravindsv 0:ba7650f404af 3341 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
aravindsv 0:ba7650f404af 3342 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
aravindsv 0:ba7650f404af 3343 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
aravindsv 0:ba7650f404af 3344
aravindsv 0:ba7650f404af 3345 /****************** Bit definition for EXTI_RTSR register *******************/
aravindsv 0:ba7650f404af 3346 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
aravindsv 0:ba7650f404af 3347 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
aravindsv 0:ba7650f404af 3348 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
aravindsv 0:ba7650f404af 3349 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
aravindsv 0:ba7650f404af 3350 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
aravindsv 0:ba7650f404af 3351 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
aravindsv 0:ba7650f404af 3352 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
aravindsv 0:ba7650f404af 3353 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
aravindsv 0:ba7650f404af 3354 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
aravindsv 0:ba7650f404af 3355 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
aravindsv 0:ba7650f404af 3356 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
aravindsv 0:ba7650f404af 3357 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
aravindsv 0:ba7650f404af 3358 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
aravindsv 0:ba7650f404af 3359 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
aravindsv 0:ba7650f404af 3360 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
aravindsv 0:ba7650f404af 3361 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
aravindsv 0:ba7650f404af 3362 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
aravindsv 0:ba7650f404af 3363 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
aravindsv 0:ba7650f404af 3364 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
aravindsv 0:ba7650f404af 3365 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
aravindsv 0:ba7650f404af 3366
aravindsv 0:ba7650f404af 3367 /****************** Bit definition for EXTI_FTSR register *******************/
aravindsv 0:ba7650f404af 3368 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
aravindsv 0:ba7650f404af 3369 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
aravindsv 0:ba7650f404af 3370 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
aravindsv 0:ba7650f404af 3371 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
aravindsv 0:ba7650f404af 3372 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
aravindsv 0:ba7650f404af 3373 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
aravindsv 0:ba7650f404af 3374 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
aravindsv 0:ba7650f404af 3375 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
aravindsv 0:ba7650f404af 3376 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
aravindsv 0:ba7650f404af 3377 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
aravindsv 0:ba7650f404af 3378 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
aravindsv 0:ba7650f404af 3379 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
aravindsv 0:ba7650f404af 3380 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
aravindsv 0:ba7650f404af 3381 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
aravindsv 0:ba7650f404af 3382 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
aravindsv 0:ba7650f404af 3383 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
aravindsv 0:ba7650f404af 3384 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
aravindsv 0:ba7650f404af 3385 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
aravindsv 0:ba7650f404af 3386 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
aravindsv 0:ba7650f404af 3387 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
aravindsv 0:ba7650f404af 3388
aravindsv 0:ba7650f404af 3389 /****************** Bit definition for EXTI_SWIER register ******************/
aravindsv 0:ba7650f404af 3390 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
aravindsv 0:ba7650f404af 3391 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
aravindsv 0:ba7650f404af 3392 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
aravindsv 0:ba7650f404af 3393 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
aravindsv 0:ba7650f404af 3394 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
aravindsv 0:ba7650f404af 3395 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
aravindsv 0:ba7650f404af 3396 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
aravindsv 0:ba7650f404af 3397 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
aravindsv 0:ba7650f404af 3398 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
aravindsv 0:ba7650f404af 3399 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
aravindsv 0:ba7650f404af 3400 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
aravindsv 0:ba7650f404af 3401 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
aravindsv 0:ba7650f404af 3402 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
aravindsv 0:ba7650f404af 3403 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
aravindsv 0:ba7650f404af 3404 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
aravindsv 0:ba7650f404af 3405 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
aravindsv 0:ba7650f404af 3406 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
aravindsv 0:ba7650f404af 3407 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
aravindsv 0:ba7650f404af 3408 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
aravindsv 0:ba7650f404af 3409 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
aravindsv 0:ba7650f404af 3410
aravindsv 0:ba7650f404af 3411 /******************* Bit definition for EXTI_PR register ********************/
aravindsv 0:ba7650f404af 3412 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
aravindsv 0:ba7650f404af 3413 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
aravindsv 0:ba7650f404af 3414 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
aravindsv 0:ba7650f404af 3415 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
aravindsv 0:ba7650f404af 3416 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
aravindsv 0:ba7650f404af 3417 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
aravindsv 0:ba7650f404af 3418 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
aravindsv 0:ba7650f404af 3419 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
aravindsv 0:ba7650f404af 3420 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
aravindsv 0:ba7650f404af 3421 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
aravindsv 0:ba7650f404af 3422 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
aravindsv 0:ba7650f404af 3423 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
aravindsv 0:ba7650f404af 3424 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
aravindsv 0:ba7650f404af 3425 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
aravindsv 0:ba7650f404af 3426 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
aravindsv 0:ba7650f404af 3427 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
aravindsv 0:ba7650f404af 3428 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
aravindsv 0:ba7650f404af 3429 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
aravindsv 0:ba7650f404af 3430 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
aravindsv 0:ba7650f404af 3431 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
aravindsv 0:ba7650f404af 3432
aravindsv 0:ba7650f404af 3433 /******************************************************************************/
aravindsv 0:ba7650f404af 3434 /* */
aravindsv 0:ba7650f404af 3435 /* FLASH */
aravindsv 0:ba7650f404af 3436 /* */
aravindsv 0:ba7650f404af 3437 /******************************************************************************/
aravindsv 0:ba7650f404af 3438 /******************* Bits definition for FLASH_ACR register *****************/
aravindsv 0:ba7650f404af 3439 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
aravindsv 0:ba7650f404af 3440 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
aravindsv 0:ba7650f404af 3441 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3442 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3443 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
aravindsv 0:ba7650f404af 3444 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3445 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
aravindsv 0:ba7650f404af 3446 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
aravindsv 0:ba7650f404af 3447 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
aravindsv 0:ba7650f404af 3448
aravindsv 0:ba7650f404af 3449 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3450 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3451 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3452 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3453 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 3454 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
aravindsv 0:ba7650f404af 3455 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
aravindsv 0:ba7650f404af 3456
aravindsv 0:ba7650f404af 3457 /******************* Bits definition for FLASH_SR register ******************/
aravindsv 0:ba7650f404af 3458 #define FLASH_SR_EOP ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3459 #define FLASH_SR_SOP ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3460 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3461 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3462 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3463 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 3464 #define FLASH_SR_BSY ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3465
aravindsv 0:ba7650f404af 3466 /******************* Bits definition for FLASH_CR register ******************/
aravindsv 0:ba7650f404af 3467 #define FLASH_CR_PG ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3468 #define FLASH_CR_SER ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3469 #define FLASH_CR_MER ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3470 #define FLASH_CR_MER1 FLASH_CR_MER
aravindsv 0:ba7650f404af 3471 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
aravindsv 0:ba7650f404af 3472 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3473 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 3474 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3475 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3476 #define FLASH_CR_SNB_4 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3477 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
aravindsv 0:ba7650f404af 3478 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3479 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3480 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 3481 #define FLASH_CR_STRT ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3482 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 3483 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 3484
aravindsv 0:ba7650f404af 3485 /******************* Bits definition for FLASH_OPTCR register ***************/
aravindsv 0:ba7650f404af 3486 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 3487 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 3488 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 3489 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 3490 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
aravindsv 0:ba7650f404af 3491 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 3492 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 3493 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 3494 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
aravindsv 0:ba7650f404af 3495 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 3496 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 3497 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 3498 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 3499 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 3500 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 3501 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 3502 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 3503 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
aravindsv 0:ba7650f404af 3504 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3505 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 3506 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 3507 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 3508 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 3509 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 3510 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 3511 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 3512 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 3513 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 3514 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 3515 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 3516
aravindsv 0:ba7650f404af 3517 /****************** Bits definition for FLASH_OPTCR1 register ***************/
aravindsv 0:ba7650f404af 3518 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
aravindsv 0:ba7650f404af 3519 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 3520 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 3521 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 3522 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 3523 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 3524 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 3525 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 3526 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 3527 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 3528 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 3529 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 3530 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 3531
aravindsv 0:ba7650f404af 3532
aravindsv 0:ba7650f404af 3533 /******************************************************************************/
aravindsv 0:ba7650f404af 3534 /* */
aravindsv 0:ba7650f404af 3535 /* Flexible Static Memory Controller */
aravindsv 0:ba7650f404af 3536 /* */
aravindsv 0:ba7650f404af 3537 /******************************************************************************/
aravindsv 0:ba7650f404af 3538 /****************** Bit definition for FSMC_BCR1 register *******************/
aravindsv 0:ba7650f404af 3539 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
aravindsv 0:ba7650f404af 3540 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
aravindsv 0:ba7650f404af 3541
aravindsv 0:ba7650f404af 3542 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
aravindsv 0:ba7650f404af 3543 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3544 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3545
aravindsv 0:ba7650f404af 3546 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
aravindsv 0:ba7650f404af 3547 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3548 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3549
aravindsv 0:ba7650f404af 3550 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
aravindsv 0:ba7650f404af 3551 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
aravindsv 0:ba7650f404af 3552 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
aravindsv 0:ba7650f404af 3553 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
aravindsv 0:ba7650f404af 3554 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
aravindsv 0:ba7650f404af 3555 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
aravindsv 0:ba7650f404af 3556 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
aravindsv 0:ba7650f404af 3557 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
aravindsv 0:ba7650f404af 3558 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
aravindsv 0:ba7650f404af 3559 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
aravindsv 0:ba7650f404af 3560
aravindsv 0:ba7650f404af 3561 /****************** Bit definition for FSMC_BCR2 register *******************/
aravindsv 0:ba7650f404af 3562 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
aravindsv 0:ba7650f404af 3563 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
aravindsv 0:ba7650f404af 3564
aravindsv 0:ba7650f404af 3565 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
aravindsv 0:ba7650f404af 3566 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3567 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3568
aravindsv 0:ba7650f404af 3569 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
aravindsv 0:ba7650f404af 3570 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3571 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3572
aravindsv 0:ba7650f404af 3573 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
aravindsv 0:ba7650f404af 3574 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
aravindsv 0:ba7650f404af 3575 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
aravindsv 0:ba7650f404af 3576 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
aravindsv 0:ba7650f404af 3577 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
aravindsv 0:ba7650f404af 3578 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
aravindsv 0:ba7650f404af 3579 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
aravindsv 0:ba7650f404af 3580 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
aravindsv 0:ba7650f404af 3581 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
aravindsv 0:ba7650f404af 3582 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
aravindsv 0:ba7650f404af 3583
aravindsv 0:ba7650f404af 3584 /****************** Bit definition for FSMC_BCR3 register *******************/
aravindsv 0:ba7650f404af 3585 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
aravindsv 0:ba7650f404af 3586 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
aravindsv 0:ba7650f404af 3587
aravindsv 0:ba7650f404af 3588 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
aravindsv 0:ba7650f404af 3589 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3590 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3591
aravindsv 0:ba7650f404af 3592 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
aravindsv 0:ba7650f404af 3593 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3594 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3595
aravindsv 0:ba7650f404af 3596 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
aravindsv 0:ba7650f404af 3597 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
aravindsv 0:ba7650f404af 3598 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
aravindsv 0:ba7650f404af 3599 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
aravindsv 0:ba7650f404af 3600 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
aravindsv 0:ba7650f404af 3601 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
aravindsv 0:ba7650f404af 3602 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
aravindsv 0:ba7650f404af 3603 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
aravindsv 0:ba7650f404af 3604 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
aravindsv 0:ba7650f404af 3605 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
aravindsv 0:ba7650f404af 3606
aravindsv 0:ba7650f404af 3607 /****************** Bit definition for FSMC_BCR4 register *******************/
aravindsv 0:ba7650f404af 3608 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
aravindsv 0:ba7650f404af 3609 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
aravindsv 0:ba7650f404af 3610
aravindsv 0:ba7650f404af 3611 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
aravindsv 0:ba7650f404af 3612 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3613 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3614
aravindsv 0:ba7650f404af 3615 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
aravindsv 0:ba7650f404af 3616 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3617 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3618
aravindsv 0:ba7650f404af 3619 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
aravindsv 0:ba7650f404af 3620 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
aravindsv 0:ba7650f404af 3621 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
aravindsv 0:ba7650f404af 3622 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
aravindsv 0:ba7650f404af 3623 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
aravindsv 0:ba7650f404af 3624 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
aravindsv 0:ba7650f404af 3625 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
aravindsv 0:ba7650f404af 3626 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
aravindsv 0:ba7650f404af 3627 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
aravindsv 0:ba7650f404af 3628 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
aravindsv 0:ba7650f404af 3629
aravindsv 0:ba7650f404af 3630 /****************** Bit definition for FSMC_BTR1 register ******************/
aravindsv 0:ba7650f404af 3631 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
aravindsv 0:ba7650f404af 3632 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3633 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3634 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3635 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3636
aravindsv 0:ba7650f404af 3637 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
aravindsv 0:ba7650f404af 3638 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3639 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3640 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3641 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3642
aravindsv 0:ba7650f404af 3643 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
aravindsv 0:ba7650f404af 3644 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3645 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3646 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3647 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3648
aravindsv 0:ba7650f404af 3649 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
aravindsv 0:ba7650f404af 3650 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3651 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3652 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3653 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3654
aravindsv 0:ba7650f404af 3655 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
aravindsv 0:ba7650f404af 3656 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3657 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3658 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3659 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3660
aravindsv 0:ba7650f404af 3661 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
aravindsv 0:ba7650f404af 3662 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3663 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3664 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3665 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3666
aravindsv 0:ba7650f404af 3667 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
aravindsv 0:ba7650f404af 3668 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3669 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3670
aravindsv 0:ba7650f404af 3671 /****************** Bit definition for FSMC_BTR2 register *******************/
aravindsv 0:ba7650f404af 3672 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
aravindsv 0:ba7650f404af 3673 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3674 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3675 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3676 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3677
aravindsv 0:ba7650f404af 3678 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
aravindsv 0:ba7650f404af 3679 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3680 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3681 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3682 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3683
aravindsv 0:ba7650f404af 3684 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
aravindsv 0:ba7650f404af 3685 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3686 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3687 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3688 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3689
aravindsv 0:ba7650f404af 3690 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
aravindsv 0:ba7650f404af 3691 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3692 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3693 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3694 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3695
aravindsv 0:ba7650f404af 3696 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
aravindsv 0:ba7650f404af 3697 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3698 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3699 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3700 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3701
aravindsv 0:ba7650f404af 3702 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
aravindsv 0:ba7650f404af 3703 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3704 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3705 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3706 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3707
aravindsv 0:ba7650f404af 3708 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
aravindsv 0:ba7650f404af 3709 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3710 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3711
aravindsv 0:ba7650f404af 3712 /******************* Bit definition for FSMC_BTR3 register *******************/
aravindsv 0:ba7650f404af 3713 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
aravindsv 0:ba7650f404af 3714 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3715 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3716 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3717 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3718
aravindsv 0:ba7650f404af 3719 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
aravindsv 0:ba7650f404af 3720 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3721 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3722 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3723 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3724
aravindsv 0:ba7650f404af 3725 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
aravindsv 0:ba7650f404af 3726 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3727 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3728 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3729 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3730
aravindsv 0:ba7650f404af 3731 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
aravindsv 0:ba7650f404af 3732 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3733 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3734 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3735 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3736
aravindsv 0:ba7650f404af 3737 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
aravindsv 0:ba7650f404af 3738 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3739 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3740 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3741 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3742
aravindsv 0:ba7650f404af 3743 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
aravindsv 0:ba7650f404af 3744 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3745 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3746 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3747 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3748
aravindsv 0:ba7650f404af 3749 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
aravindsv 0:ba7650f404af 3750 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3751 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3752
aravindsv 0:ba7650f404af 3753 /****************** Bit definition for FSMC_BTR4 register *******************/
aravindsv 0:ba7650f404af 3754 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
aravindsv 0:ba7650f404af 3755 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3756 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3757 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3758 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3759
aravindsv 0:ba7650f404af 3760 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
aravindsv 0:ba7650f404af 3761 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3762 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3763 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3764 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3765
aravindsv 0:ba7650f404af 3766 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
aravindsv 0:ba7650f404af 3767 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3768 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3769 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3770 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3771
aravindsv 0:ba7650f404af 3772 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
aravindsv 0:ba7650f404af 3773 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3774 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3775 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3776 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3777
aravindsv 0:ba7650f404af 3778 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
aravindsv 0:ba7650f404af 3779 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3780 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3781 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3782 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3783
aravindsv 0:ba7650f404af 3784 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
aravindsv 0:ba7650f404af 3785 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3786 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3787 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3788 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3789
aravindsv 0:ba7650f404af 3790 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
aravindsv 0:ba7650f404af 3791 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3792 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3793
aravindsv 0:ba7650f404af 3794 /****************** Bit definition for FSMC_BWTR1 register ******************/
aravindsv 0:ba7650f404af 3795 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
aravindsv 0:ba7650f404af 3796 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3797 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3798 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3799 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3800
aravindsv 0:ba7650f404af 3801 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
aravindsv 0:ba7650f404af 3802 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3803 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3804 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3805 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3806
aravindsv 0:ba7650f404af 3807 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
aravindsv 0:ba7650f404af 3808 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3809 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3810 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3811 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3812
aravindsv 0:ba7650f404af 3813 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
aravindsv 0:ba7650f404af 3814 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3815 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3816 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3817 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3818
aravindsv 0:ba7650f404af 3819 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
aravindsv 0:ba7650f404af 3820 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3821 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3822 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3823 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3824
aravindsv 0:ba7650f404af 3825 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
aravindsv 0:ba7650f404af 3826 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3827 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3828
aravindsv 0:ba7650f404af 3829 /****************** Bit definition for FSMC_BWTR2 register ******************/
aravindsv 0:ba7650f404af 3830 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
aravindsv 0:ba7650f404af 3831 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3832 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3833 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3834 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3835
aravindsv 0:ba7650f404af 3836 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
aravindsv 0:ba7650f404af 3837 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3838 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3839 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3840 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3841
aravindsv 0:ba7650f404af 3842 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
aravindsv 0:ba7650f404af 3843 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3844 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3845 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3846 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3847
aravindsv 0:ba7650f404af 3848 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
aravindsv 0:ba7650f404af 3849 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3850 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
aravindsv 0:ba7650f404af 3851 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3852 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3853
aravindsv 0:ba7650f404af 3854 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
aravindsv 0:ba7650f404af 3855 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3856 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3857 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3858 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3859
aravindsv 0:ba7650f404af 3860 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
aravindsv 0:ba7650f404af 3861 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3862 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3863
aravindsv 0:ba7650f404af 3864 /****************** Bit definition for FSMC_BWTR3 register ******************/
aravindsv 0:ba7650f404af 3865 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
aravindsv 0:ba7650f404af 3866 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3867 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3868 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3869 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3870
aravindsv 0:ba7650f404af 3871 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
aravindsv 0:ba7650f404af 3872 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3873 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3874 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3875 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3876
aravindsv 0:ba7650f404af 3877 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
aravindsv 0:ba7650f404af 3878 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3879 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3880 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3881 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3882
aravindsv 0:ba7650f404af 3883 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
aravindsv 0:ba7650f404af 3884 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3885 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3886 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3887 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3888
aravindsv 0:ba7650f404af 3889 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
aravindsv 0:ba7650f404af 3890 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3891 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3892 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3893 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3894
aravindsv 0:ba7650f404af 3895 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
aravindsv 0:ba7650f404af 3896 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3897 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3898
aravindsv 0:ba7650f404af 3899 /****************** Bit definition for FSMC_BWTR4 register ******************/
aravindsv 0:ba7650f404af 3900 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
aravindsv 0:ba7650f404af 3901 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3902 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3903 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3904 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3905
aravindsv 0:ba7650f404af 3906 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
aravindsv 0:ba7650f404af 3907 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3908 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3909 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3910 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3911
aravindsv 0:ba7650f404af 3912 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
aravindsv 0:ba7650f404af 3913 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3914 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3915 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3916 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3917
aravindsv 0:ba7650f404af 3918 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
aravindsv 0:ba7650f404af 3919 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3920 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3921 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3922 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3923
aravindsv 0:ba7650f404af 3924 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
aravindsv 0:ba7650f404af 3925 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3926 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3927 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3928 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3929
aravindsv 0:ba7650f404af 3930 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
aravindsv 0:ba7650f404af 3931 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3932 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3933
aravindsv 0:ba7650f404af 3934 /****************** Bit definition for FSMC_PCR2 register *******************/
aravindsv 0:ba7650f404af 3935 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
aravindsv 0:ba7650f404af 3936 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
aravindsv 0:ba7650f404af 3937 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
aravindsv 0:ba7650f404af 3938
aravindsv 0:ba7650f404af 3939 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
aravindsv 0:ba7650f404af 3940 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3941 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3942
aravindsv 0:ba7650f404af 3943 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
aravindsv 0:ba7650f404af 3944
aravindsv 0:ba7650f404af 3945 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
aravindsv 0:ba7650f404af 3946 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3947 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3948 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3949 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3950
aravindsv 0:ba7650f404af 3951 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
aravindsv 0:ba7650f404af 3952 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3953 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3954 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3955 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3956
aravindsv 0:ba7650f404af 3957 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
aravindsv 0:ba7650f404af 3958 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3959 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3960 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3961
aravindsv 0:ba7650f404af 3962 /****************** Bit definition for FSMC_PCR3 register *******************/
aravindsv 0:ba7650f404af 3963 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
aravindsv 0:ba7650f404af 3964 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
aravindsv 0:ba7650f404af 3965 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
aravindsv 0:ba7650f404af 3966
aravindsv 0:ba7650f404af 3967 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
aravindsv 0:ba7650f404af 3968 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3969 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3970
aravindsv 0:ba7650f404af 3971 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
aravindsv 0:ba7650f404af 3972
aravindsv 0:ba7650f404af 3973 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
aravindsv 0:ba7650f404af 3974 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3975 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3976 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3977 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3978
aravindsv 0:ba7650f404af 3979 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
aravindsv 0:ba7650f404af 3980 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3981 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3982 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3983 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 3984
aravindsv 0:ba7650f404af 3985 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
aravindsv 0:ba7650f404af 3986 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3987 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3988 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 3989
aravindsv 0:ba7650f404af 3990 /****************** Bit definition for FSMC_PCR4 register *******************/
aravindsv 0:ba7650f404af 3991 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
aravindsv 0:ba7650f404af 3992 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
aravindsv 0:ba7650f404af 3993 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
aravindsv 0:ba7650f404af 3994
aravindsv 0:ba7650f404af 3995 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
aravindsv 0:ba7650f404af 3996 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 3997 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 3998
aravindsv 0:ba7650f404af 3999 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
aravindsv 0:ba7650f404af 4000
aravindsv 0:ba7650f404af 4001 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
aravindsv 0:ba7650f404af 4002 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4003 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4004 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4005 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4006
aravindsv 0:ba7650f404af 4007 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
aravindsv 0:ba7650f404af 4008 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4009 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4010 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4011 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4012
aravindsv 0:ba7650f404af 4013 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
aravindsv 0:ba7650f404af 4014 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4015 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4016 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4017
aravindsv 0:ba7650f404af 4018 /******************* Bit definition for FSMC_SR2 register *******************/
aravindsv 0:ba7650f404af 4019 #define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
aravindsv 0:ba7650f404af 4020 #define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
aravindsv 0:ba7650f404af 4021 #define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
aravindsv 0:ba7650f404af 4022 #define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
aravindsv 0:ba7650f404af 4023 #define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
aravindsv 0:ba7650f404af 4024 #define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
aravindsv 0:ba7650f404af 4025 #define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
aravindsv 0:ba7650f404af 4026
aravindsv 0:ba7650f404af 4027 /******************* Bit definition for FSMC_SR3 register *******************/
aravindsv 0:ba7650f404af 4028 #define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
aravindsv 0:ba7650f404af 4029 #define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
aravindsv 0:ba7650f404af 4030 #define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
aravindsv 0:ba7650f404af 4031 #define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
aravindsv 0:ba7650f404af 4032 #define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
aravindsv 0:ba7650f404af 4033 #define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
aravindsv 0:ba7650f404af 4034 #define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
aravindsv 0:ba7650f404af 4035
aravindsv 0:ba7650f404af 4036 /******************* Bit definition for FSMC_SR4 register *******************/
aravindsv 0:ba7650f404af 4037 #define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */
aravindsv 0:ba7650f404af 4038 #define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */
aravindsv 0:ba7650f404af 4039 #define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */
aravindsv 0:ba7650f404af 4040 #define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
aravindsv 0:ba7650f404af 4041 #define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */
aravindsv 0:ba7650f404af 4042 #define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
aravindsv 0:ba7650f404af 4043 #define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */
aravindsv 0:ba7650f404af 4044
aravindsv 0:ba7650f404af 4045 /****************** Bit definition for FSMC_PMEM2 register ******************/
aravindsv 0:ba7650f404af 4046 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
aravindsv 0:ba7650f404af 4047 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4048 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4049 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4050 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4051 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4052 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4053 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4054 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4055
aravindsv 0:ba7650f404af 4056 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
aravindsv 0:ba7650f404af 4057 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4058 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4059 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4060 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4061 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4062 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4063 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4064 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4065
aravindsv 0:ba7650f404af 4066 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
aravindsv 0:ba7650f404af 4067 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4068 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4069 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4070 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4071 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4072 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4073 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4074 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4075
aravindsv 0:ba7650f404af 4076 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
aravindsv 0:ba7650f404af 4077 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4078 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4079 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4080 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4081 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4082 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4083 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4084 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4085
aravindsv 0:ba7650f404af 4086 /****************** Bit definition for FSMC_PMEM3 register ******************/
aravindsv 0:ba7650f404af 4087 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
aravindsv 0:ba7650f404af 4088 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4089 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4090 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4091 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4092 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4093 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4094 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4095 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4096
aravindsv 0:ba7650f404af 4097 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
aravindsv 0:ba7650f404af 4098 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4099 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4100 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4101 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4102 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4103 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4104 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4105 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4106
aravindsv 0:ba7650f404af 4107 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
aravindsv 0:ba7650f404af 4108 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4109 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4110 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4111 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4112 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4113 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4114 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4115 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4116
aravindsv 0:ba7650f404af 4117 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
aravindsv 0:ba7650f404af 4118 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4119 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4120 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4121 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4122 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4123 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4124 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4125 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4126
aravindsv 0:ba7650f404af 4127 /****************** Bit definition for FSMC_PMEM4 register ******************/
aravindsv 0:ba7650f404af 4128 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
aravindsv 0:ba7650f404af 4129 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4130 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4131 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4132 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4133 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4134 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4135 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4136 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4137
aravindsv 0:ba7650f404af 4138 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
aravindsv 0:ba7650f404af 4139 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4140 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4141 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4142 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4143 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4144 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4145 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4146 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4147
aravindsv 0:ba7650f404af 4148 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
aravindsv 0:ba7650f404af 4149 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4150 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4151 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4152 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4153 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4154 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4155 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4156 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4157
aravindsv 0:ba7650f404af 4158 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
aravindsv 0:ba7650f404af 4159 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4160 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4161 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4162 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4163 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4164 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4165 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4166 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4167
aravindsv 0:ba7650f404af 4168 /****************** Bit definition for FSMC_PATT2 register ******************/
aravindsv 0:ba7650f404af 4169 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
aravindsv 0:ba7650f404af 4170 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4171 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4172 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4173 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4174 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4175 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4176 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4177 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4178
aravindsv 0:ba7650f404af 4179 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
aravindsv 0:ba7650f404af 4180 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4181 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4182 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4183 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4184 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4185 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4186 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4187 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4188
aravindsv 0:ba7650f404af 4189 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
aravindsv 0:ba7650f404af 4190 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4191 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4192 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4193 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4194 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4195 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4196 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4197 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4198
aravindsv 0:ba7650f404af 4199 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
aravindsv 0:ba7650f404af 4200 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4201 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4202 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4203 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4204 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4205 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4206 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4207 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4208
aravindsv 0:ba7650f404af 4209 /****************** Bit definition for FSMC_PATT3 register ******************/
aravindsv 0:ba7650f404af 4210 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
aravindsv 0:ba7650f404af 4211 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4212 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4213 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4214 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4215 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4216 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4217 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4218 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4219
aravindsv 0:ba7650f404af 4220 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
aravindsv 0:ba7650f404af 4221 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4222 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4223 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4224 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4225 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4226 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4227 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4228 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4229
aravindsv 0:ba7650f404af 4230 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
aravindsv 0:ba7650f404af 4231 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4232 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4233 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4234 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4235 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4236 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4237 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4238 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4239
aravindsv 0:ba7650f404af 4240 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
aravindsv 0:ba7650f404af 4241 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4242 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4243 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4244 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4245 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4246 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4247 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4248 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4249
aravindsv 0:ba7650f404af 4250 /****************** Bit definition for FSMC_PATT4 register ******************/
aravindsv 0:ba7650f404af 4251 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
aravindsv 0:ba7650f404af 4252 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4253 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4254 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4255 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4256 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4257 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4258 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4259 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4260
aravindsv 0:ba7650f404af 4261 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
aravindsv 0:ba7650f404af 4262 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4263 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4264 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4265 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4266 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4267 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4268 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4269 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4270
aravindsv 0:ba7650f404af 4271 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
aravindsv 0:ba7650f404af 4272 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4273 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4274 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4275 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4276 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4277 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4278 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4279 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4280
aravindsv 0:ba7650f404af 4281 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
aravindsv 0:ba7650f404af 4282 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4283 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4284 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4285 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4286 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4287 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4288 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4289 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4290
aravindsv 0:ba7650f404af 4291 /****************** Bit definition for FSMC_PIO4 register *******************/
aravindsv 0:ba7650f404af 4292 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
aravindsv 0:ba7650f404af 4293 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4294 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4295 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4296 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4297 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4298 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4299 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4300 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4301
aravindsv 0:ba7650f404af 4302 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
aravindsv 0:ba7650f404af 4303 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4304 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4305 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4306 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4307 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4308 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4309 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4310 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4311
aravindsv 0:ba7650f404af 4312 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
aravindsv 0:ba7650f404af 4313 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4314 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4315 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4316 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4317 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4318 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4319 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4320 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4321
aravindsv 0:ba7650f404af 4322 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
aravindsv 0:ba7650f404af 4323 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4324 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4325 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4326 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4327 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4328 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4329 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4330 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4331
aravindsv 0:ba7650f404af 4332 /****************** Bit definition for FSMC_ECCR2 register ******************/
aravindsv 0:ba7650f404af 4333 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
aravindsv 0:ba7650f404af 4334
aravindsv 0:ba7650f404af 4335 /****************** Bit definition for FSMC_ECCR3 register ******************/
aravindsv 0:ba7650f404af 4336 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
aravindsv 0:ba7650f404af 4337
aravindsv 0:ba7650f404af 4338
aravindsv 0:ba7650f404af 4339 /******************************************************************************/
aravindsv 0:ba7650f404af 4340 /* */
aravindsv 0:ba7650f404af 4341 /* General Purpose I/O */
aravindsv 0:ba7650f404af 4342 /* */
aravindsv 0:ba7650f404af 4343 /******************************************************************************/
aravindsv 0:ba7650f404af 4344 /****************** Bits definition for GPIO_MODER register *****************/
aravindsv 0:ba7650f404af 4345 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
aravindsv 0:ba7650f404af 4346 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4347 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4348
aravindsv 0:ba7650f404af 4349 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
aravindsv 0:ba7650f404af 4350 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4351 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4352
aravindsv 0:ba7650f404af 4353 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
aravindsv 0:ba7650f404af 4354 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4355 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4356
aravindsv 0:ba7650f404af 4357 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
aravindsv 0:ba7650f404af 4358 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4359 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4360
aravindsv 0:ba7650f404af 4361 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
aravindsv 0:ba7650f404af 4362 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4363 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4364
aravindsv 0:ba7650f404af 4365 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
aravindsv 0:ba7650f404af 4366 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4367 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4368
aravindsv 0:ba7650f404af 4369 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
aravindsv 0:ba7650f404af 4370 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4371 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4372
aravindsv 0:ba7650f404af 4373 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
aravindsv 0:ba7650f404af 4374 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 4375 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 4376
aravindsv 0:ba7650f404af 4377 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
aravindsv 0:ba7650f404af 4378 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 4379 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 4380
aravindsv 0:ba7650f404af 4381 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
aravindsv 0:ba7650f404af 4382 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 4383 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 4384
aravindsv 0:ba7650f404af 4385 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
aravindsv 0:ba7650f404af 4386 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 4387 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 4388
aravindsv 0:ba7650f404af 4389 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
aravindsv 0:ba7650f404af 4390 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 4391 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 4392
aravindsv 0:ba7650f404af 4393 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
aravindsv 0:ba7650f404af 4394 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 4395 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 4396
aravindsv 0:ba7650f404af 4397 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
aravindsv 0:ba7650f404af 4398 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 4399 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 4400
aravindsv 0:ba7650f404af 4401 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
aravindsv 0:ba7650f404af 4402 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 4403 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 4404
aravindsv 0:ba7650f404af 4405 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
aravindsv 0:ba7650f404af 4406 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 4407 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 4408
aravindsv 0:ba7650f404af 4409 /****************** Bits definition for GPIO_OTYPER register ****************/
aravindsv 0:ba7650f404af 4410 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4411 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4412 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4413 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4414 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4415 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4416 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4417 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4418 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4419 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4420 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4421 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4422 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4423 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4424 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 4425 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 4426
aravindsv 0:ba7650f404af 4427 /****************** Bits definition for GPIO_OSPEEDR register ***************/
aravindsv 0:ba7650f404af 4428 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
aravindsv 0:ba7650f404af 4429 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4430 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4431
aravindsv 0:ba7650f404af 4432 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
aravindsv 0:ba7650f404af 4433 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4434 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4435
aravindsv 0:ba7650f404af 4436 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
aravindsv 0:ba7650f404af 4437 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4438 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4439
aravindsv 0:ba7650f404af 4440 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
aravindsv 0:ba7650f404af 4441 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4442 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4443
aravindsv 0:ba7650f404af 4444 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
aravindsv 0:ba7650f404af 4445 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4446 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4447
aravindsv 0:ba7650f404af 4448 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
aravindsv 0:ba7650f404af 4449 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4450 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4451
aravindsv 0:ba7650f404af 4452 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
aravindsv 0:ba7650f404af 4453 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4454 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4455
aravindsv 0:ba7650f404af 4456 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
aravindsv 0:ba7650f404af 4457 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 4458 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 4459
aravindsv 0:ba7650f404af 4460 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
aravindsv 0:ba7650f404af 4461 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 4462 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 4463
aravindsv 0:ba7650f404af 4464 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
aravindsv 0:ba7650f404af 4465 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 4466 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 4467
aravindsv 0:ba7650f404af 4468 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
aravindsv 0:ba7650f404af 4469 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 4470 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 4471
aravindsv 0:ba7650f404af 4472 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
aravindsv 0:ba7650f404af 4473 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 4474 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 4475
aravindsv 0:ba7650f404af 4476 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
aravindsv 0:ba7650f404af 4477 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 4478 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 4479
aravindsv 0:ba7650f404af 4480 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
aravindsv 0:ba7650f404af 4481 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 4482 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 4483
aravindsv 0:ba7650f404af 4484 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
aravindsv 0:ba7650f404af 4485 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 4486 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 4487
aravindsv 0:ba7650f404af 4488 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
aravindsv 0:ba7650f404af 4489 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 4490 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 4491
aravindsv 0:ba7650f404af 4492 /****************** Bits definition for GPIO_PUPDR register *****************/
aravindsv 0:ba7650f404af 4493 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
aravindsv 0:ba7650f404af 4494 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4495 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4496
aravindsv 0:ba7650f404af 4497 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
aravindsv 0:ba7650f404af 4498 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4499 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4500
aravindsv 0:ba7650f404af 4501 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
aravindsv 0:ba7650f404af 4502 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4503 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4504
aravindsv 0:ba7650f404af 4505 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
aravindsv 0:ba7650f404af 4506 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4507 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4508
aravindsv 0:ba7650f404af 4509 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
aravindsv 0:ba7650f404af 4510 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4511 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4512
aravindsv 0:ba7650f404af 4513 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
aravindsv 0:ba7650f404af 4514 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4515 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4516
aravindsv 0:ba7650f404af 4517 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
aravindsv 0:ba7650f404af 4518 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4519 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4520
aravindsv 0:ba7650f404af 4521 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
aravindsv 0:ba7650f404af 4522 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 4523 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 4524
aravindsv 0:ba7650f404af 4525 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
aravindsv 0:ba7650f404af 4526 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 4527 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 4528
aravindsv 0:ba7650f404af 4529 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
aravindsv 0:ba7650f404af 4530 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 4531 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 4532
aravindsv 0:ba7650f404af 4533 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
aravindsv 0:ba7650f404af 4534 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 4535 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 4536
aravindsv 0:ba7650f404af 4537 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
aravindsv 0:ba7650f404af 4538 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 4539 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 4540
aravindsv 0:ba7650f404af 4541 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
aravindsv 0:ba7650f404af 4542 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 4543 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 4544
aravindsv 0:ba7650f404af 4545 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
aravindsv 0:ba7650f404af 4546 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 4547 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 4548
aravindsv 0:ba7650f404af 4549 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
aravindsv 0:ba7650f404af 4550 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 4551 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 4552
aravindsv 0:ba7650f404af 4553 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
aravindsv 0:ba7650f404af 4554 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 4555 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 4556
aravindsv 0:ba7650f404af 4557 /****************** Bits definition for GPIO_IDR register *******************/
aravindsv 0:ba7650f404af 4558 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4559 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4560 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4561 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4562 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4563 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4564 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4565 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4566 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4567 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4568 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4569 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4570 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4571 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4572 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 4573 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 4574 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
aravindsv 0:ba7650f404af 4575 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
aravindsv 0:ba7650f404af 4576 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
aravindsv 0:ba7650f404af 4577 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
aravindsv 0:ba7650f404af 4578 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
aravindsv 0:ba7650f404af 4579 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
aravindsv 0:ba7650f404af 4580 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
aravindsv 0:ba7650f404af 4581 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
aravindsv 0:ba7650f404af 4582 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
aravindsv 0:ba7650f404af 4583 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
aravindsv 0:ba7650f404af 4584 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
aravindsv 0:ba7650f404af 4585 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
aravindsv 0:ba7650f404af 4586 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
aravindsv 0:ba7650f404af 4587 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
aravindsv 0:ba7650f404af 4588 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
aravindsv 0:ba7650f404af 4589 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
aravindsv 0:ba7650f404af 4590 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
aravindsv 0:ba7650f404af 4591
aravindsv 0:ba7650f404af 4592 /****************** Bits definition for GPIO_ODR register *******************/
aravindsv 0:ba7650f404af 4593 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4594 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4595 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4596 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4597 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4598 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4599 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4600 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4601 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4602 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4603 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4604 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4605 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4606 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4607 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 4608 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 4609 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
aravindsv 0:ba7650f404af 4610 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
aravindsv 0:ba7650f404af 4611 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
aravindsv 0:ba7650f404af 4612 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
aravindsv 0:ba7650f404af 4613 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
aravindsv 0:ba7650f404af 4614 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
aravindsv 0:ba7650f404af 4615 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
aravindsv 0:ba7650f404af 4616 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
aravindsv 0:ba7650f404af 4617 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
aravindsv 0:ba7650f404af 4618 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
aravindsv 0:ba7650f404af 4619 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
aravindsv 0:ba7650f404af 4620 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
aravindsv 0:ba7650f404af 4621 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
aravindsv 0:ba7650f404af 4622 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
aravindsv 0:ba7650f404af 4623 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
aravindsv 0:ba7650f404af 4624 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
aravindsv 0:ba7650f404af 4625 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
aravindsv 0:ba7650f404af 4626
aravindsv 0:ba7650f404af 4627 /****************** Bits definition for GPIO_BSRR register ******************/
aravindsv 0:ba7650f404af 4628 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4629 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4630 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4631 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4632 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4633 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4634 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4635 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4636 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4637 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4638 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4639 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4640 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4641 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4642 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 4643 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 4644 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 4645 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 4646 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 4647 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 4648 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 4649 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 4650 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 4651 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 4652 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 4653 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 4654 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 4655 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 4656 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 4657 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 4658 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 4659 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 4660
aravindsv 0:ba7650f404af 4661 /******************************************************************************/
aravindsv 0:ba7650f404af 4662 /* */
aravindsv 0:ba7650f404af 4663 /* HASH */
aravindsv 0:ba7650f404af 4664 /* */
aravindsv 0:ba7650f404af 4665 /******************************************************************************/
aravindsv 0:ba7650f404af 4666 /****************** Bits definition for HASH_CR register ********************/
aravindsv 0:ba7650f404af 4667 #define HASH_CR_INIT ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4668 #define HASH_CR_DMAE ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4669 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
aravindsv 0:ba7650f404af 4670 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4671 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4672 #define HASH_CR_MODE ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4673 #define HASH_CR_ALGO ((uint32_t)0x00040080)
aravindsv 0:ba7650f404af 4674 #define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4675 #define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 4676 #define HASH_CR_NBW ((uint32_t)0x00000F00)
aravindsv 0:ba7650f404af 4677 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4678 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4679 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4680 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4681 #define HASH_CR_DINNE ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4682 #define HASH_CR_MDMAT ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4683 #define HASH_CR_LKEY ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 4684
aravindsv 0:ba7650f404af 4685 /****************** Bits definition for HASH_STR register *******************/
aravindsv 0:ba7650f404af 4686 #define HASH_STR_NBW ((uint32_t)0x0000001F)
aravindsv 0:ba7650f404af 4687 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4688 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4689 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4690 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4691 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4692 #define HASH_STR_DCAL ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4693
aravindsv 0:ba7650f404af 4694 /****************** Bits definition for HASH_IMR register *******************/
aravindsv 0:ba7650f404af 4695 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4696 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4697
aravindsv 0:ba7650f404af 4698 /****************** Bits definition for HASH_SR register ********************/
aravindsv 0:ba7650f404af 4699 #define HASH_SR_DINIS ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4700 #define HASH_SR_DCIS ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4701 #define HASH_SR_DMAS ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4702 #define HASH_SR_BUSY ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4703
aravindsv 0:ba7650f404af 4704 /******************************************************************************/
aravindsv 0:ba7650f404af 4705 /* */
aravindsv 0:ba7650f404af 4706 /* Inter-integrated Circuit Interface */
aravindsv 0:ba7650f404af 4707 /* */
aravindsv 0:ba7650f404af 4708 /******************************************************************************/
aravindsv 0:ba7650f404af 4709 /******************* Bit definition for I2C_CR1 register ********************/
aravindsv 0:ba7650f404af 4710 #define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */
aravindsv 0:ba7650f404af 4711 #define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */
aravindsv 0:ba7650f404af 4712 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */
aravindsv 0:ba7650f404af 4713 #define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */
aravindsv 0:ba7650f404af 4714 #define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */
aravindsv 0:ba7650f404af 4715 #define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */
aravindsv 0:ba7650f404af 4716 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */
aravindsv 0:ba7650f404af 4717 #define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */
aravindsv 0:ba7650f404af 4718 #define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */
aravindsv 0:ba7650f404af 4719 #define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */
aravindsv 0:ba7650f404af 4720 #define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */
aravindsv 0:ba7650f404af 4721 #define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */
aravindsv 0:ba7650f404af 4722 #define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */
aravindsv 0:ba7650f404af 4723 #define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */
aravindsv 0:ba7650f404af 4724
aravindsv 0:ba7650f404af 4725 /******************* Bit definition for I2C_CR2 register ********************/
aravindsv 0:ba7650f404af 4726 #define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
aravindsv 0:ba7650f404af 4727 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4728 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4729 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4730 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4731 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4732 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4733
aravindsv 0:ba7650f404af 4734 #define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */
aravindsv 0:ba7650f404af 4735 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */
aravindsv 0:ba7650f404af 4736 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */
aravindsv 0:ba7650f404af 4737 #define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */
aravindsv 0:ba7650f404af 4738 #define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */
aravindsv 0:ba7650f404af 4739
aravindsv 0:ba7650f404af 4740 /******************* Bit definition for I2C_OAR1 register *******************/
aravindsv 0:ba7650f404af 4741 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */
aravindsv 0:ba7650f404af 4742 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */
aravindsv 0:ba7650f404af 4743
aravindsv 0:ba7650f404af 4744 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4745 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4746 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4747 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 4748 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 4749 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 4750 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 4751 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 4752 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */
aravindsv 0:ba7650f404af 4753 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */
aravindsv 0:ba7650f404af 4754
aravindsv 0:ba7650f404af 4755 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */
aravindsv 0:ba7650f404af 4756
aravindsv 0:ba7650f404af 4757 /******************* Bit definition for I2C_OAR2 register *******************/
aravindsv 0:ba7650f404af 4758 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */
aravindsv 0:ba7650f404af 4759 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */
aravindsv 0:ba7650f404af 4760
aravindsv 0:ba7650f404af 4761 /******************** Bit definition for I2C_DR register ********************/
aravindsv 0:ba7650f404af 4762 #define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */
aravindsv 0:ba7650f404af 4763
aravindsv 0:ba7650f404af 4764 /******************* Bit definition for I2C_SR1 register ********************/
aravindsv 0:ba7650f404af 4765 #define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */
aravindsv 0:ba7650f404af 4766 #define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */
aravindsv 0:ba7650f404af 4767 #define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */
aravindsv 0:ba7650f404af 4768 #define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */
aravindsv 0:ba7650f404af 4769 #define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */
aravindsv 0:ba7650f404af 4770 #define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */
aravindsv 0:ba7650f404af 4771 #define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */
aravindsv 0:ba7650f404af 4772 #define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */
aravindsv 0:ba7650f404af 4773 #define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */
aravindsv 0:ba7650f404af 4774 #define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */
aravindsv 0:ba7650f404af 4775 #define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */
aravindsv 0:ba7650f404af 4776 #define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */
aravindsv 0:ba7650f404af 4777 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */
aravindsv 0:ba7650f404af 4778 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */
aravindsv 0:ba7650f404af 4779
aravindsv 0:ba7650f404af 4780 /******************* Bit definition for I2C_SR2 register ********************/
aravindsv 0:ba7650f404af 4781 #define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */
aravindsv 0:ba7650f404af 4782 #define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */
aravindsv 0:ba7650f404af 4783 #define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */
aravindsv 0:ba7650f404af 4784 #define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */
aravindsv 0:ba7650f404af 4785 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */
aravindsv 0:ba7650f404af 4786 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */
aravindsv 0:ba7650f404af 4787 #define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */
aravindsv 0:ba7650f404af 4788 #define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */
aravindsv 0:ba7650f404af 4789
aravindsv 0:ba7650f404af 4790 /******************* Bit definition for I2C_CCR register ********************/
aravindsv 0:ba7650f404af 4791 #define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
aravindsv 0:ba7650f404af 4792 #define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */
aravindsv 0:ba7650f404af 4793 #define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */
aravindsv 0:ba7650f404af 4794
aravindsv 0:ba7650f404af 4795 /****************** Bit definition for I2C_TRISE register *******************/
aravindsv 0:ba7650f404af 4796 #define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
aravindsv 0:ba7650f404af 4797
aravindsv 0:ba7650f404af 4798 /****************** Bit definition for I2C_FLTR register *******************/
aravindsv 0:ba7650f404af 4799 #define I2C_FLTR_DNF ((uint8_t)0x0F) /*!<Digital Noise Filter */
aravindsv 0:ba7650f404af 4800 #define I2C_FLTR_ANOFF ((uint8_t)0x10) /*!<Analog Noise Filter OFF */
aravindsv 0:ba7650f404af 4801
aravindsv 0:ba7650f404af 4802 /******************************************************************************/
aravindsv 0:ba7650f404af 4803 /* */
aravindsv 0:ba7650f404af 4804 /* Independent WATCHDOG */
aravindsv 0:ba7650f404af 4805 /* */
aravindsv 0:ba7650f404af 4806 /******************************************************************************/
aravindsv 0:ba7650f404af 4807 /******************* Bit definition for IWDG_KR register ********************/
aravindsv 0:ba7650f404af 4808 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */
aravindsv 0:ba7650f404af 4809
aravindsv 0:ba7650f404af 4810 /******************* Bit definition for IWDG_PR register ********************/
aravindsv 0:ba7650f404af 4811 #define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */
aravindsv 0:ba7650f404af 4812 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */
aravindsv 0:ba7650f404af 4813 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */
aravindsv 0:ba7650f404af 4814 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */
aravindsv 0:ba7650f404af 4815
aravindsv 0:ba7650f404af 4816 /******************* Bit definition for IWDG_RLR register *******************/
aravindsv 0:ba7650f404af 4817 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */
aravindsv 0:ba7650f404af 4818
aravindsv 0:ba7650f404af 4819 /******************* Bit definition for IWDG_SR register ********************/
aravindsv 0:ba7650f404af 4820 #define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */
aravindsv 0:ba7650f404af 4821 #define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */
aravindsv 0:ba7650f404af 4822
aravindsv 0:ba7650f404af 4823
aravindsv 0:ba7650f404af 4824 /******************************************************************************/
aravindsv 0:ba7650f404af 4825 /* */
aravindsv 0:ba7650f404af 4826 /* Power Control */
aravindsv 0:ba7650f404af 4827 /* */
aravindsv 0:ba7650f404af 4828 /******************************************************************************/
aravindsv 0:ba7650f404af 4829 /******************** Bit definition for PWR_CR register ********************/
aravindsv 0:ba7650f404af 4830 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
aravindsv 0:ba7650f404af 4831 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
aravindsv 0:ba7650f404af 4832 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
aravindsv 0:ba7650f404af 4833 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
aravindsv 0:ba7650f404af 4834 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
aravindsv 0:ba7650f404af 4835
aravindsv 0:ba7650f404af 4836 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
aravindsv 0:ba7650f404af 4837 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
aravindsv 0:ba7650f404af 4838 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
aravindsv 0:ba7650f404af 4839 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
aravindsv 0:ba7650f404af 4840
aravindsv 0:ba7650f404af 4841 /*!< PVD level configuration */
aravindsv 0:ba7650f404af 4842 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
aravindsv 0:ba7650f404af 4843 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
aravindsv 0:ba7650f404af 4844 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
aravindsv 0:ba7650f404af 4845 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
aravindsv 0:ba7650f404af 4846 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
aravindsv 0:ba7650f404af 4847 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
aravindsv 0:ba7650f404af 4848 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
aravindsv 0:ba7650f404af 4849 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
aravindsv 0:ba7650f404af 4850
aravindsv 0:ba7650f404af 4851 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
aravindsv 0:ba7650f404af 4852 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
aravindsv 0:ba7650f404af 4853 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
aravindsv 0:ba7650f404af 4854 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
aravindsv 0:ba7650f404af 4855
aravindsv 0:ba7650f404af 4856 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
aravindsv 0:ba7650f404af 4857 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
aravindsv 0:ba7650f404af 4858 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
aravindsv 0:ba7650f404af 4859
aravindsv 0:ba7650f404af 4860 /* Legacy define */
aravindsv 0:ba7650f404af 4861 #define PWR_CR_PMODE PWR_CR_VOS
aravindsv 0:ba7650f404af 4862
aravindsv 0:ba7650f404af 4863 /******************* Bit definition for PWR_CSR register ********************/
aravindsv 0:ba7650f404af 4864 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
aravindsv 0:ba7650f404af 4865 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
aravindsv 0:ba7650f404af 4866 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
aravindsv 0:ba7650f404af 4867 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
aravindsv 0:ba7650f404af 4868 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
aravindsv 0:ba7650f404af 4869 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
aravindsv 0:ba7650f404af 4870 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
aravindsv 0:ba7650f404af 4871
aravindsv 0:ba7650f404af 4872 /* Legacy define */
aravindsv 0:ba7650f404af 4873 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
aravindsv 0:ba7650f404af 4874
aravindsv 0:ba7650f404af 4875 /******************************************************************************/
aravindsv 0:ba7650f404af 4876 /* */
aravindsv 0:ba7650f404af 4877 /* Reset and Clock Control */
aravindsv 0:ba7650f404af 4878 /* */
aravindsv 0:ba7650f404af 4879 /******************************************************************************/
aravindsv 0:ba7650f404af 4880 /******************** Bit definition for RCC_CR register ********************/
aravindsv 0:ba7650f404af 4881 #define RCC_CR_HSION ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4882 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4883
aravindsv 0:ba7650f404af 4884 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
aravindsv 0:ba7650f404af 4885 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
aravindsv 0:ba7650f404af 4886 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
aravindsv 0:ba7650f404af 4887 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
aravindsv 0:ba7650f404af 4888 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
aravindsv 0:ba7650f404af 4889 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
aravindsv 0:ba7650f404af 4890
aravindsv 0:ba7650f404af 4891 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
aravindsv 0:ba7650f404af 4892 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
aravindsv 0:ba7650f404af 4893 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
aravindsv 0:ba7650f404af 4894 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
aravindsv 0:ba7650f404af 4895 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
aravindsv 0:ba7650f404af 4896 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
aravindsv 0:ba7650f404af 4897 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
aravindsv 0:ba7650f404af 4898 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
aravindsv 0:ba7650f404af 4899 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
aravindsv 0:ba7650f404af 4900
aravindsv 0:ba7650f404af 4901 #define RCC_CR_HSEON ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 4902 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 4903 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 4904 #define RCC_CR_CSSON ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 4905 #define RCC_CR_PLLON ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 4906 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 4907 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 4908 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 4909
aravindsv 0:ba7650f404af 4910
aravindsv 0:ba7650f404af 4911 /******************** Bit definition for RCC_PLLCFGR register ***************/
aravindsv 0:ba7650f404af 4912 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
aravindsv 0:ba7650f404af 4913 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 4914 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 4915 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 4916 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 4917 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 4918 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 4919
aravindsv 0:ba7650f404af 4920 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
aravindsv 0:ba7650f404af 4921 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 4922 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 4923 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 4924 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 4925 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 4926 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 4927 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 4928 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 4929 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 4930
aravindsv 0:ba7650f404af 4931 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
aravindsv 0:ba7650f404af 4932 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 4933 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 4934
aravindsv 0:ba7650f404af 4935 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 4936 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 4937 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
aravindsv 0:ba7650f404af 4938
aravindsv 0:ba7650f404af 4939 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
aravindsv 0:ba7650f404af 4940 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 4941 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 4942 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 4943 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 4944
aravindsv 0:ba7650f404af 4945 /******************** Bit definition for RCC_CFGR register ******************/
aravindsv 0:ba7650f404af 4946 /*!< SW configuration */
aravindsv 0:ba7650f404af 4947 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
aravindsv 0:ba7650f404af 4948 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
aravindsv 0:ba7650f404af 4949 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
aravindsv 0:ba7650f404af 4950
aravindsv 0:ba7650f404af 4951 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
aravindsv 0:ba7650f404af 4952 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
aravindsv 0:ba7650f404af 4953 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
aravindsv 0:ba7650f404af 4954
aravindsv 0:ba7650f404af 4955 /*!< SWS configuration */
aravindsv 0:ba7650f404af 4956 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
aravindsv 0:ba7650f404af 4957 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
aravindsv 0:ba7650f404af 4958 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
aravindsv 0:ba7650f404af 4959
aravindsv 0:ba7650f404af 4960 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
aravindsv 0:ba7650f404af 4961 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
aravindsv 0:ba7650f404af 4962 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
aravindsv 0:ba7650f404af 4963
aravindsv 0:ba7650f404af 4964 /*!< HPRE configuration */
aravindsv 0:ba7650f404af 4965 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
aravindsv 0:ba7650f404af 4966 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
aravindsv 0:ba7650f404af 4967 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
aravindsv 0:ba7650f404af 4968 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
aravindsv 0:ba7650f404af 4969 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
aravindsv 0:ba7650f404af 4970
aravindsv 0:ba7650f404af 4971 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
aravindsv 0:ba7650f404af 4972 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
aravindsv 0:ba7650f404af 4973 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
aravindsv 0:ba7650f404af 4974 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
aravindsv 0:ba7650f404af 4975 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
aravindsv 0:ba7650f404af 4976 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
aravindsv 0:ba7650f404af 4977 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
aravindsv 0:ba7650f404af 4978 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
aravindsv 0:ba7650f404af 4979 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
aravindsv 0:ba7650f404af 4980
aravindsv 0:ba7650f404af 4981 /*!< PPRE1 configuration */
aravindsv 0:ba7650f404af 4982 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
aravindsv 0:ba7650f404af 4983 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
aravindsv 0:ba7650f404af 4984 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
aravindsv 0:ba7650f404af 4985 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
aravindsv 0:ba7650f404af 4986
aravindsv 0:ba7650f404af 4987 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
aravindsv 0:ba7650f404af 4988 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
aravindsv 0:ba7650f404af 4989 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
aravindsv 0:ba7650f404af 4990 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
aravindsv 0:ba7650f404af 4991 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
aravindsv 0:ba7650f404af 4992
aravindsv 0:ba7650f404af 4993 /*!< PPRE2 configuration */
aravindsv 0:ba7650f404af 4994 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
aravindsv 0:ba7650f404af 4995 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
aravindsv 0:ba7650f404af 4996 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
aravindsv 0:ba7650f404af 4997 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
aravindsv 0:ba7650f404af 4998
aravindsv 0:ba7650f404af 4999 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
aravindsv 0:ba7650f404af 5000 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
aravindsv 0:ba7650f404af 5001 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
aravindsv 0:ba7650f404af 5002 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
aravindsv 0:ba7650f404af 5003 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
aravindsv 0:ba7650f404af 5004
aravindsv 0:ba7650f404af 5005 /*!< RTCPRE configuration */
aravindsv 0:ba7650f404af 5006 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
aravindsv 0:ba7650f404af 5007 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5008 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5009 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5010 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5011 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5012
aravindsv 0:ba7650f404af 5013 /*!< MCO1 configuration */
aravindsv 0:ba7650f404af 5014 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
aravindsv 0:ba7650f404af 5015 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5016 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5017
aravindsv 0:ba7650f404af 5018 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5019
aravindsv 0:ba7650f404af 5020 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
aravindsv 0:ba7650f404af 5021 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 5022 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5023 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5024
aravindsv 0:ba7650f404af 5025 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
aravindsv 0:ba7650f404af 5026 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 5027 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5028 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5029
aravindsv 0:ba7650f404af 5030 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
aravindsv 0:ba7650f404af 5031 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5032 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5033
aravindsv 0:ba7650f404af 5034 /******************** Bit definition for RCC_CIR register *******************/
aravindsv 0:ba7650f404af 5035 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5036 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5037 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5038 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5039 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5040 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5041 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5042 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5043 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5044 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5045 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5046 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5047 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5048 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5049 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5050 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5051 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5052 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5053 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5054 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5055
aravindsv 0:ba7650f404af 5056 /******************** Bit definition for RCC_AHB1RSTR register **************/
aravindsv 0:ba7650f404af 5057 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5058 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5059 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5060 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5061 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5062 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5063 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5064 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5065 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5066 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5067 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5068 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5069 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5070 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5071
aravindsv 0:ba7650f404af 5072 /******************** Bit definition for RCC_AHB2RSTR register **************/
aravindsv 0:ba7650f404af 5073 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5074 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5075 #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5076 /* maintained for legacy purpose */
aravindsv 0:ba7650f404af 5077 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
aravindsv 0:ba7650f404af 5078 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5079 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5080
aravindsv 0:ba7650f404af 5081 /******************** Bit definition for RCC_AHB3RSTR register **************/
aravindsv 0:ba7650f404af 5082 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5083
aravindsv 0:ba7650f404af 5084 /******************** Bit definition for RCC_APB1RSTR register **************/
aravindsv 0:ba7650f404af 5085 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5086 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5087 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5088 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5089 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5090 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5091 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5092 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5093 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5094 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5095 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5096 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5097 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5098 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5099 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5100 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5101 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5102 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5103 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5104 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5105 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5106 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5107 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5108 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5109 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5110
aravindsv 0:ba7650f404af 5111 /******************** Bit definition for RCC_APB2RSTR register **************/
aravindsv 0:ba7650f404af 5112 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5113 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5114 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5115 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5116 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5117 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5118 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5119 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5120 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5121 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5122 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5123 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5124 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5125 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5126
aravindsv 0:ba7650f404af 5127 /* Old SPI1RST bit definition, maintained for legacy purpose */
aravindsv 0:ba7650f404af 5128 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
aravindsv 0:ba7650f404af 5129
aravindsv 0:ba7650f404af 5130 /******************** Bit definition for RCC_AHB1ENR register ***************/
aravindsv 0:ba7650f404af 5131 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5132 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5133 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5134 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5135 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5136 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5137 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5138 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5139 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5140 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5141 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5142 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5143 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5144 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5145 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5146 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5147 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 5148 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5149 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5150 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5151
aravindsv 0:ba7650f404af 5152 /******************** Bit definition for RCC_AHB2ENR register ***************/
aravindsv 0:ba7650f404af 5153 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5154 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5155 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5156 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5157 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5158
aravindsv 0:ba7650f404af 5159 /******************** Bit definition for RCC_AHB3ENR register ***************/
aravindsv 0:ba7650f404af 5160 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5161
aravindsv 0:ba7650f404af 5162 /******************** Bit definition for RCC_APB1ENR register ***************/
aravindsv 0:ba7650f404af 5163 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5164 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5165 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5166 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5167 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5168 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5169 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5170 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5171 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5172 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5173 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5174 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5175 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5176 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5177 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5178 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5179 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5180 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5181 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5182 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5183 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5184 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5185 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5186 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5187 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5188
aravindsv 0:ba7650f404af 5189 /******************** Bit definition for RCC_APB2ENR register ***************/
aravindsv 0:ba7650f404af 5190 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5191 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5192 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5193 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5194 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5195 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5196 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5197 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5198 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5199 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5200 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5201 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5202 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5203 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5204 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5205 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5206
aravindsv 0:ba7650f404af 5207 /******************** Bit definition for RCC_AHB1LPENR register *************/
aravindsv 0:ba7650f404af 5208 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5209 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5210 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5211 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5212 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5213 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5214 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5215 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5216 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5217 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5218 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5219 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5220 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5221 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5222 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5223 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5224 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5225 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5226 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5227 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 5228 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5229 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5230 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5231
aravindsv 0:ba7650f404af 5232 /******************** Bit definition for RCC_AHB2LPENR register *************/
aravindsv 0:ba7650f404af 5233 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5234 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5235 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5236 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5237 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5238
aravindsv 0:ba7650f404af 5239 /******************** Bit definition for RCC_AHB3LPENR register *************/
aravindsv 0:ba7650f404af 5240 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5241
aravindsv 0:ba7650f404af 5242 /******************** Bit definition for RCC_APB1LPENR register *************/
aravindsv 0:ba7650f404af 5243 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5244 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5245 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5246 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5247 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5248 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5249 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5250 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5251 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5252 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5253 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5254 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5255 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5256 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5257 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5258 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5259 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5260 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5261 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5262 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5263 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5264 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5265 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5266 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5267 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5268
aravindsv 0:ba7650f404af 5269 /******************** Bit definition for RCC_APB2LPENR register *************/
aravindsv 0:ba7650f404af 5270 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5271 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5272 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5273 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5274 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5275 #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5276 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5277 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5278 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5279 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5280 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5281 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5282 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5283 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5284 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5285 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5286
aravindsv 0:ba7650f404af 5287 /******************** Bit definition for RCC_BDCR register ******************/
aravindsv 0:ba7650f404af 5288 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5289 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5290 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5291
aravindsv 0:ba7650f404af 5292 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
aravindsv 0:ba7650f404af 5293 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5294 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5295
aravindsv 0:ba7650f404af 5296 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5297 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5298
aravindsv 0:ba7650f404af 5299 /******************** Bit definition for RCC_CSR register *******************/
aravindsv 0:ba7650f404af 5300 #define RCC_CSR_LSION ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5301 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5302 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 5303 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5304 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5305 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 5306 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5307 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5308 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5309 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5310
aravindsv 0:ba7650f404af 5311 /******************** Bit definition for RCC_SSCGR register *****************/
aravindsv 0:ba7650f404af 5312 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
aravindsv 0:ba7650f404af 5313 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
aravindsv 0:ba7650f404af 5314 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5315 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5316
aravindsv 0:ba7650f404af 5317 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
aravindsv 0:ba7650f404af 5318 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
aravindsv 0:ba7650f404af 5319 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
aravindsv 0:ba7650f404af 5320
aravindsv 0:ba7650f404af 5321 /******************** Bit definition for RCC_DCKCFGR register ***************/
aravindsv 0:ba7650f404af 5322 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 5323
aravindsv 0:ba7650f404af 5324
aravindsv 0:ba7650f404af 5325 /******************************************************************************/
aravindsv 0:ba7650f404af 5326 /* */
aravindsv 0:ba7650f404af 5327 /* RNG */
aravindsv 0:ba7650f404af 5328 /* */
aravindsv 0:ba7650f404af 5329 /******************************************************************************/
aravindsv 0:ba7650f404af 5330 /******************** Bits definition for RNG_CR register *******************/
aravindsv 0:ba7650f404af 5331 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5332 #define RNG_CR_IE ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5333
aravindsv 0:ba7650f404af 5334 /******************** Bits definition for RNG_SR register *******************/
aravindsv 0:ba7650f404af 5335 #define RNG_SR_DRDY ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5336 #define RNG_SR_CECS ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5337 #define RNG_SR_SECS ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5338 #define RNG_SR_CEIS ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5339 #define RNG_SR_SEIS ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5340
aravindsv 0:ba7650f404af 5341 /******************************************************************************/
aravindsv 0:ba7650f404af 5342 /* */
aravindsv 0:ba7650f404af 5343 /* Real-Time Clock (RTC) */
aravindsv 0:ba7650f404af 5344 /* */
aravindsv 0:ba7650f404af 5345 /******************************************************************************/
aravindsv 0:ba7650f404af 5346 /******************** Bits definition for RTC_TR register *******************/
aravindsv 0:ba7650f404af 5347 #define RTC_TR_PM ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5348 #define RTC_TR_HT ((uint32_t)0x00300000)
aravindsv 0:ba7650f404af 5349 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5350 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5351 #define RTC_TR_HU ((uint32_t)0x000F0000)
aravindsv 0:ba7650f404af 5352 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5353 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5354 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5355 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5356 #define RTC_TR_MNT ((uint32_t)0x00007000)
aravindsv 0:ba7650f404af 5357 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5358 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5359 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5360 #define RTC_TR_MNU ((uint32_t)0x00000F00)
aravindsv 0:ba7650f404af 5361 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5362 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5363 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5364 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5365 #define RTC_TR_ST ((uint32_t)0x00000070)
aravindsv 0:ba7650f404af 5366 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5367 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5368 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5369 #define RTC_TR_SU ((uint32_t)0x0000000F)
aravindsv 0:ba7650f404af 5370 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5371 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5372 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5373 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5374
aravindsv 0:ba7650f404af 5375 /******************** Bits definition for RTC_DR register *******************/
aravindsv 0:ba7650f404af 5376 #define RTC_DR_YT ((uint32_t)0x00F00000)
aravindsv 0:ba7650f404af 5377 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5378 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5379 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5380 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5381 #define RTC_DR_YU ((uint32_t)0x000F0000)
aravindsv 0:ba7650f404af 5382 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5383 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5384 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5385 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5386 #define RTC_DR_WDU ((uint32_t)0x0000E000)
aravindsv 0:ba7650f404af 5387 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5388 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5389 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5390 #define RTC_DR_MT ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5391 #define RTC_DR_MU ((uint32_t)0x00000F00)
aravindsv 0:ba7650f404af 5392 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5393 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5394 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5395 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5396 #define RTC_DR_DT ((uint32_t)0x00000030)
aravindsv 0:ba7650f404af 5397 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5398 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5399 #define RTC_DR_DU ((uint32_t)0x0000000F)
aravindsv 0:ba7650f404af 5400 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5401 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5402 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5403 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5404
aravindsv 0:ba7650f404af 5405 /******************** Bits definition for RTC_CR register *******************/
aravindsv 0:ba7650f404af 5406 #define RTC_CR_COE ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5407 #define RTC_CR_OSEL ((uint32_t)0x00600000)
aravindsv 0:ba7650f404af 5408 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5409 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5410 #define RTC_CR_POL ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5411 #define RTC_CR_COSEL ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5412 #define RTC_CR_BCK ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5413 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5414 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5415 #define RTC_CR_TSIE ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5416 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5417 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5418 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5419 #define RTC_CR_TSE ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5420 #define RTC_CR_WUTE ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5421 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5422 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5423 #define RTC_CR_DCE ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5424 #define RTC_CR_FMT ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5425 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5426 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5427 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5428 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
aravindsv 0:ba7650f404af 5429 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5430 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5431 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5432
aravindsv 0:ba7650f404af 5433 /******************** Bits definition for RTC_ISR register ******************/
aravindsv 0:ba7650f404af 5434 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5435 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5436 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5437 #define RTC_ISR_TSF ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5438 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5439 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5440 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5441 #define RTC_ISR_INIT ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5442 #define RTC_ISR_INITF ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5443 #define RTC_ISR_RSF ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5444 #define RTC_ISR_INITS ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5445 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5446 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5447 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5448 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5449
aravindsv 0:ba7650f404af 5450 /******************** Bits definition for RTC_PRER register *****************/
aravindsv 0:ba7650f404af 5451 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
aravindsv 0:ba7650f404af 5452 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
aravindsv 0:ba7650f404af 5453
aravindsv 0:ba7650f404af 5454 /******************** Bits definition for RTC_WUTR register *****************/
aravindsv 0:ba7650f404af 5455 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
aravindsv 0:ba7650f404af 5456
aravindsv 0:ba7650f404af 5457 /******************** Bits definition for RTC_CALIBR register ***************/
aravindsv 0:ba7650f404af 5458 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5459 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
aravindsv 0:ba7650f404af 5460
aravindsv 0:ba7650f404af 5461 /******************** Bits definition for RTC_ALRMAR register ***************/
aravindsv 0:ba7650f404af 5462 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5463 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5464 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
aravindsv 0:ba7650f404af 5465 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5466 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5467 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
aravindsv 0:ba7650f404af 5468 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 5469 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5470 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5471 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 5472 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5473 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5474 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
aravindsv 0:ba7650f404af 5475 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5476 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5477 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
aravindsv 0:ba7650f404af 5478 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5479 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5480 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5481 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5482 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5483 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
aravindsv 0:ba7650f404af 5484 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5485 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5486 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5487 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
aravindsv 0:ba7650f404af 5488 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5489 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5490 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5491 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5492 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5493 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
aravindsv 0:ba7650f404af 5494 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5495 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5496 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5497 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
aravindsv 0:ba7650f404af 5498 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5499 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5500 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5501 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5502
aravindsv 0:ba7650f404af 5503 /******************** Bits definition for RTC_ALRMBR register ***************/
aravindsv 0:ba7650f404af 5504 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5505 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
aravindsv 0:ba7650f404af 5506 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
aravindsv 0:ba7650f404af 5507 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
aravindsv 0:ba7650f404af 5508 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
aravindsv 0:ba7650f404af 5509 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
aravindsv 0:ba7650f404af 5510 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 5511 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5512 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5513 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 5514 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 5515 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5516 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
aravindsv 0:ba7650f404af 5517 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5518 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5519 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
aravindsv 0:ba7650f404af 5520 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5521 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5522 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5523 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5524 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5525 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
aravindsv 0:ba7650f404af 5526 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5527 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5528 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5529 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
aravindsv 0:ba7650f404af 5530 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5531 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5532 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5533 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5534 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5535 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
aravindsv 0:ba7650f404af 5536 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5537 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5538 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5539 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
aravindsv 0:ba7650f404af 5540 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5541 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5542 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5543 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5544
aravindsv 0:ba7650f404af 5545 /******************** Bits definition for RTC_WPR register ******************/
aravindsv 0:ba7650f404af 5546 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
aravindsv 0:ba7650f404af 5547
aravindsv 0:ba7650f404af 5548 /******************** Bits definition for RTC_SSR register ******************/
aravindsv 0:ba7650f404af 5549 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
aravindsv 0:ba7650f404af 5550
aravindsv 0:ba7650f404af 5551 /******************** Bits definition for RTC_SHIFTR register ***************/
aravindsv 0:ba7650f404af 5552 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
aravindsv 0:ba7650f404af 5553 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
aravindsv 0:ba7650f404af 5554
aravindsv 0:ba7650f404af 5555 /******************** Bits definition for RTC_TSTR register *****************/
aravindsv 0:ba7650f404af 5556 #define RTC_TSTR_PM ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 5557 #define RTC_TSTR_HT ((uint32_t)0x00300000)
aravindsv 0:ba7650f404af 5558 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
aravindsv 0:ba7650f404af 5559 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 5560 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
aravindsv 0:ba7650f404af 5561 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5562 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5563 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5564 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
aravindsv 0:ba7650f404af 5565 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
aravindsv 0:ba7650f404af 5566 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5567 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5568 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5569 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
aravindsv 0:ba7650f404af 5570 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5571 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5572 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5573 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5574 #define RTC_TSTR_ST ((uint32_t)0x00000070)
aravindsv 0:ba7650f404af 5575 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5576 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5577 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5578 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
aravindsv 0:ba7650f404af 5579 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5580 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5581 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5582 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5583
aravindsv 0:ba7650f404af 5584 /******************** Bits definition for RTC_TSDR register *****************/
aravindsv 0:ba7650f404af 5585 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
aravindsv 0:ba7650f404af 5586 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5587 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5588 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5589 #define RTC_TSDR_MT ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5590 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
aravindsv 0:ba7650f404af 5591 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5592 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5593 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5594 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5595 #define RTC_TSDR_DT ((uint32_t)0x00000030)
aravindsv 0:ba7650f404af 5596 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5597 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5598 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
aravindsv 0:ba7650f404af 5599 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5600 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5601 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5602 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5603
aravindsv 0:ba7650f404af 5604 /******************** Bits definition for RTC_TSSSR register ****************/
aravindsv 0:ba7650f404af 5605 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
aravindsv 0:ba7650f404af 5606
aravindsv 0:ba7650f404af 5607 /******************** Bits definition for RTC_CAL register *****************/
aravindsv 0:ba7650f404af 5608 #define RTC_CALR_CALP ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5609 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5610 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5611 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
aravindsv 0:ba7650f404af 5612 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5613 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5614 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5615 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 5616 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 5617 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 5618 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 5619 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5620 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5621
aravindsv 0:ba7650f404af 5622 /******************** Bits definition for RTC_TAFCR register ****************/
aravindsv 0:ba7650f404af 5623 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 5624 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 5625 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 5626 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
aravindsv 0:ba7650f404af 5627 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
aravindsv 0:ba7650f404af 5628 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
aravindsv 0:ba7650f404af 5629 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
aravindsv 0:ba7650f404af 5630 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
aravindsv 0:ba7650f404af 5631 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 5632 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 5633 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
aravindsv 0:ba7650f404af 5634 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 5635 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
aravindsv 0:ba7650f404af 5636 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 5637 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 5638 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5639 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5640 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5641
aravindsv 0:ba7650f404af 5642 /******************** Bits definition for RTC_ALRMASSR register *************/
aravindsv 0:ba7650f404af 5643 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
aravindsv 0:ba7650f404af 5644 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 5645 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5646 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5647 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 5648 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
aravindsv 0:ba7650f404af 5649
aravindsv 0:ba7650f404af 5650 /******************** Bits definition for RTC_ALRMBSSR register *************/
aravindsv 0:ba7650f404af 5651 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
aravindsv 0:ba7650f404af 5652 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
aravindsv 0:ba7650f404af 5653 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 5654 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 5655 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
aravindsv 0:ba7650f404af 5656 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
aravindsv 0:ba7650f404af 5657
aravindsv 0:ba7650f404af 5658 /******************** Bits definition for RTC_BKP0R register ****************/
aravindsv 0:ba7650f404af 5659 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5660
aravindsv 0:ba7650f404af 5661 /******************** Bits definition for RTC_BKP1R register ****************/
aravindsv 0:ba7650f404af 5662 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5663
aravindsv 0:ba7650f404af 5664 /******************** Bits definition for RTC_BKP2R register ****************/
aravindsv 0:ba7650f404af 5665 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5666
aravindsv 0:ba7650f404af 5667 /******************** Bits definition for RTC_BKP3R register ****************/
aravindsv 0:ba7650f404af 5668 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5669
aravindsv 0:ba7650f404af 5670 /******************** Bits definition for RTC_BKP4R register ****************/
aravindsv 0:ba7650f404af 5671 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5672
aravindsv 0:ba7650f404af 5673 /******************** Bits definition for RTC_BKP5R register ****************/
aravindsv 0:ba7650f404af 5674 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5675
aravindsv 0:ba7650f404af 5676 /******************** Bits definition for RTC_BKP6R register ****************/
aravindsv 0:ba7650f404af 5677 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5678
aravindsv 0:ba7650f404af 5679 /******************** Bits definition for RTC_BKP7R register ****************/
aravindsv 0:ba7650f404af 5680 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5681
aravindsv 0:ba7650f404af 5682 /******************** Bits definition for RTC_BKP8R register ****************/
aravindsv 0:ba7650f404af 5683 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5684
aravindsv 0:ba7650f404af 5685 /******************** Bits definition for RTC_BKP9R register ****************/
aravindsv 0:ba7650f404af 5686 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5687
aravindsv 0:ba7650f404af 5688 /******************** Bits definition for RTC_BKP10R register ***************/
aravindsv 0:ba7650f404af 5689 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5690
aravindsv 0:ba7650f404af 5691 /******************** Bits definition for RTC_BKP11R register ***************/
aravindsv 0:ba7650f404af 5692 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5693
aravindsv 0:ba7650f404af 5694 /******************** Bits definition for RTC_BKP12R register ***************/
aravindsv 0:ba7650f404af 5695 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5696
aravindsv 0:ba7650f404af 5697 /******************** Bits definition for RTC_BKP13R register ***************/
aravindsv 0:ba7650f404af 5698 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5699
aravindsv 0:ba7650f404af 5700 /******************** Bits definition for RTC_BKP14R register ***************/
aravindsv 0:ba7650f404af 5701 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5702
aravindsv 0:ba7650f404af 5703 /******************** Bits definition for RTC_BKP15R register ***************/
aravindsv 0:ba7650f404af 5704 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5705
aravindsv 0:ba7650f404af 5706 /******************** Bits definition for RTC_BKP16R register ***************/
aravindsv 0:ba7650f404af 5707 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5708
aravindsv 0:ba7650f404af 5709 /******************** Bits definition for RTC_BKP17R register ***************/
aravindsv 0:ba7650f404af 5710 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5711
aravindsv 0:ba7650f404af 5712 /******************** Bits definition for RTC_BKP18R register ***************/
aravindsv 0:ba7650f404af 5713 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5714
aravindsv 0:ba7650f404af 5715 /******************** Bits definition for RTC_BKP19R register ***************/
aravindsv 0:ba7650f404af 5716 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
aravindsv 0:ba7650f404af 5717
aravindsv 0:ba7650f404af 5718
aravindsv 0:ba7650f404af 5719 /******************************************************************************/
aravindsv 0:ba7650f404af 5720 /* */
aravindsv 0:ba7650f404af 5721 /* SD host Interface */
aravindsv 0:ba7650f404af 5722 /* */
aravindsv 0:ba7650f404af 5723 /******************************************************************************/
aravindsv 0:ba7650f404af 5724 /****************** Bit definition for SDIO_POWER register ******************/
aravindsv 0:ba7650f404af 5725 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
aravindsv 0:ba7650f404af 5726 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */
aravindsv 0:ba7650f404af 5727 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */
aravindsv 0:ba7650f404af 5728
aravindsv 0:ba7650f404af 5729 /****************** Bit definition for SDIO_CLKCR register ******************/
aravindsv 0:ba7650f404af 5730 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */
aravindsv 0:ba7650f404af 5731 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */
aravindsv 0:ba7650f404af 5732 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */
aravindsv 0:ba7650f404af 5733 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */
aravindsv 0:ba7650f404af 5734
aravindsv 0:ba7650f404af 5735 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
aravindsv 0:ba7650f404af 5736 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */
aravindsv 0:ba7650f404af 5737 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 5738
aravindsv 0:ba7650f404af 5739 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */
aravindsv 0:ba7650f404af 5740 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */
aravindsv 0:ba7650f404af 5741
aravindsv 0:ba7650f404af 5742 /******************* Bit definition for SDIO_ARG register *******************/
aravindsv 0:ba7650f404af 5743 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
aravindsv 0:ba7650f404af 5744
aravindsv 0:ba7650f404af 5745 /******************* Bit definition for SDIO_CMD register *******************/
aravindsv 0:ba7650f404af 5746 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */
aravindsv 0:ba7650f404af 5747
aravindsv 0:ba7650f404af 5748 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
aravindsv 0:ba7650f404af 5749 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
aravindsv 0:ba7650f404af 5750 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
aravindsv 0:ba7650f404af 5751
aravindsv 0:ba7650f404af 5752 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */
aravindsv 0:ba7650f404af 5753 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
aravindsv 0:ba7650f404af 5754 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
aravindsv 0:ba7650f404af 5755 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */
aravindsv 0:ba7650f404af 5756 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */
aravindsv 0:ba7650f404af 5757 #define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */
aravindsv 0:ba7650f404af 5758 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */
aravindsv 0:ba7650f404af 5759
aravindsv 0:ba7650f404af 5760 /***************** Bit definition for SDIO_RESPCMD register *****************/
aravindsv 0:ba7650f404af 5761 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */
aravindsv 0:ba7650f404af 5762
aravindsv 0:ba7650f404af 5763 /****************** Bit definition for SDIO_RESP0 register ******************/
aravindsv 0:ba7650f404af 5764 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
aravindsv 0:ba7650f404af 5765
aravindsv 0:ba7650f404af 5766 /****************** Bit definition for SDIO_RESP1 register ******************/
aravindsv 0:ba7650f404af 5767 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
aravindsv 0:ba7650f404af 5768
aravindsv 0:ba7650f404af 5769 /****************** Bit definition for SDIO_RESP2 register ******************/
aravindsv 0:ba7650f404af 5770 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
aravindsv 0:ba7650f404af 5771
aravindsv 0:ba7650f404af 5772 /****************** Bit definition for SDIO_RESP3 register ******************/
aravindsv 0:ba7650f404af 5773 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
aravindsv 0:ba7650f404af 5774
aravindsv 0:ba7650f404af 5775 /****************** Bit definition for SDIO_RESP4 register ******************/
aravindsv 0:ba7650f404af 5776 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
aravindsv 0:ba7650f404af 5777
aravindsv 0:ba7650f404af 5778 /****************** Bit definition for SDIO_DTIMER register *****************/
aravindsv 0:ba7650f404af 5779 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
aravindsv 0:ba7650f404af 5780
aravindsv 0:ba7650f404af 5781 /****************** Bit definition for SDIO_DLEN register *******************/
aravindsv 0:ba7650f404af 5782 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
aravindsv 0:ba7650f404af 5783
aravindsv 0:ba7650f404af 5784 /****************** Bit definition for SDIO_DCTRL register ******************/
aravindsv 0:ba7650f404af 5785 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */
aravindsv 0:ba7650f404af 5786 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */
aravindsv 0:ba7650f404af 5787 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */
aravindsv 0:ba7650f404af 5788 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */
aravindsv 0:ba7650f404af 5789
aravindsv 0:ba7650f404af 5790 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
aravindsv 0:ba7650f404af 5791 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 5792 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 5793 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 5794 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 5795
aravindsv 0:ba7650f404af 5796 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */
aravindsv 0:ba7650f404af 5797 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */
aravindsv 0:ba7650f404af 5798 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */
aravindsv 0:ba7650f404af 5799 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */
aravindsv 0:ba7650f404af 5800
aravindsv 0:ba7650f404af 5801 /****************** Bit definition for SDIO_DCOUNT register *****************/
aravindsv 0:ba7650f404af 5802 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
aravindsv 0:ba7650f404af 5803
aravindsv 0:ba7650f404af 5804 /****************** Bit definition for SDIO_STA register ********************/
aravindsv 0:ba7650f404af 5805 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
aravindsv 0:ba7650f404af 5806 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
aravindsv 0:ba7650f404af 5807 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
aravindsv 0:ba7650f404af 5808 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
aravindsv 0:ba7650f404af 5809 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
aravindsv 0:ba7650f404af 5810 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
aravindsv 0:ba7650f404af 5811 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
aravindsv 0:ba7650f404af 5812 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
aravindsv 0:ba7650f404af 5813 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
aravindsv 0:ba7650f404af 5814 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
aravindsv 0:ba7650f404af 5815 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
aravindsv 0:ba7650f404af 5816 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
aravindsv 0:ba7650f404af 5817 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
aravindsv 0:ba7650f404af 5818 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
aravindsv 0:ba7650f404af 5819 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
aravindsv 0:ba7650f404af 5820 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
aravindsv 0:ba7650f404af 5821 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
aravindsv 0:ba7650f404af 5822 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
aravindsv 0:ba7650f404af 5823 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
aravindsv 0:ba7650f404af 5824 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
aravindsv 0:ba7650f404af 5825 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
aravindsv 0:ba7650f404af 5826 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
aravindsv 0:ba7650f404af 5827 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
aravindsv 0:ba7650f404af 5828 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
aravindsv 0:ba7650f404af 5829
aravindsv 0:ba7650f404af 5830 /******************* Bit definition for SDIO_ICR register *******************/
aravindsv 0:ba7650f404af 5831 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
aravindsv 0:ba7650f404af 5832 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
aravindsv 0:ba7650f404af 5833 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
aravindsv 0:ba7650f404af 5834 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
aravindsv 0:ba7650f404af 5835 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
aravindsv 0:ba7650f404af 5836 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
aravindsv 0:ba7650f404af 5837 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
aravindsv 0:ba7650f404af 5838 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
aravindsv 0:ba7650f404af 5839 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
aravindsv 0:ba7650f404af 5840 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
aravindsv 0:ba7650f404af 5841 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
aravindsv 0:ba7650f404af 5842 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
aravindsv 0:ba7650f404af 5843 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
aravindsv 0:ba7650f404af 5844
aravindsv 0:ba7650f404af 5845 /****************** Bit definition for SDIO_MASK register *******************/
aravindsv 0:ba7650f404af 5846 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
aravindsv 0:ba7650f404af 5847 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
aravindsv 0:ba7650f404af 5848 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
aravindsv 0:ba7650f404af 5849 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
aravindsv 0:ba7650f404af 5850 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
aravindsv 0:ba7650f404af 5851 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
aravindsv 0:ba7650f404af 5852 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
aravindsv 0:ba7650f404af 5853 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
aravindsv 0:ba7650f404af 5854 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
aravindsv 0:ba7650f404af 5855 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
aravindsv 0:ba7650f404af 5856 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
aravindsv 0:ba7650f404af 5857 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
aravindsv 0:ba7650f404af 5858 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
aravindsv 0:ba7650f404af 5859 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
aravindsv 0:ba7650f404af 5860 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
aravindsv 0:ba7650f404af 5861 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
aravindsv 0:ba7650f404af 5862 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
aravindsv 0:ba7650f404af 5863 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
aravindsv 0:ba7650f404af 5864 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
aravindsv 0:ba7650f404af 5865 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
aravindsv 0:ba7650f404af 5866 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
aravindsv 0:ba7650f404af 5867 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
aravindsv 0:ba7650f404af 5868 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
aravindsv 0:ba7650f404af 5869 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
aravindsv 0:ba7650f404af 5870
aravindsv 0:ba7650f404af 5871 /***************** Bit definition for SDIO_FIFOCNT register *****************/
aravindsv 0:ba7650f404af 5872 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
aravindsv 0:ba7650f404af 5873
aravindsv 0:ba7650f404af 5874 /****************** Bit definition for SDIO_FIFO register *******************/
aravindsv 0:ba7650f404af 5875 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
aravindsv 0:ba7650f404af 5876
aravindsv 0:ba7650f404af 5877 /******************************************************************************/
aravindsv 0:ba7650f404af 5878 /* */
aravindsv 0:ba7650f404af 5879 /* Serial Peripheral Interface */
aravindsv 0:ba7650f404af 5880 /* */
aravindsv 0:ba7650f404af 5881 /******************************************************************************/
aravindsv 0:ba7650f404af 5882 /******************* Bit definition for SPI_CR1 register ********************/
aravindsv 0:ba7650f404af 5883 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */
aravindsv 0:ba7650f404af 5884 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */
aravindsv 0:ba7650f404af 5885 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */
aravindsv 0:ba7650f404af 5886
aravindsv 0:ba7650f404af 5887 #define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */
aravindsv 0:ba7650f404af 5888 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */
aravindsv 0:ba7650f404af 5889 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */
aravindsv 0:ba7650f404af 5890 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */
aravindsv 0:ba7650f404af 5891
aravindsv 0:ba7650f404af 5892 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */
aravindsv 0:ba7650f404af 5893 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */
aravindsv 0:ba7650f404af 5894 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */
aravindsv 0:ba7650f404af 5895 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */
aravindsv 0:ba7650f404af 5896 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */
aravindsv 0:ba7650f404af 5897 #define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */
aravindsv 0:ba7650f404af 5898 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */
aravindsv 0:ba7650f404af 5899 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */
aravindsv 0:ba7650f404af 5900 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */
aravindsv 0:ba7650f404af 5901 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */
aravindsv 0:ba7650f404af 5902
aravindsv 0:ba7650f404af 5903 /******************* Bit definition for SPI_CR2 register ********************/
aravindsv 0:ba7650f404af 5904 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */
aravindsv 0:ba7650f404af 5905 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */
aravindsv 0:ba7650f404af 5906 #define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */
aravindsv 0:ba7650f404af 5907 #define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */
aravindsv 0:ba7650f404af 5908 #define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */
aravindsv 0:ba7650f404af 5909 #define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */
aravindsv 0:ba7650f404af 5910
aravindsv 0:ba7650f404af 5911 /******************** Bit definition for SPI_SR register ********************/
aravindsv 0:ba7650f404af 5912 #define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */
aravindsv 0:ba7650f404af 5913 #define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */
aravindsv 0:ba7650f404af 5914 #define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */
aravindsv 0:ba7650f404af 5915 #define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */
aravindsv 0:ba7650f404af 5916 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */
aravindsv 0:ba7650f404af 5917 #define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */
aravindsv 0:ba7650f404af 5918 #define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */
aravindsv 0:ba7650f404af 5919 #define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */
aravindsv 0:ba7650f404af 5920
aravindsv 0:ba7650f404af 5921 /******************** Bit definition for SPI_DR register ********************/
aravindsv 0:ba7650f404af 5922 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */
aravindsv 0:ba7650f404af 5923
aravindsv 0:ba7650f404af 5924 /******************* Bit definition for SPI_CRCPR register ******************/
aravindsv 0:ba7650f404af 5925 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */
aravindsv 0:ba7650f404af 5926
aravindsv 0:ba7650f404af 5927 /****************** Bit definition for SPI_RXCRCR register ******************/
aravindsv 0:ba7650f404af 5928 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */
aravindsv 0:ba7650f404af 5929
aravindsv 0:ba7650f404af 5930 /****************** Bit definition for SPI_TXCRCR register ******************/
aravindsv 0:ba7650f404af 5931 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */
aravindsv 0:ba7650f404af 5932
aravindsv 0:ba7650f404af 5933 /****************** Bit definition for SPI_I2SCFGR register *****************/
aravindsv 0:ba7650f404af 5934 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
aravindsv 0:ba7650f404af 5935
aravindsv 0:ba7650f404af 5936 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
aravindsv 0:ba7650f404af 5937 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
aravindsv 0:ba7650f404af 5938 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
aravindsv 0:ba7650f404af 5939
aravindsv 0:ba7650f404af 5940 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
aravindsv 0:ba7650f404af 5941
aravindsv 0:ba7650f404af 5942 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
aravindsv 0:ba7650f404af 5943 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 5944 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 5945
aravindsv 0:ba7650f404af 5946 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
aravindsv 0:ba7650f404af 5947
aravindsv 0:ba7650f404af 5948 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
aravindsv 0:ba7650f404af 5949 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 5950 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 5951
aravindsv 0:ba7650f404af 5952 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
aravindsv 0:ba7650f404af 5953 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
aravindsv 0:ba7650f404af 5954
aravindsv 0:ba7650f404af 5955 /****************** Bit definition for SPI_I2SPR register *******************/
aravindsv 0:ba7650f404af 5956 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
aravindsv 0:ba7650f404af 5957 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
aravindsv 0:ba7650f404af 5958 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
aravindsv 0:ba7650f404af 5959
aravindsv 0:ba7650f404af 5960 /******************************************************************************/
aravindsv 0:ba7650f404af 5961 /* */
aravindsv 0:ba7650f404af 5962 /* SYSCFG */
aravindsv 0:ba7650f404af 5963 /* */
aravindsv 0:ba7650f404af 5964 /******************************************************************************/
aravindsv 0:ba7650f404af 5965 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
aravindsv 0:ba7650f404af 5966 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
aravindsv 0:ba7650f404af 5967 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 5968 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 5969 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 5970
aravindsv 0:ba7650f404af 5971 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
aravindsv 0:ba7650f404af 5972
aravindsv 0:ba7650f404af 5973 /****************** Bit definition for SYSCFG_PMC register ******************/
aravindsv 0:ba7650f404af 5974 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
aravindsv 0:ba7650f404af 5975 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
aravindsv 0:ba7650f404af 5976 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
aravindsv 0:ba7650f404af 5977
aravindsv 0:ba7650f404af 5978 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
aravindsv 0:ba7650f404af 5979 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
aravindsv 0:ba7650f404af 5980 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */
aravindsv 0:ba7650f404af 5981 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */
aravindsv 0:ba7650f404af 5982 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */
aravindsv 0:ba7650f404af 5983 /**
aravindsv 0:ba7650f404af 5984 * @brief EXTI0 configuration
aravindsv 0:ba7650f404af 5985 */
aravindsv 0:ba7650f404af 5986 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */
aravindsv 0:ba7650f404af 5987 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */
aravindsv 0:ba7650f404af 5988 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */
aravindsv 0:ba7650f404af 5989 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */
aravindsv 0:ba7650f404af 5990 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */
aravindsv 0:ba7650f404af 5991 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */
aravindsv 0:ba7650f404af 5992 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */
aravindsv 0:ba7650f404af 5993 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */
aravindsv 0:ba7650f404af 5994 #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */
aravindsv 0:ba7650f404af 5995
aravindsv 0:ba7650f404af 5996 /**
aravindsv 0:ba7650f404af 5997 * @brief EXTI1 configuration
aravindsv 0:ba7650f404af 5998 */
aravindsv 0:ba7650f404af 5999 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */
aravindsv 0:ba7650f404af 6000 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */
aravindsv 0:ba7650f404af 6001 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */
aravindsv 0:ba7650f404af 6002 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */
aravindsv 0:ba7650f404af 6003 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */
aravindsv 0:ba7650f404af 6004 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */
aravindsv 0:ba7650f404af 6005 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */
aravindsv 0:ba7650f404af 6006 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */
aravindsv 0:ba7650f404af 6007 #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */
aravindsv 0:ba7650f404af 6008
aravindsv 0:ba7650f404af 6009 /**
aravindsv 0:ba7650f404af 6010 * @brief EXTI2 configuration
aravindsv 0:ba7650f404af 6011 */
aravindsv 0:ba7650f404af 6012 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */
aravindsv 0:ba7650f404af 6013 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */
aravindsv 0:ba7650f404af 6014 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */
aravindsv 0:ba7650f404af 6015 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */
aravindsv 0:ba7650f404af 6016 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */
aravindsv 0:ba7650f404af 6017 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */
aravindsv 0:ba7650f404af 6018 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */
aravindsv 0:ba7650f404af 6019 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */
aravindsv 0:ba7650f404af 6020 #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */
aravindsv 0:ba7650f404af 6021
aravindsv 0:ba7650f404af 6022 /**
aravindsv 0:ba7650f404af 6023 * @brief EXTI3 configuration
aravindsv 0:ba7650f404af 6024 */
aravindsv 0:ba7650f404af 6025 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */
aravindsv 0:ba7650f404af 6026 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */
aravindsv 0:ba7650f404af 6027 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */
aravindsv 0:ba7650f404af 6028 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */
aravindsv 0:ba7650f404af 6029 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */
aravindsv 0:ba7650f404af 6030 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */
aravindsv 0:ba7650f404af 6031 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */
aravindsv 0:ba7650f404af 6032 #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */
aravindsv 0:ba7650f404af 6033 #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */
aravindsv 0:ba7650f404af 6034
aravindsv 0:ba7650f404af 6035 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
aravindsv 0:ba7650f404af 6036 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */
aravindsv 0:ba7650f404af 6037 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */
aravindsv 0:ba7650f404af 6038 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */
aravindsv 0:ba7650f404af 6039 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */
aravindsv 0:ba7650f404af 6040 /**
aravindsv 0:ba7650f404af 6041 * @brief EXTI4 configuration
aravindsv 0:ba7650f404af 6042 */
aravindsv 0:ba7650f404af 6043 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */
aravindsv 0:ba7650f404af 6044 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */
aravindsv 0:ba7650f404af 6045 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */
aravindsv 0:ba7650f404af 6046 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */
aravindsv 0:ba7650f404af 6047 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */
aravindsv 0:ba7650f404af 6048 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */
aravindsv 0:ba7650f404af 6049 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */
aravindsv 0:ba7650f404af 6050 #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */
aravindsv 0:ba7650f404af 6051 #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */
aravindsv 0:ba7650f404af 6052
aravindsv 0:ba7650f404af 6053 /**
aravindsv 0:ba7650f404af 6054 * @brief EXTI5 configuration
aravindsv 0:ba7650f404af 6055 */
aravindsv 0:ba7650f404af 6056 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */
aravindsv 0:ba7650f404af 6057 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */
aravindsv 0:ba7650f404af 6058 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */
aravindsv 0:ba7650f404af 6059 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */
aravindsv 0:ba7650f404af 6060 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */
aravindsv 0:ba7650f404af 6061 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */
aravindsv 0:ba7650f404af 6062 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */
aravindsv 0:ba7650f404af 6063 #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */
aravindsv 0:ba7650f404af 6064 #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */
aravindsv 0:ba7650f404af 6065
aravindsv 0:ba7650f404af 6066 /**
aravindsv 0:ba7650f404af 6067 * @brief EXTI6 configuration
aravindsv 0:ba7650f404af 6068 */
aravindsv 0:ba7650f404af 6069 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */
aravindsv 0:ba7650f404af 6070 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */
aravindsv 0:ba7650f404af 6071 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */
aravindsv 0:ba7650f404af 6072 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */
aravindsv 0:ba7650f404af 6073 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */
aravindsv 0:ba7650f404af 6074 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */
aravindsv 0:ba7650f404af 6075 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */
aravindsv 0:ba7650f404af 6076 #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */
aravindsv 0:ba7650f404af 6077 #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */
aravindsv 0:ba7650f404af 6078
aravindsv 0:ba7650f404af 6079 /**
aravindsv 0:ba7650f404af 6080 * @brief EXTI7 configuration
aravindsv 0:ba7650f404af 6081 */
aravindsv 0:ba7650f404af 6082 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */
aravindsv 0:ba7650f404af 6083 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */
aravindsv 0:ba7650f404af 6084 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */
aravindsv 0:ba7650f404af 6085 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */
aravindsv 0:ba7650f404af 6086 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */
aravindsv 0:ba7650f404af 6087 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */
aravindsv 0:ba7650f404af 6088 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */
aravindsv 0:ba7650f404af 6089 #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */
aravindsv 0:ba7650f404af 6090 #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */
aravindsv 0:ba7650f404af 6091
aravindsv 0:ba7650f404af 6092 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
aravindsv 0:ba7650f404af 6093 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */
aravindsv 0:ba7650f404af 6094 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */
aravindsv 0:ba7650f404af 6095 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */
aravindsv 0:ba7650f404af 6096 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */
aravindsv 0:ba7650f404af 6097
aravindsv 0:ba7650f404af 6098 /**
aravindsv 0:ba7650f404af 6099 * @brief EXTI8 configuration
aravindsv 0:ba7650f404af 6100 */
aravindsv 0:ba7650f404af 6101 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */
aravindsv 0:ba7650f404af 6102 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */
aravindsv 0:ba7650f404af 6103 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */
aravindsv 0:ba7650f404af 6104 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */
aravindsv 0:ba7650f404af 6105 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */
aravindsv 0:ba7650f404af 6106 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */
aravindsv 0:ba7650f404af 6107 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */
aravindsv 0:ba7650f404af 6108 #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */
aravindsv 0:ba7650f404af 6109 #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */
aravindsv 0:ba7650f404af 6110
aravindsv 0:ba7650f404af 6111 /**
aravindsv 0:ba7650f404af 6112 * @brief EXTI9 configuration
aravindsv 0:ba7650f404af 6113 */
aravindsv 0:ba7650f404af 6114 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */
aravindsv 0:ba7650f404af 6115 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */
aravindsv 0:ba7650f404af 6116 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */
aravindsv 0:ba7650f404af 6117 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */
aravindsv 0:ba7650f404af 6118 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */
aravindsv 0:ba7650f404af 6119 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */
aravindsv 0:ba7650f404af 6120 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */
aravindsv 0:ba7650f404af 6121 #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */
aravindsv 0:ba7650f404af 6122 #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */
aravindsv 0:ba7650f404af 6123
aravindsv 0:ba7650f404af 6124 /**
aravindsv 0:ba7650f404af 6125 * @brief EXTI10 configuration
aravindsv 0:ba7650f404af 6126 */
aravindsv 0:ba7650f404af 6127 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */
aravindsv 0:ba7650f404af 6128 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */
aravindsv 0:ba7650f404af 6129 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */
aravindsv 0:ba7650f404af 6130 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */
aravindsv 0:ba7650f404af 6131 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */
aravindsv 0:ba7650f404af 6132 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */
aravindsv 0:ba7650f404af 6133 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */
aravindsv 0:ba7650f404af 6134 #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */
aravindsv 0:ba7650f404af 6135 #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */
aravindsv 0:ba7650f404af 6136
aravindsv 0:ba7650f404af 6137 /**
aravindsv 0:ba7650f404af 6138 * @brief EXTI11 configuration
aravindsv 0:ba7650f404af 6139 */
aravindsv 0:ba7650f404af 6140 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */
aravindsv 0:ba7650f404af 6141 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */
aravindsv 0:ba7650f404af 6142 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */
aravindsv 0:ba7650f404af 6143 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */
aravindsv 0:ba7650f404af 6144 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */
aravindsv 0:ba7650f404af 6145 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */
aravindsv 0:ba7650f404af 6146 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */
aravindsv 0:ba7650f404af 6147 #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */
aravindsv 0:ba7650f404af 6148 #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */
aravindsv 0:ba7650f404af 6149
aravindsv 0:ba7650f404af 6150 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
aravindsv 0:ba7650f404af 6151 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */
aravindsv 0:ba7650f404af 6152 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */
aravindsv 0:ba7650f404af 6153 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */
aravindsv 0:ba7650f404af 6154 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */
aravindsv 0:ba7650f404af 6155 /**
aravindsv 0:ba7650f404af 6156 * @brief EXTI12 configuration
aravindsv 0:ba7650f404af 6157 */
aravindsv 0:ba7650f404af 6158 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */
aravindsv 0:ba7650f404af 6159 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */
aravindsv 0:ba7650f404af 6160 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */
aravindsv 0:ba7650f404af 6161 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */
aravindsv 0:ba7650f404af 6162 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */
aravindsv 0:ba7650f404af 6163 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */
aravindsv 0:ba7650f404af 6164 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */
aravindsv 0:ba7650f404af 6165 #define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */
aravindsv 0:ba7650f404af 6166
aravindsv 0:ba7650f404af 6167 /**
aravindsv 0:ba7650f404af 6168 * @brief EXTI13 configuration
aravindsv 0:ba7650f404af 6169 */
aravindsv 0:ba7650f404af 6170 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */
aravindsv 0:ba7650f404af 6171 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */
aravindsv 0:ba7650f404af 6172 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */
aravindsv 0:ba7650f404af 6173 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */
aravindsv 0:ba7650f404af 6174 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */
aravindsv 0:ba7650f404af 6175 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */
aravindsv 0:ba7650f404af 6176 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */
aravindsv 0:ba7650f404af 6177 #define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */
aravindsv 0:ba7650f404af 6178
aravindsv 0:ba7650f404af 6179 /**
aravindsv 0:ba7650f404af 6180 * @brief EXTI14 configuration
aravindsv 0:ba7650f404af 6181 */
aravindsv 0:ba7650f404af 6182 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */
aravindsv 0:ba7650f404af 6183 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */
aravindsv 0:ba7650f404af 6184 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */
aravindsv 0:ba7650f404af 6185 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */
aravindsv 0:ba7650f404af 6186 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */
aravindsv 0:ba7650f404af 6187 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */
aravindsv 0:ba7650f404af 6188 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */
aravindsv 0:ba7650f404af 6189 #define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */
aravindsv 0:ba7650f404af 6190
aravindsv 0:ba7650f404af 6191 /**
aravindsv 0:ba7650f404af 6192 * @brief EXTI15 configuration
aravindsv 0:ba7650f404af 6193 */
aravindsv 0:ba7650f404af 6194 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */
aravindsv 0:ba7650f404af 6195 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */
aravindsv 0:ba7650f404af 6196 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */
aravindsv 0:ba7650f404af 6197 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */
aravindsv 0:ba7650f404af 6198 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */
aravindsv 0:ba7650f404af 6199 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */
aravindsv 0:ba7650f404af 6200 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */
aravindsv 0:ba7650f404af 6201 #define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */
aravindsv 0:ba7650f404af 6202
aravindsv 0:ba7650f404af 6203 /****************** Bit definition for SYSCFG_CMPCR register ****************/
aravindsv 0:ba7650f404af 6204 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
aravindsv 0:ba7650f404af 6205 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
aravindsv 0:ba7650f404af 6206
aravindsv 0:ba7650f404af 6207 /******************************************************************************/
aravindsv 0:ba7650f404af 6208 /* */
aravindsv 0:ba7650f404af 6209 /* TIM */
aravindsv 0:ba7650f404af 6210 /* */
aravindsv 0:ba7650f404af 6211 /******************************************************************************/
aravindsv 0:ba7650f404af 6212 /******************* Bit definition for TIM_CR1 register ********************/
aravindsv 0:ba7650f404af 6213 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
aravindsv 0:ba7650f404af 6214 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
aravindsv 0:ba7650f404af 6215 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
aravindsv 0:ba7650f404af 6216 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
aravindsv 0:ba7650f404af 6217 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
aravindsv 0:ba7650f404af 6218
aravindsv 0:ba7650f404af 6219 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
aravindsv 0:ba7650f404af 6220 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6221 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6222
aravindsv 0:ba7650f404af 6223 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
aravindsv 0:ba7650f404af 6224
aravindsv 0:ba7650f404af 6225 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
aravindsv 0:ba7650f404af 6226 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6227 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6228
aravindsv 0:ba7650f404af 6229 /******************* Bit definition for TIM_CR2 register ********************/
aravindsv 0:ba7650f404af 6230 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
aravindsv 0:ba7650f404af 6231 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
aravindsv 0:ba7650f404af 6232 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
aravindsv 0:ba7650f404af 6233
aravindsv 0:ba7650f404af 6234 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
aravindsv 0:ba7650f404af 6235 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6236 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6237 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6238
aravindsv 0:ba7650f404af 6239 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
aravindsv 0:ba7650f404af 6240 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
aravindsv 0:ba7650f404af 6241 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
aravindsv 0:ba7650f404af 6242 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
aravindsv 0:ba7650f404af 6243 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
aravindsv 0:ba7650f404af 6244 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
aravindsv 0:ba7650f404af 6245 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
aravindsv 0:ba7650f404af 6246 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
aravindsv 0:ba7650f404af 6247
aravindsv 0:ba7650f404af 6248 /******************* Bit definition for TIM_SMCR register *******************/
aravindsv 0:ba7650f404af 6249 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
aravindsv 0:ba7650f404af 6250 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6251 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6252 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6253
aravindsv 0:ba7650f404af 6254 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
aravindsv 0:ba7650f404af 6255 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6256 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6257 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6258
aravindsv 0:ba7650f404af 6259 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
aravindsv 0:ba7650f404af 6260
aravindsv 0:ba7650f404af 6261 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
aravindsv 0:ba7650f404af 6262 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6263 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6264 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6265 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6266
aravindsv 0:ba7650f404af 6267 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
aravindsv 0:ba7650f404af 6268 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6269 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6270
aravindsv 0:ba7650f404af 6271 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
aravindsv 0:ba7650f404af 6272 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
aravindsv 0:ba7650f404af 6273
aravindsv 0:ba7650f404af 6274 /******************* Bit definition for TIM_DIER register *******************/
aravindsv 0:ba7650f404af 6275 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
aravindsv 0:ba7650f404af 6276 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
aravindsv 0:ba7650f404af 6277 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
aravindsv 0:ba7650f404af 6278 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
aravindsv 0:ba7650f404af 6279 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
aravindsv 0:ba7650f404af 6280 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
aravindsv 0:ba7650f404af 6281 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
aravindsv 0:ba7650f404af 6282 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
aravindsv 0:ba7650f404af 6283 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
aravindsv 0:ba7650f404af 6284 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
aravindsv 0:ba7650f404af 6285 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
aravindsv 0:ba7650f404af 6286 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
aravindsv 0:ba7650f404af 6287 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
aravindsv 0:ba7650f404af 6288 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
aravindsv 0:ba7650f404af 6289 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
aravindsv 0:ba7650f404af 6290
aravindsv 0:ba7650f404af 6291 /******************** Bit definition for TIM_SR register ********************/
aravindsv 0:ba7650f404af 6292 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
aravindsv 0:ba7650f404af 6293 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
aravindsv 0:ba7650f404af 6294 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
aravindsv 0:ba7650f404af 6295 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
aravindsv 0:ba7650f404af 6296 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
aravindsv 0:ba7650f404af 6297 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
aravindsv 0:ba7650f404af 6298 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
aravindsv 0:ba7650f404af 6299 #define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
aravindsv 0:ba7650f404af 6300 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
aravindsv 0:ba7650f404af 6301 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
aravindsv 0:ba7650f404af 6302 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
aravindsv 0:ba7650f404af 6303 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
aravindsv 0:ba7650f404af 6304
aravindsv 0:ba7650f404af 6305 /******************* Bit definition for TIM_EGR register ********************/
aravindsv 0:ba7650f404af 6306 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
aravindsv 0:ba7650f404af 6307 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
aravindsv 0:ba7650f404af 6308 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
aravindsv 0:ba7650f404af 6309 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
aravindsv 0:ba7650f404af 6310 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
aravindsv 0:ba7650f404af 6311 #define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
aravindsv 0:ba7650f404af 6312 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
aravindsv 0:ba7650f404af 6313 #define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
aravindsv 0:ba7650f404af 6314
aravindsv 0:ba7650f404af 6315 /****************** Bit definition for TIM_CCMR1 register *******************/
aravindsv 0:ba7650f404af 6316 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
aravindsv 0:ba7650f404af 6317 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6318 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6319
aravindsv 0:ba7650f404af 6320 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
aravindsv 0:ba7650f404af 6321 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
aravindsv 0:ba7650f404af 6322
aravindsv 0:ba7650f404af 6323 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
aravindsv 0:ba7650f404af 6324 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6325 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6326 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6327
aravindsv 0:ba7650f404af 6328 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
aravindsv 0:ba7650f404af 6329
aravindsv 0:ba7650f404af 6330 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
aravindsv 0:ba7650f404af 6331 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6332 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6333
aravindsv 0:ba7650f404af 6334 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
aravindsv 0:ba7650f404af 6335 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
aravindsv 0:ba7650f404af 6336
aravindsv 0:ba7650f404af 6337 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
aravindsv 0:ba7650f404af 6338 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6339 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6340 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6341
aravindsv 0:ba7650f404af 6342 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
aravindsv 0:ba7650f404af 6343
aravindsv 0:ba7650f404af 6344 /*----------------------------------------------------------------------------*/
aravindsv 0:ba7650f404af 6345
aravindsv 0:ba7650f404af 6346 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
aravindsv 0:ba7650f404af 6347 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6348 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6349
aravindsv 0:ba7650f404af 6350 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
aravindsv 0:ba7650f404af 6351 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6352 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6353 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6354 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6355
aravindsv 0:ba7650f404af 6356 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
aravindsv 0:ba7650f404af 6357 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6358 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6359
aravindsv 0:ba7650f404af 6360 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
aravindsv 0:ba7650f404af 6361 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6362 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6363 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6364 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6365
aravindsv 0:ba7650f404af 6366 /****************** Bit definition for TIM_CCMR2 register *******************/
aravindsv 0:ba7650f404af 6367 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
aravindsv 0:ba7650f404af 6368 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6369 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6370
aravindsv 0:ba7650f404af 6371 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
aravindsv 0:ba7650f404af 6372 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
aravindsv 0:ba7650f404af 6373
aravindsv 0:ba7650f404af 6374 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
aravindsv 0:ba7650f404af 6375 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6376 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6377 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6378
aravindsv 0:ba7650f404af 6379 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
aravindsv 0:ba7650f404af 6380
aravindsv 0:ba7650f404af 6381 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
aravindsv 0:ba7650f404af 6382 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6383 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6384
aravindsv 0:ba7650f404af 6385 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
aravindsv 0:ba7650f404af 6386 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
aravindsv 0:ba7650f404af 6387
aravindsv 0:ba7650f404af 6388 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
aravindsv 0:ba7650f404af 6389 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6390 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6391 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6392
aravindsv 0:ba7650f404af 6393 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
aravindsv 0:ba7650f404af 6394
aravindsv 0:ba7650f404af 6395 /*----------------------------------------------------------------------------*/
aravindsv 0:ba7650f404af 6396
aravindsv 0:ba7650f404af 6397 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
aravindsv 0:ba7650f404af 6398 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6399 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6400
aravindsv 0:ba7650f404af 6401 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
aravindsv 0:ba7650f404af 6402 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6403 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6404 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6405 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6406
aravindsv 0:ba7650f404af 6407 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
aravindsv 0:ba7650f404af 6408 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6409 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6410
aravindsv 0:ba7650f404af 6411 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
aravindsv 0:ba7650f404af 6412 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6413 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6414 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6415 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6416
aravindsv 0:ba7650f404af 6417 /******************* Bit definition for TIM_CCER register *******************/
aravindsv 0:ba7650f404af 6418 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
aravindsv 0:ba7650f404af 6419 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
aravindsv 0:ba7650f404af 6420 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
aravindsv 0:ba7650f404af 6421 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
aravindsv 0:ba7650f404af 6422 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
aravindsv 0:ba7650f404af 6423 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
aravindsv 0:ba7650f404af 6424 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
aravindsv 0:ba7650f404af 6425 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
aravindsv 0:ba7650f404af 6426 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
aravindsv 0:ba7650f404af 6427 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
aravindsv 0:ba7650f404af 6428 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
aravindsv 0:ba7650f404af 6429 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
aravindsv 0:ba7650f404af 6430 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
aravindsv 0:ba7650f404af 6431 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
aravindsv 0:ba7650f404af 6432 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
aravindsv 0:ba7650f404af 6433
aravindsv 0:ba7650f404af 6434 /******************* Bit definition for TIM_CNT register ********************/
aravindsv 0:ba7650f404af 6435 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
aravindsv 0:ba7650f404af 6436
aravindsv 0:ba7650f404af 6437 /******************* Bit definition for TIM_PSC register ********************/
aravindsv 0:ba7650f404af 6438 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
aravindsv 0:ba7650f404af 6439
aravindsv 0:ba7650f404af 6440 /******************* Bit definition for TIM_ARR register ********************/
aravindsv 0:ba7650f404af 6441 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
aravindsv 0:ba7650f404af 6442
aravindsv 0:ba7650f404af 6443 /******************* Bit definition for TIM_RCR register ********************/
aravindsv 0:ba7650f404af 6444 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
aravindsv 0:ba7650f404af 6445
aravindsv 0:ba7650f404af 6446 /******************* Bit definition for TIM_CCR1 register *******************/
aravindsv 0:ba7650f404af 6447 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
aravindsv 0:ba7650f404af 6448
aravindsv 0:ba7650f404af 6449 /******************* Bit definition for TIM_CCR2 register *******************/
aravindsv 0:ba7650f404af 6450 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
aravindsv 0:ba7650f404af 6451
aravindsv 0:ba7650f404af 6452 /******************* Bit definition for TIM_CCR3 register *******************/
aravindsv 0:ba7650f404af 6453 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
aravindsv 0:ba7650f404af 6454
aravindsv 0:ba7650f404af 6455 /******************* Bit definition for TIM_CCR4 register *******************/
aravindsv 0:ba7650f404af 6456 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
aravindsv 0:ba7650f404af 6457
aravindsv 0:ba7650f404af 6458 /******************* Bit definition for TIM_BDTR register *******************/
aravindsv 0:ba7650f404af 6459 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
aravindsv 0:ba7650f404af 6460 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6461 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6462 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6463 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6464 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 6465 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 6466 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 6467 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 6468
aravindsv 0:ba7650f404af 6469 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
aravindsv 0:ba7650f404af 6470 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6471 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6472
aravindsv 0:ba7650f404af 6473 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
aravindsv 0:ba7650f404af 6474 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
aravindsv 0:ba7650f404af 6475 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
aravindsv 0:ba7650f404af 6476 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
aravindsv 0:ba7650f404af 6477 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
aravindsv 0:ba7650f404af 6478 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
aravindsv 0:ba7650f404af 6479
aravindsv 0:ba7650f404af 6480 /******************* Bit definition for TIM_DCR register ********************/
aravindsv 0:ba7650f404af 6481 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
aravindsv 0:ba7650f404af 6482 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6483 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6484 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6485 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6486 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 6487
aravindsv 0:ba7650f404af 6488 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
aravindsv 0:ba7650f404af 6489 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6490 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6491 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6492 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6493 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
aravindsv 0:ba7650f404af 6494
aravindsv 0:ba7650f404af 6495 /******************* Bit definition for TIM_DMAR register *******************/
aravindsv 0:ba7650f404af 6496 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
aravindsv 0:ba7650f404af 6497
aravindsv 0:ba7650f404af 6498 /******************* Bit definition for TIM_OR register *********************/
aravindsv 0:ba7650f404af 6499 #define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
aravindsv 0:ba7650f404af 6500 #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6501 #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6502 #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
aravindsv 0:ba7650f404af 6503 #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6504 #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6505
aravindsv 0:ba7650f404af 6506
aravindsv 0:ba7650f404af 6507 /******************************************************************************/
aravindsv 0:ba7650f404af 6508 /* */
aravindsv 0:ba7650f404af 6509 /* Universal Synchronous Asynchronous Receiver Transmitter */
aravindsv 0:ba7650f404af 6510 /* */
aravindsv 0:ba7650f404af 6511 /******************************************************************************/
aravindsv 0:ba7650f404af 6512 /******************* Bit definition for USART_SR register *******************/
aravindsv 0:ba7650f404af 6513 #define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */
aravindsv 0:ba7650f404af 6514 #define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */
aravindsv 0:ba7650f404af 6515 #define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */
aravindsv 0:ba7650f404af 6516 #define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */
aravindsv 0:ba7650f404af 6517 #define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */
aravindsv 0:ba7650f404af 6518 #define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */
aravindsv 0:ba7650f404af 6519 #define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */
aravindsv 0:ba7650f404af 6520 #define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */
aravindsv 0:ba7650f404af 6521 #define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */
aravindsv 0:ba7650f404af 6522 #define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */
aravindsv 0:ba7650f404af 6523
aravindsv 0:ba7650f404af 6524 /******************* Bit definition for USART_DR register *******************/
aravindsv 0:ba7650f404af 6525 #define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */
aravindsv 0:ba7650f404af 6526
aravindsv 0:ba7650f404af 6527 /****************** Bit definition for USART_BRR register *******************/
aravindsv 0:ba7650f404af 6528 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */
aravindsv 0:ba7650f404af 6529 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */
aravindsv 0:ba7650f404af 6530
aravindsv 0:ba7650f404af 6531 /****************** Bit definition for USART_CR1 register *******************/
aravindsv 0:ba7650f404af 6532 #define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */
aravindsv 0:ba7650f404af 6533 #define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */
aravindsv 0:ba7650f404af 6534 #define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */
aravindsv 0:ba7650f404af 6535 #define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */
aravindsv 0:ba7650f404af 6536 #define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */
aravindsv 0:ba7650f404af 6537 #define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */
aravindsv 0:ba7650f404af 6538 #define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */
aravindsv 0:ba7650f404af 6539 #define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */
aravindsv 0:ba7650f404af 6540 #define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */
aravindsv 0:ba7650f404af 6541 #define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */
aravindsv 0:ba7650f404af 6542 #define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */
aravindsv 0:ba7650f404af 6543 #define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
aravindsv 0:ba7650f404af 6544 #define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
aravindsv 0:ba7650f404af 6545 #define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
aravindsv 0:ba7650f404af 6546 #define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */
aravindsv 0:ba7650f404af 6547
aravindsv 0:ba7650f404af 6548 /****************** Bit definition for USART_CR2 register *******************/
aravindsv 0:ba7650f404af 6549 #define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
aravindsv 0:ba7650f404af 6550 #define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */
aravindsv 0:ba7650f404af 6551 #define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
aravindsv 0:ba7650f404af 6552 #define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */
aravindsv 0:ba7650f404af 6553 #define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */
aravindsv 0:ba7650f404af 6554 #define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */
aravindsv 0:ba7650f404af 6555 #define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */
aravindsv 0:ba7650f404af 6556
aravindsv 0:ba7650f404af 6557 #define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
aravindsv 0:ba7650f404af 6558 #define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6559 #define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6560
aravindsv 0:ba7650f404af 6561 #define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */
aravindsv 0:ba7650f404af 6562
aravindsv 0:ba7650f404af 6563 /****************** Bit definition for USART_CR3 register *******************/
aravindsv 0:ba7650f404af 6564 #define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */
aravindsv 0:ba7650f404af 6565 #define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */
aravindsv 0:ba7650f404af 6566 #define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */
aravindsv 0:ba7650f404af 6567 #define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */
aravindsv 0:ba7650f404af 6568 #define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */
aravindsv 0:ba7650f404af 6569 #define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */
aravindsv 0:ba7650f404af 6570 #define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */
aravindsv 0:ba7650f404af 6571 #define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */
aravindsv 0:ba7650f404af 6572 #define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
aravindsv 0:ba7650f404af 6573 #define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
aravindsv 0:ba7650f404af 6574 #define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
aravindsv 0:ba7650f404af 6575 #define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */
aravindsv 0:ba7650f404af 6576
aravindsv 0:ba7650f404af 6577 /****************** Bit definition for USART_GTPR register ******************/
aravindsv 0:ba7650f404af 6578 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
aravindsv 0:ba7650f404af 6579 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6580 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6581 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6582 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6583 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 6584 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 6585 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 6586 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */
aravindsv 0:ba7650f404af 6587
aravindsv 0:ba7650f404af 6588 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */
aravindsv 0:ba7650f404af 6589
aravindsv 0:ba7650f404af 6590 /******************************************************************************/
aravindsv 0:ba7650f404af 6591 /* */
aravindsv 0:ba7650f404af 6592 /* Window WATCHDOG */
aravindsv 0:ba7650f404af 6593 /* */
aravindsv 0:ba7650f404af 6594 /******************************************************************************/
aravindsv 0:ba7650f404af 6595 /******************* Bit definition for WWDG_CR register ********************/
aravindsv 0:ba7650f404af 6596 #define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
aravindsv 0:ba7650f404af 6597 #define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6598 #define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6599 #define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6600 #define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6601 #define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
aravindsv 0:ba7650f404af 6602 #define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
aravindsv 0:ba7650f404af 6603 #define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
aravindsv 0:ba7650f404af 6604
aravindsv 0:ba7650f404af 6605 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
aravindsv 0:ba7650f404af 6606
aravindsv 0:ba7650f404af 6607 /******************* Bit definition for WWDG_CFR register *******************/
aravindsv 0:ba7650f404af 6608 #define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
aravindsv 0:ba7650f404af 6609 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6610 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6611 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
aravindsv 0:ba7650f404af 6612 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
aravindsv 0:ba7650f404af 6613 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
aravindsv 0:ba7650f404af 6614 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
aravindsv 0:ba7650f404af 6615 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
aravindsv 0:ba7650f404af 6616
aravindsv 0:ba7650f404af 6617 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
aravindsv 0:ba7650f404af 6618 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
aravindsv 0:ba7650f404af 6619 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
aravindsv 0:ba7650f404af 6620
aravindsv 0:ba7650f404af 6621 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
aravindsv 0:ba7650f404af 6622
aravindsv 0:ba7650f404af 6623 /******************* Bit definition for WWDG_SR register ********************/
aravindsv 0:ba7650f404af 6624 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
aravindsv 0:ba7650f404af 6625
aravindsv 0:ba7650f404af 6626
aravindsv 0:ba7650f404af 6627 /******************************************************************************/
aravindsv 0:ba7650f404af 6628 /* */
aravindsv 0:ba7650f404af 6629 /* DBG */
aravindsv 0:ba7650f404af 6630 /* */
aravindsv 0:ba7650f404af 6631 /******************************************************************************/
aravindsv 0:ba7650f404af 6632 /******************** Bit definition for DBGMCU_IDCODE register *************/
aravindsv 0:ba7650f404af 6633 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
aravindsv 0:ba7650f404af 6634 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
aravindsv 0:ba7650f404af 6635
aravindsv 0:ba7650f404af 6636 /******************** Bit definition for DBGMCU_CR register *****************/
aravindsv 0:ba7650f404af 6637 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 6638 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 6639 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 6640 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 6641
aravindsv 0:ba7650f404af 6642 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
aravindsv 0:ba7650f404af 6643 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
aravindsv 0:ba7650f404af 6644 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
aravindsv 0:ba7650f404af 6645
aravindsv 0:ba7650f404af 6646 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
aravindsv 0:ba7650f404af 6647 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 6648 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 6649 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
aravindsv 0:ba7650f404af 6650 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
aravindsv 0:ba7650f404af 6651 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
aravindsv 0:ba7650f404af 6652 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
aravindsv 0:ba7650f404af 6653 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
aravindsv 0:ba7650f404af 6654 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
aravindsv 0:ba7650f404af 6655 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
aravindsv 0:ba7650f404af 6656 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
aravindsv 0:ba7650f404af 6657 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
aravindsv 0:ba7650f404af 6658 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
aravindsv 0:ba7650f404af 6659 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
aravindsv 0:ba7650f404af 6660 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
aravindsv 0:ba7650f404af 6661 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
aravindsv 0:ba7650f404af 6662 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
aravindsv 0:ba7650f404af 6663 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
aravindsv 0:ba7650f404af 6664 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
aravindsv 0:ba7650f404af 6665 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
aravindsv 0:ba7650f404af 6666
aravindsv 0:ba7650f404af 6667 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
aravindsv 0:ba7650f404af 6668 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
aravindsv 0:ba7650f404af 6669 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
aravindsv 0:ba7650f404af 6670 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
aravindsv 0:ba7650f404af 6671 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
aravindsv 0:ba7650f404af 6672 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
aravindsv 0:ba7650f404af 6673
aravindsv 0:ba7650f404af 6674 /******************************************************************************/
aravindsv 0:ba7650f404af 6675 /* */
aravindsv 0:ba7650f404af 6676 /* Ethernet MAC Registers bits definitions */
aravindsv 0:ba7650f404af 6677 /* */
aravindsv 0:ba7650f404af 6678 /******************************************************************************/
aravindsv 0:ba7650f404af 6679 /* Bit definition for Ethernet MAC Control Register register */
aravindsv 0:ba7650f404af 6680 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
aravindsv 0:ba7650f404af 6681 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
aravindsv 0:ba7650f404af 6682 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
aravindsv 0:ba7650f404af 6683 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
aravindsv 0:ba7650f404af 6684 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
aravindsv 0:ba7650f404af 6685 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
aravindsv 0:ba7650f404af 6686 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
aravindsv 0:ba7650f404af 6687 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
aravindsv 0:ba7650f404af 6688 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
aravindsv 0:ba7650f404af 6689 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
aravindsv 0:ba7650f404af 6690 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
aravindsv 0:ba7650f404af 6691 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
aravindsv 0:ba7650f404af 6692 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
aravindsv 0:ba7650f404af 6693 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
aravindsv 0:ba7650f404af 6694 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
aravindsv 0:ba7650f404af 6695 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
aravindsv 0:ba7650f404af 6696 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
aravindsv 0:ba7650f404af 6697 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
aravindsv 0:ba7650f404af 6698 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
aravindsv 0:ba7650f404af 6699 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
aravindsv 0:ba7650f404af 6700 a transmission attempt during retries after a collision: 0 =< r <2^k */
aravindsv 0:ba7650f404af 6701 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
aravindsv 0:ba7650f404af 6702 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
aravindsv 0:ba7650f404af 6703 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
aravindsv 0:ba7650f404af 6704 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
aravindsv 0:ba7650f404af 6705 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
aravindsv 0:ba7650f404af 6706 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
aravindsv 0:ba7650f404af 6707 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
aravindsv 0:ba7650f404af 6708
aravindsv 0:ba7650f404af 6709 /* Bit definition for Ethernet MAC Frame Filter Register */
aravindsv 0:ba7650f404af 6710 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
aravindsv 0:ba7650f404af 6711 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
aravindsv 0:ba7650f404af 6712 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
aravindsv 0:ba7650f404af 6713 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
aravindsv 0:ba7650f404af 6714 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
aravindsv 0:ba7650f404af 6715 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
aravindsv 0:ba7650f404af 6716 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
aravindsv 0:ba7650f404af 6717 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
aravindsv 0:ba7650f404af 6718 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
aravindsv 0:ba7650f404af 6719 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
aravindsv 0:ba7650f404af 6720 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
aravindsv 0:ba7650f404af 6721 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
aravindsv 0:ba7650f404af 6722 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
aravindsv 0:ba7650f404af 6723 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
aravindsv 0:ba7650f404af 6724
aravindsv 0:ba7650f404af 6725 /* Bit definition for Ethernet MAC Hash Table High Register */
aravindsv 0:ba7650f404af 6726 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
aravindsv 0:ba7650f404af 6727
aravindsv 0:ba7650f404af 6728 /* Bit definition for Ethernet MAC Hash Table Low Register */
aravindsv 0:ba7650f404af 6729 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
aravindsv 0:ba7650f404af 6730
aravindsv 0:ba7650f404af 6731 /* Bit definition for Ethernet MAC MII Address Register */
aravindsv 0:ba7650f404af 6732 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
aravindsv 0:ba7650f404af 6733 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
aravindsv 0:ba7650f404af 6734 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
aravindsv 0:ba7650f404af 6735 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
aravindsv 0:ba7650f404af 6736 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
aravindsv 0:ba7650f404af 6737 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
aravindsv 0:ba7650f404af 6738 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
aravindsv 0:ba7650f404af 6739 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
aravindsv 0:ba7650f404af 6740 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
aravindsv 0:ba7650f404af 6741 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
aravindsv 0:ba7650f404af 6742
aravindsv 0:ba7650f404af 6743 /* Bit definition for Ethernet MAC MII Data Register */
aravindsv 0:ba7650f404af 6744 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
aravindsv 0:ba7650f404af 6745
aravindsv 0:ba7650f404af 6746 /* Bit definition for Ethernet MAC Flow Control Register */
aravindsv 0:ba7650f404af 6747 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
aravindsv 0:ba7650f404af 6748 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
aravindsv 0:ba7650f404af 6749 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
aravindsv 0:ba7650f404af 6750 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
aravindsv 0:ba7650f404af 6751 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
aravindsv 0:ba7650f404af 6752 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
aravindsv 0:ba7650f404af 6753 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
aravindsv 0:ba7650f404af 6754 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
aravindsv 0:ba7650f404af 6755 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
aravindsv 0:ba7650f404af 6756 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
aravindsv 0:ba7650f404af 6757 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
aravindsv 0:ba7650f404af 6758
aravindsv 0:ba7650f404af 6759 /* Bit definition for Ethernet MAC VLAN Tag Register */
aravindsv 0:ba7650f404af 6760 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
aravindsv 0:ba7650f404af 6761 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
aravindsv 0:ba7650f404af 6762
aravindsv 0:ba7650f404af 6763 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
aravindsv 0:ba7650f404af 6764 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
aravindsv 0:ba7650f404af 6765 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
aravindsv 0:ba7650f404af 6766 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
aravindsv 0:ba7650f404af 6767 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
aravindsv 0:ba7650f404af 6768 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
aravindsv 0:ba7650f404af 6769 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
aravindsv 0:ba7650f404af 6770 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
aravindsv 0:ba7650f404af 6771 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
aravindsv 0:ba7650f404af 6772 RSVD - Filter1 Command - RSVD - Filter0 Command
aravindsv 0:ba7650f404af 6773 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
aravindsv 0:ba7650f404af 6774 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
aravindsv 0:ba7650f404af 6775 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
aravindsv 0:ba7650f404af 6776
aravindsv 0:ba7650f404af 6777 /* Bit definition for Ethernet MAC PMT Control and Status Register */
aravindsv 0:ba7650f404af 6778 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
aravindsv 0:ba7650f404af 6779 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
aravindsv 0:ba7650f404af 6780 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
aravindsv 0:ba7650f404af 6781 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
aravindsv 0:ba7650f404af 6782 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
aravindsv 0:ba7650f404af 6783 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
aravindsv 0:ba7650f404af 6784 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
aravindsv 0:ba7650f404af 6785
aravindsv 0:ba7650f404af 6786 /* Bit definition for Ethernet MAC Status Register */
aravindsv 0:ba7650f404af 6787 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
aravindsv 0:ba7650f404af 6788 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
aravindsv 0:ba7650f404af 6789 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
aravindsv 0:ba7650f404af 6790 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
aravindsv 0:ba7650f404af 6791 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
aravindsv 0:ba7650f404af 6792
aravindsv 0:ba7650f404af 6793 /* Bit definition for Ethernet MAC Interrupt Mask Register */
aravindsv 0:ba7650f404af 6794 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
aravindsv 0:ba7650f404af 6795 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
aravindsv 0:ba7650f404af 6796
aravindsv 0:ba7650f404af 6797 /* Bit definition for Ethernet MAC Address0 High Register */
aravindsv 0:ba7650f404af 6798 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
aravindsv 0:ba7650f404af 6799
aravindsv 0:ba7650f404af 6800 /* Bit definition for Ethernet MAC Address0 Low Register */
aravindsv 0:ba7650f404af 6801 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
aravindsv 0:ba7650f404af 6802
aravindsv 0:ba7650f404af 6803 /* Bit definition for Ethernet MAC Address1 High Register */
aravindsv 0:ba7650f404af 6804 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
aravindsv 0:ba7650f404af 6805 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
aravindsv 0:ba7650f404af 6806 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
aravindsv 0:ba7650f404af 6807 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
aravindsv 0:ba7650f404af 6808 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
aravindsv 0:ba7650f404af 6809 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
aravindsv 0:ba7650f404af 6810 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
aravindsv 0:ba7650f404af 6811 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
aravindsv 0:ba7650f404af 6812 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
aravindsv 0:ba7650f404af 6813 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
aravindsv 0:ba7650f404af 6814
aravindsv 0:ba7650f404af 6815 /* Bit definition for Ethernet MAC Address1 Low Register */
aravindsv 0:ba7650f404af 6816 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
aravindsv 0:ba7650f404af 6817
aravindsv 0:ba7650f404af 6818 /* Bit definition for Ethernet MAC Address2 High Register */
aravindsv 0:ba7650f404af 6819 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
aravindsv 0:ba7650f404af 6820 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
aravindsv 0:ba7650f404af 6821 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
aravindsv 0:ba7650f404af 6822 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
aravindsv 0:ba7650f404af 6823 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
aravindsv 0:ba7650f404af 6824 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
aravindsv 0:ba7650f404af 6825 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
aravindsv 0:ba7650f404af 6826 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
aravindsv 0:ba7650f404af 6827 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
aravindsv 0:ba7650f404af 6828 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
aravindsv 0:ba7650f404af 6829
aravindsv 0:ba7650f404af 6830 /* Bit definition for Ethernet MAC Address2 Low Register */
aravindsv 0:ba7650f404af 6831 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
aravindsv 0:ba7650f404af 6832
aravindsv 0:ba7650f404af 6833 /* Bit definition for Ethernet MAC Address3 High Register */
aravindsv 0:ba7650f404af 6834 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
aravindsv 0:ba7650f404af 6835 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
aravindsv 0:ba7650f404af 6836 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
aravindsv 0:ba7650f404af 6837 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
aravindsv 0:ba7650f404af 6838 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
aravindsv 0:ba7650f404af 6839 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
aravindsv 0:ba7650f404af 6840 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
aravindsv 0:ba7650f404af 6841 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
aravindsv 0:ba7650f404af 6842 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
aravindsv 0:ba7650f404af 6843 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
aravindsv 0:ba7650f404af 6844
aravindsv 0:ba7650f404af 6845 /* Bit definition for Ethernet MAC Address3 Low Register */
aravindsv 0:ba7650f404af 6846 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
aravindsv 0:ba7650f404af 6847
aravindsv 0:ba7650f404af 6848 /******************************************************************************/
aravindsv 0:ba7650f404af 6849 /* Ethernet MMC Registers bits definition */
aravindsv 0:ba7650f404af 6850 /******************************************************************************/
aravindsv 0:ba7650f404af 6851
aravindsv 0:ba7650f404af 6852 /* Bit definition for Ethernet MMC Contol Register */
aravindsv 0:ba7650f404af 6853 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
aravindsv 0:ba7650f404af 6854 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
aravindsv 0:ba7650f404af 6855 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
aravindsv 0:ba7650f404af 6856 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
aravindsv 0:ba7650f404af 6857 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
aravindsv 0:ba7650f404af 6858 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
aravindsv 0:ba7650f404af 6859
aravindsv 0:ba7650f404af 6860 /* Bit definition for Ethernet MMC Receive Interrupt Register */
aravindsv 0:ba7650f404af 6861 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6862 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6863 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6864
aravindsv 0:ba7650f404af 6865 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
aravindsv 0:ba7650f404af 6866 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6867 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6868 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6869
aravindsv 0:ba7650f404af 6870 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
aravindsv 0:ba7650f404af 6871 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6872 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6873 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6874
aravindsv 0:ba7650f404af 6875 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
aravindsv 0:ba7650f404af 6876 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6877 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6878 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
aravindsv 0:ba7650f404af 6879
aravindsv 0:ba7650f404af 6880 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
aravindsv 0:ba7650f404af 6881 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
aravindsv 0:ba7650f404af 6882
aravindsv 0:ba7650f404af 6883 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
aravindsv 0:ba7650f404af 6884 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
aravindsv 0:ba7650f404af 6885
aravindsv 0:ba7650f404af 6886 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
aravindsv 0:ba7650f404af 6887 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
aravindsv 0:ba7650f404af 6888
aravindsv 0:ba7650f404af 6889 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
aravindsv 0:ba7650f404af 6890 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
aravindsv 0:ba7650f404af 6891
aravindsv 0:ba7650f404af 6892 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
aravindsv 0:ba7650f404af 6893 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
aravindsv 0:ba7650f404af 6894
aravindsv 0:ba7650f404af 6895 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
aravindsv 0:ba7650f404af 6896 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
aravindsv 0:ba7650f404af 6897
aravindsv 0:ba7650f404af 6898 /******************************************************************************/
aravindsv 0:ba7650f404af 6899 /* Ethernet PTP Registers bits definition */
aravindsv 0:ba7650f404af 6900 /******************************************************************************/
aravindsv 0:ba7650f404af 6901
aravindsv 0:ba7650f404af 6902 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
aravindsv 0:ba7650f404af 6903 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
aravindsv 0:ba7650f404af 6904 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
aravindsv 0:ba7650f404af 6905 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
aravindsv 0:ba7650f404af 6906 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
aravindsv 0:ba7650f404af 6907 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
aravindsv 0:ba7650f404af 6908 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
aravindsv 0:ba7650f404af 6909 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
aravindsv 0:ba7650f404af 6910 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
aravindsv 0:ba7650f404af 6911 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
aravindsv 0:ba7650f404af 6912
aravindsv 0:ba7650f404af 6913 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
aravindsv 0:ba7650f404af 6914 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
aravindsv 0:ba7650f404af 6915 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
aravindsv 0:ba7650f404af 6916 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
aravindsv 0:ba7650f404af 6917 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
aravindsv 0:ba7650f404af 6918 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
aravindsv 0:ba7650f404af 6919
aravindsv 0:ba7650f404af 6920 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
aravindsv 0:ba7650f404af 6921 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
aravindsv 0:ba7650f404af 6922
aravindsv 0:ba7650f404af 6923 /* Bit definition for Ethernet PTP Time Stamp High Register */
aravindsv 0:ba7650f404af 6924 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
aravindsv 0:ba7650f404af 6925
aravindsv 0:ba7650f404af 6926 /* Bit definition for Ethernet PTP Time Stamp Low Register */
aravindsv 0:ba7650f404af 6927 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
aravindsv 0:ba7650f404af 6928 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
aravindsv 0:ba7650f404af 6929
aravindsv 0:ba7650f404af 6930 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
aravindsv 0:ba7650f404af 6931 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
aravindsv 0:ba7650f404af 6932
aravindsv 0:ba7650f404af 6933 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
aravindsv 0:ba7650f404af 6934 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
aravindsv 0:ba7650f404af 6935 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
aravindsv 0:ba7650f404af 6936
aravindsv 0:ba7650f404af 6937 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
aravindsv 0:ba7650f404af 6938 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
aravindsv 0:ba7650f404af 6939
aravindsv 0:ba7650f404af 6940 /* Bit definition for Ethernet PTP Target Time High Register */
aravindsv 0:ba7650f404af 6941 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
aravindsv 0:ba7650f404af 6942
aravindsv 0:ba7650f404af 6943 /* Bit definition for Ethernet PTP Target Time Low Register */
aravindsv 0:ba7650f404af 6944 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
aravindsv 0:ba7650f404af 6945
aravindsv 0:ba7650f404af 6946 /* Bit definition for Ethernet PTP Time Stamp Status Register */
aravindsv 0:ba7650f404af 6947 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
aravindsv 0:ba7650f404af 6948 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
aravindsv 0:ba7650f404af 6949
aravindsv 0:ba7650f404af 6950 /******************************************************************************/
aravindsv 0:ba7650f404af 6951 /* Ethernet DMA Registers bits definition */
aravindsv 0:ba7650f404af 6952 /******************************************************************************/
aravindsv 0:ba7650f404af 6953
aravindsv 0:ba7650f404af 6954 /* Bit definition for Ethernet DMA Bus Mode Register */
aravindsv 0:ba7650f404af 6955 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
aravindsv 0:ba7650f404af 6956 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
aravindsv 0:ba7650f404af 6957 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
aravindsv 0:ba7650f404af 6958 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
aravindsv 0:ba7650f404af 6959 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
aravindsv 0:ba7650f404af 6960 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
aravindsv 0:ba7650f404af 6961 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
aravindsv 0:ba7650f404af 6962 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
aravindsv 0:ba7650f404af 6963 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
aravindsv 0:ba7650f404af 6964 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
aravindsv 0:ba7650f404af 6965 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
aravindsv 0:ba7650f404af 6966 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
aravindsv 0:ba7650f404af 6967 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
aravindsv 0:ba7650f404af 6968 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
aravindsv 0:ba7650f404af 6969 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
aravindsv 0:ba7650f404af 6970 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
aravindsv 0:ba7650f404af 6971 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
aravindsv 0:ba7650f404af 6972 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
aravindsv 0:ba7650f404af 6973 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
aravindsv 0:ba7650f404af 6974 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
aravindsv 0:ba7650f404af 6975 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
aravindsv 0:ba7650f404af 6976 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
aravindsv 0:ba7650f404af 6977 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
aravindsv 0:ba7650f404af 6978 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
aravindsv 0:ba7650f404af 6979 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
aravindsv 0:ba7650f404af 6980 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
aravindsv 0:ba7650f404af 6981 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
aravindsv 0:ba7650f404af 6982 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
aravindsv 0:ba7650f404af 6983 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
aravindsv 0:ba7650f404af 6984 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
aravindsv 0:ba7650f404af 6985 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
aravindsv 0:ba7650f404af 6986 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
aravindsv 0:ba7650f404af 6987 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
aravindsv 0:ba7650f404af 6988 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
aravindsv 0:ba7650f404af 6989 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
aravindsv 0:ba7650f404af 6990 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
aravindsv 0:ba7650f404af 6991 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
aravindsv 0:ba7650f404af 6992 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
aravindsv 0:ba7650f404af 6993 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
aravindsv 0:ba7650f404af 6994
aravindsv 0:ba7650f404af 6995 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
aravindsv 0:ba7650f404af 6996 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
aravindsv 0:ba7650f404af 6997
aravindsv 0:ba7650f404af 6998 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
aravindsv 0:ba7650f404af 6999 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
aravindsv 0:ba7650f404af 7000
aravindsv 0:ba7650f404af 7001 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
aravindsv 0:ba7650f404af 7002 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
aravindsv 0:ba7650f404af 7003
aravindsv 0:ba7650f404af 7004 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
aravindsv 0:ba7650f404af 7005 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
aravindsv 0:ba7650f404af 7006
aravindsv 0:ba7650f404af 7007 /* Bit definition for Ethernet DMA Status Register */
aravindsv 0:ba7650f404af 7008 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
aravindsv 0:ba7650f404af 7009 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
aravindsv 0:ba7650f404af 7010 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
aravindsv 0:ba7650f404af 7011 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
aravindsv 0:ba7650f404af 7012 /* combination with EBS[2:0] for GetFlagStatus function */
aravindsv 0:ba7650f404af 7013 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
aravindsv 0:ba7650f404af 7014 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
aravindsv 0:ba7650f404af 7015 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
aravindsv 0:ba7650f404af 7016 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
aravindsv 0:ba7650f404af 7017 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
aravindsv 0:ba7650f404af 7018 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
aravindsv 0:ba7650f404af 7019 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
aravindsv 0:ba7650f404af 7020 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
aravindsv 0:ba7650f404af 7021 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
aravindsv 0:ba7650f404af 7022 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
aravindsv 0:ba7650f404af 7023 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
aravindsv 0:ba7650f404af 7024 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
aravindsv 0:ba7650f404af 7025 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
aravindsv 0:ba7650f404af 7026 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
aravindsv 0:ba7650f404af 7027 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
aravindsv 0:ba7650f404af 7028 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
aravindsv 0:ba7650f404af 7029 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
aravindsv 0:ba7650f404af 7030 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
aravindsv 0:ba7650f404af 7031 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
aravindsv 0:ba7650f404af 7032 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
aravindsv 0:ba7650f404af 7033 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
aravindsv 0:ba7650f404af 7034 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
aravindsv 0:ba7650f404af 7035 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
aravindsv 0:ba7650f404af 7036 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
aravindsv 0:ba7650f404af 7037 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
aravindsv 0:ba7650f404af 7038 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
aravindsv 0:ba7650f404af 7039 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
aravindsv 0:ba7650f404af 7040 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
aravindsv 0:ba7650f404af 7041 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
aravindsv 0:ba7650f404af 7042 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
aravindsv 0:ba7650f404af 7043 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
aravindsv 0:ba7650f404af 7044 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
aravindsv 0:ba7650f404af 7045
aravindsv 0:ba7650f404af 7046 /* Bit definition for Ethernet DMA Operation Mode Register */
aravindsv 0:ba7650f404af 7047 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
aravindsv 0:ba7650f404af 7048 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
aravindsv 0:ba7650f404af 7049 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
aravindsv 0:ba7650f404af 7050 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
aravindsv 0:ba7650f404af 7051 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
aravindsv 0:ba7650f404af 7052 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
aravindsv 0:ba7650f404af 7053 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
aravindsv 0:ba7650f404af 7054 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
aravindsv 0:ba7650f404af 7055 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
aravindsv 0:ba7650f404af 7056 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
aravindsv 0:ba7650f404af 7057 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
aravindsv 0:ba7650f404af 7058 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
aravindsv 0:ba7650f404af 7059 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
aravindsv 0:ba7650f404af 7060 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
aravindsv 0:ba7650f404af 7061 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
aravindsv 0:ba7650f404af 7062 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
aravindsv 0:ba7650f404af 7063 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
aravindsv 0:ba7650f404af 7064 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
aravindsv 0:ba7650f404af 7065 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
aravindsv 0:ba7650f404af 7066 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
aravindsv 0:ba7650f404af 7067 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
aravindsv 0:ba7650f404af 7068 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
aravindsv 0:ba7650f404af 7069 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
aravindsv 0:ba7650f404af 7070 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
aravindsv 0:ba7650f404af 7071
aravindsv 0:ba7650f404af 7072 /* Bit definition for Ethernet DMA Interrupt Enable Register */
aravindsv 0:ba7650f404af 7073 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
aravindsv 0:ba7650f404af 7074 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
aravindsv 0:ba7650f404af 7075 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
aravindsv 0:ba7650f404af 7076 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
aravindsv 0:ba7650f404af 7077 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
aravindsv 0:ba7650f404af 7078 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
aravindsv 0:ba7650f404af 7079 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
aravindsv 0:ba7650f404af 7080 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
aravindsv 0:ba7650f404af 7081 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
aravindsv 0:ba7650f404af 7082 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
aravindsv 0:ba7650f404af 7083 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
aravindsv 0:ba7650f404af 7084 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
aravindsv 0:ba7650f404af 7085 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
aravindsv 0:ba7650f404af 7086 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
aravindsv 0:ba7650f404af 7087 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
aravindsv 0:ba7650f404af 7088
aravindsv 0:ba7650f404af 7089 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
aravindsv 0:ba7650f404af 7090 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
aravindsv 0:ba7650f404af 7091 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
aravindsv 0:ba7650f404af 7092 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
aravindsv 0:ba7650f404af 7093 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
aravindsv 0:ba7650f404af 7094
aravindsv 0:ba7650f404af 7095 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
aravindsv 0:ba7650f404af 7096 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
aravindsv 0:ba7650f404af 7097
aravindsv 0:ba7650f404af 7098 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
aravindsv 0:ba7650f404af 7099 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
aravindsv 0:ba7650f404af 7100
aravindsv 0:ba7650f404af 7101 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
aravindsv 0:ba7650f404af 7102 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
aravindsv 0:ba7650f404af 7103
aravindsv 0:ba7650f404af 7104 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
aravindsv 0:ba7650f404af 7105 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
aravindsv 0:ba7650f404af 7106
aravindsv 0:ba7650f404af 7107 /**
aravindsv 0:ba7650f404af 7108 *
aravindsv 0:ba7650f404af 7109 */
aravindsv 0:ba7650f404af 7110
aravindsv 0:ba7650f404af 7111 /**
aravindsv 0:ba7650f404af 7112 * @}
aravindsv 0:ba7650f404af 7113 */
aravindsv 0:ba7650f404af 7114
aravindsv 0:ba7650f404af 7115 #ifdef USE_STDPERIPH_DRIVER
aravindsv 0:ba7650f404af 7116 #include "stm32f4xx_conf.h"
aravindsv 0:ba7650f404af 7117 #endif /* USE_STDPERIPH_DRIVER */
aravindsv 0:ba7650f404af 7118
aravindsv 0:ba7650f404af 7119 /** @addtogroup Exported_macro
aravindsv 0:ba7650f404af 7120 * @{
aravindsv 0:ba7650f404af 7121 */
aravindsv 0:ba7650f404af 7122
aravindsv 0:ba7650f404af 7123 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
aravindsv 0:ba7650f404af 7124
aravindsv 0:ba7650f404af 7125 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
aravindsv 0:ba7650f404af 7126
aravindsv 0:ba7650f404af 7127 #define READ_BIT(REG, BIT) ((REG) & (BIT))
aravindsv 0:ba7650f404af 7128
aravindsv 0:ba7650f404af 7129 #define CLEAR_REG(REG) ((REG) = (0x0))
aravindsv 0:ba7650f404af 7130
aravindsv 0:ba7650f404af 7131 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
aravindsv 0:ba7650f404af 7132
aravindsv 0:ba7650f404af 7133 #define READ_REG(REG) ((REG))
aravindsv 0:ba7650f404af 7134
aravindsv 0:ba7650f404af 7135 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
aravindsv 0:ba7650f404af 7136
aravindsv 0:ba7650f404af 7137 /**
aravindsv 0:ba7650f404af 7138 * @}
aravindsv 0:ba7650f404af 7139 */
aravindsv 0:ba7650f404af 7140
aravindsv 0:ba7650f404af 7141 #ifdef __cplusplus
aravindsv 0:ba7650f404af 7142 }
aravindsv 0:ba7650f404af 7143 #endif /* __cplusplus */
aravindsv 0:ba7650f404af 7144
aravindsv 0:ba7650f404af 7145 #endif /* __STM32F4xx_H */
aravindsv 0:ba7650f404af 7146
aravindsv 0:ba7650f404af 7147 /**
aravindsv 0:ba7650f404af 7148 * @}
aravindsv 0:ba7650f404af 7149 */
aravindsv 0:ba7650f404af 7150
aravindsv 0:ba7650f404af 7151 /**
aravindsv 0:ba7650f404af 7152 * @}
aravindsv 0:ba7650f404af 7153 */
aravindsv 0:ba7650f404af 7154
aravindsv 0:ba7650f404af 7155 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/