Aravind Vadali / mbed-src-AV

mbed.h library with any bug fixes AV finds.

Dependents:   micromouse4_encoder_testing PID_Test Lab1_Test WorkingPID ... more

targets/hal/TARGET_NXP/TARGET_LPC43XX/README.txt@1:ebce2ad32f95, 2015-11-02 (annotated)

Committer:
aravindsv
Date:
Mon Nov 02 03:07:12 2015 +0000
Revision:
1:ebce2ad32f95
Parent:
0:ba7650f404af 
Changed the RCC timeout value to 500 ms, so total code startup time before program starts running is ~1s. Hopefully no side-effects from lower startup timeouts

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aravindsv 0:ba7650f404af 1 mbed port to NXP LPC43xx
aravindsv 0:ba7650f404af 2 ========================
aravindsv 0:ba7650f404af 3 Updated: 07/11/14
aravindsv 0:ba7650f404af 4
aravindsv 0:ba7650f404af 5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
aravindsv 0:ba7650f404af 6 microcontroller package. This port allows mbed developers to take advantage
aravindsv 0:ba7650f404af 7 of the LPC43xx in their application using APIs that they are familiar with.
aravindsv 0:ba7650f404af 8 Some of the key features of the LPC43xx include:
aravindsv 0:ba7650f404af 9
aravindsv 0:ba7650f404af 10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
aravindsv 0:ba7650f404af 11 * Up to 264 KB SRAM, 1 MB internal flash
aravindsv 0:ba7650f404af 12 * Two High-speed USB 2.0 interfaces
aravindsv 0:ba7650f404af 13 * Ethernet MAC
aravindsv 0:ba7650f404af 14 * LCD interface
aravindsv 0:ba7650f404af 15 * Quad-SPI Flash Interface (SPIFI)
aravindsv 0:ba7650f404af 16 * State Configurable Timer (SCT)
aravindsv 0:ba7650f404af 17 * Serial GPIO (SGPIO)
aravindsv 0:ba7650f404af 18 * Up to 164 GPIO
aravindsv 0:ba7650f404af 19
aravindsv 0:ba7650f404af 20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
aravindsv 0:ba7650f404af 21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
aravindsv 0:ba7650f404af 22
aravindsv 0:ba7650f404af 23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
aravindsv 0:ba7650f404af 24
aravindsv 0:ba7650f404af 25 Compatibility
aravindsv 0:ba7650f404af 26 -------------
aravindsv 0:ba7650f404af 27 * This port has been tested with the following boards:
aravindsv 0:ba7650f404af 28 Board MCU RAM/Flash
aravindsv 0:ba7650f404af 29 Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
aravindsv 0:ba7650f404af 30 Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
aravindsv 0:ba7650f404af 31 Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
aravindsv 0:ba7650f404af 32 Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
aravindsv 0:ba7650f404af 33
aravindsv 0:ba7650f404af 34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
aravindsv 0:ba7650f404af 35 To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
aravindsv 0:ba7650f404af 36 for flash programming.
aravindsv 0:ba7650f404af 37
aravindsv 0:ba7650f404af 38 * This port should support NXP LPC43XX and LPC18XX variants with a single
aravindsv 0:ba7650f404af 39 codebase. The core declaration specifies the binaries to be built:
aravindsv 0:ba7650f404af 40 mbed define CMSIS define MCU Target
aravindsv 0:ba7650f404af 41 __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
aravindsv 0:ba7650f404af 42 __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
aravindsv 0:ba7650f404af 43 __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
aravindsv 0:ba7650f404af 44 These MCUs all share the peripheral IP, common driver code is feasible.
aravindsv 0:ba7650f404af 45 Yet each variant can have different memory segments, peripherals, etc.
aravindsv 0:ba7650f404af 46 Plus, each board design can integrate different external peripherals
aravindsv 0:ba7650f404af 47 or interfaces. A future release of the mbed SDK and its build tools will
aravindsv 0:ba7650f404af 48 support specifying the target board when building binaries. At this time
aravindsv 0:ba7650f404af 49 building binaries for different targets requires an external project or
aravindsv 0:ba7650f404af 50 Makefile.
aravindsv 0:ba7650f404af 51
aravindsv 0:ba7650f404af 52 * No testing has been done with LPC18xx hardware.
aravindsv 0:ba7650f404af 53
aravindsv 0:ba7650f404af 54 Notes
aravindsv 0:ba7650f404af 55 -----
aravindsv 0:ba7650f404af 56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
aravindsv 0:ba7650f404af 57 requiring different offsets for the SCU and GPIO registers. To simplify logic
aravindsv 0:ba7650f404af 58 the pin identifier encodes the offsets. Macros are used for decoding.
aravindsv 0:ba7650f404af 59 For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
aravindsv 0:ba7650f404af 60
aravindsv 0:ba7650f404af 61 P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
aravindsv 0:ba7650f404af 62
aravindsv 0:ba7650f404af 63 MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
aravindsv 0:ba7650f404af 64 MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
aravindsv 0:ba7650f404af 65
aravindsv 0:ba7650f404af 66 * Pin names use multiple aliases to support Arduino naming conventions as well
aravindsv 0:ba7650f404af 67 as others. For example, to use pin p21 on the Bambino 210 from mbed applications
aravindsv 0:ba7650f404af 68 the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
aravindsv 0:ba7650f404af 69 See the board pinout graphic and the PinNames.h for available aliases.
aravindsv 0:ba7650f404af 70
aravindsv 0:ba7650f404af 71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
aravindsv 0:ba7650f404af 72 GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
aravindsv 0:ba7650f404af 73 pin can only interrupt on the rising or falling edge, not both as required
aravindsv 0:ba7650f404af 74 by the mbed InterruptIn class. Also, group interrupts can't be cleared
aravindsv 0:ba7650f404af 75 individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
aravindsv 0:ba7650f404af 76 A future implementation may provide group interrupt support.
aravindsv 0:ba7650f404af 77
aravindsv 0:ba7650f404af 78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
aravindsv 0:ba7650f404af 79 build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
aravindsv 0:ba7650f404af 80 and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
aravindsv 0:ba7650f404af 81 when building the library.