Clone of official tools
export/lpcxpresso/lpc1768_cproject.tmpl@47:21ae3e5a7128, 2021-02-04 (annotated)
- Committer:
- Anders Blomdell
- Date:
- Thu Feb 04 17:17:13 2021 +0100
- Revision:
- 47:21ae3e5a7128
- Parent:
- 36:96847d42f010
Add a few normpath calls
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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36:96847d42f010 | 1 | {% extends "lpcxpresso/cproject_cortexm3_common.tmpl" %} |
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36:96847d42f010 | 2 | |
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36:96847d42f010 | 3 | {% block startup_file %}cr_startup_lpc176x.c{% endblock %} |
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36:96847d42f010 | 4 | |
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36:96847d42f010 | 5 | {% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> |
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36:96847d42f010 | 6 | <TargetConfig> |
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36:96847d42f010 | 7 | <Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/> |
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36:96847d42f010 | 8 | <infoList vendor="NXP"> |
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36:96847d42f010 | 9 | <info chip="LPC1768" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC1768" package="lpc17_lqfp100.xml"> |
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36:96847d42f010 | 10 | <chip> |
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36:96847d42f010 | 11 | <name>LPC1768</name> |
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36:96847d42f010 | 12 | <family>LPC17xx</family> |
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36:96847d42f010 | 13 | <vendor>NXP (formerly Philips)</vendor> |
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36:96847d42f010 | 14 | <reset board="None" core="Real" sys="Real"/> |
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36:96847d42f010 | 15 | <clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/> |
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36:96847d42f010 | 16 | <memory can_program="true" id="Flash" is_ro="true" type="Flash"/> |
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36:96847d42f010 | 17 | <memory id="RAM" type="RAM"/> |
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36:96847d42f010 | 18 | <memory id="Periph" is_volatile="true" type="Peripheral"/> |
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36:96847d42f010 | 19 | <memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/> |
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36:96847d42f010 | 20 | <memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/> |
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36:96847d42f010 | 21 | <memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/> |
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36:96847d42f010 | 22 | <prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/> |
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36:96847d42f010 | 23 | <prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/> |
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36:96847d42f010 | 24 | <peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/> |
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36:96847d42f010 | 25 | <peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&amp;0x1" id="TIMER0" location="0x40004000"/> |
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36:96847d42f010 | 26 | <peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&amp;0x1" id="TIMER1" location="0x40008000"/> |
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36:96847d42f010 | 27 | <peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&amp;0x1" id="TIMER2" location="0x40090000"/> |
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36:96847d42f010 | 28 | <peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&amp;0x1" id="TIMER3" location="0x40094000"/> |
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36:96847d42f010 | 29 | <peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&amp;0x1" id="RIT" location="0x400B0000"/> |
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36:96847d42f010 | 30 | <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO0" location="0x2009C000"/> |
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36:96847d42f010 | 31 | <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO1" location="0x2009C020"/> |
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36:96847d42f010 | 32 | <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO2" location="0x2009C040"/> |
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36:96847d42f010 | 33 | <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO3" location="0x2009C060"/> |
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36:96847d42f010 | 34 | <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&amp;0x1" id="GPIO4" location="0x2009C080"/> |
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36:96847d42f010 | 35 | <peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&amp;0x08000000" id="I2S" location="0x400A8000"/> |
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36:96847d42f010 | 36 | <peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/> |
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36:96847d42f010 | 37 | <peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&amp;0x2=2" id="DAC" location="0x4008C000"/> |
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36:96847d42f010 | 38 | <peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&amp;0x1" id="UART0" location="0x4000C000"/> |
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36:96847d42f010 | 39 | <peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&amp;0x1" id="UART1" location="0x40010000"/> |
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36:96847d42f010 | 40 | <peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&amp;0x1" id="UART2" location="0x40098000"/> |
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36:96847d42f010 | 41 | <peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&amp;0x1" id="UART3" location="0x4009C000"/> |
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36:96847d42f010 | 42 | <peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&amp;0x1" id="SPI" location="0x40020000"/> |
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36:96847d42f010 | 43 | <peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&amp;0x1" id="SSP0" location="0x40088000"/> |
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36:96847d42f010 | 44 | <peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&amp;0x1" id="SSP1" location="0x40030000"/> |
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36:96847d42f010 | 45 | <peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&amp;0x1" id="ADC" location="0x40034000"/> |
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36:96847d42f010 | 46 | <peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&amp;0x12" id="USBINTSTAT" location="0x400fc1c0"/> |
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36:96847d42f010 | 47 | <peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/> |
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36:96847d42f010 | 48 | <peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x12=0x12" id="USBDEV" location="0x5000C200"/> |
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36:96847d42f010 | 49 | <peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&amp;0x1" id="PWM" location="0x40018000"/> |
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36:96847d42f010 | 50 | <peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&amp;0x1" id="I2C0" location="0x4001C000"/> |
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36:96847d42f010 | 51 | <peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&amp;0x1" id="I2C1" location="0x4005C000"/> |
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36:96847d42f010 | 52 | <peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&amp;0x1" id="I2C2" location="0x400A0000"/> |
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36:96847d42f010 | 53 | <peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&amp;0x1" id="DMA" location="0x50004000"/> |
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36:96847d42f010 | 54 | <peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&amp;0x1" id="ENET" location="0x50000000"/> |
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36:96847d42f010 | 55 | <peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/> |
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36:96847d42f010 | 56 | <peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/> |
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36:96847d42f010 | 57 | <peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&amp;0x1" id="QEI" location="0x400bc000"/> |
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36:96847d42f010 | 58 | <peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x11=0x11" id="USBHOST" location="0x5000C000"/> |
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36:96847d42f010 | 59 | <peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&amp;0x1c=0x1c" id="USBOTG" location="0x5000C000"/> |
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36:96847d42f010 | 60 | <peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&amp;0x1" id="RTC" location="0x40024000"/> |
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36:96847d42f010 | 61 | <peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/> |
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36:96847d42f010 | 62 | <peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/> |
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36:96847d42f010 | 63 | <peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/> |
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36:96847d42f010 | 64 | <peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/> |
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36:96847d42f010 | 65 | <peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANAFR" location="0x4003C000"/> |
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36:96847d42f010 | 66 | <peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1|SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCEN" location="0x40040000"/> |
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36:96847d42f010 | 67 | <peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/> |
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36:96847d42f010 | 68 | <peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&amp;0x1" id="CANCON1" location="0x40044000"/> |
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36:96847d42f010 | 69 | <peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&amp;0x1" id="CANCON2" location="0x40048000"/> |
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36:96847d42f010 | 70 | <peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&amp;0x1" id="MCPWM" location="0x400B8000"/> |
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36:96847d42f010 | 71 | </chip> |
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36:96847d42f010 | 72 | <processor> |
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36:96847d42f010 | 73 | <name gcc_name="cortex-m3">Cortex-M3</name> |
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36:96847d42f010 | 74 | <family>Cortex-M</family> |
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36:96847d42f010 | 75 | </processor> |
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36:96847d42f010 | 76 | <link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/> |
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36:96847d42f010 | 77 | </info> |
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36:96847d42f010 | 78 | </infoList> |
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36:96847d42f010 | 79 | </TargetConfig>{% endblock %} |