Akifumi Takahashi / PMRC16ch

Library to use my Photo MOS Relays Circuit having 16 or less channels.

Fork of PMRC4ch by Akifumi Takahashi

PMRC16ch.cpp@21:fa067e2a30f2, 2018-10-23 (annotated)

Committer:
aktk
Date:
Tue Oct 23 15:10:56 2018 +0000
Revision:
21:fa067e2a30f2
Parent:
20:26972de3cf90
Child:
42:a827fe9166b5
used in UIST2018 DEMO

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aktk 21:fa067e2a30f2 1
aktk 15:56703876e914 2 #include "PMRC16ch.h"
aktk 21:fa067e2a30f2 3 const uint32_t PMRC16ch::m_statearray[] = {
aktk 21:fa067e2a30f2 4 ALLGROUND, CH1, CH2, CH3, CH4, CH5, CH6, CH7, CH8, CH9,
aktk 21:fa067e2a30f2 5 CH10, CH11, CH12, CH13, CH14, CH15, CH16, ALLHiZ
aktk 21:fa067e2a30f2 6 };
aktk 15:56703876e914 7 // A constractor whose arguments have all default value
aktk 15:56703876e914 8 // is a default constractor.
aktk 15:56703876e914 9 PMRC16ch::PMRC16ch():
aktk 15:56703876e914 10 m_num_ch(16),
aktk 15:56703876e914 11 m_SCK(DigitalOut(p11)),
aktk 15:56703876e914 12 m_CLR(DigitalOut(p12)),
aktk 15:56703876e914 13 m_RCK(DigitalOut(p13)),
aktk 15:56703876e914 14 m_SER(DigitalOut(p14)),
aktk 15:56703876e914 15 m_OUT(DigitalIn(p10))
aktk 15:56703876e914 16 {
aktk 15:56703876e914 17 init();
aktk 15:56703876e914 18 }
aktk 21:fa067e2a30f2 19 PMRC16ch::PMRC16ch(
aktk 21:fa067e2a30f2 20 uint8_t arg_num_ch
aktk 21:fa067e2a30f2 21 ):
aktk 21:fa067e2a30f2 22 m_num_ch(arg_num_ch),
aktk 21:fa067e2a30f2 23 m_SCK(DigitalOut(p11)),
aktk 21:fa067e2a30f2 24 m_CLR(DigitalOut(p12)),
aktk 21:fa067e2a30f2 25 m_RCK(DigitalOut(p13)),
aktk 21:fa067e2a30f2 26 m_SER(DigitalOut(p14)),
aktk 21:fa067e2a30f2 27 m_OUT(DigitalIn(p10))
aktk 21:fa067e2a30f2 28 {
aktk 21:fa067e2a30f2 29 init();
aktk 21:fa067e2a30f2 30 }
aktk 21:fa067e2a30f2 31
aktk 15:56703876e914 32
aktk 15:56703876e914 33 PMRC16ch::PMRC16ch(
aktk 15:56703876e914 34 uint8_t arg_num_ch,
aktk 15:56703876e914 35 PinName arg_SCK,
aktk 15:56703876e914 36 PinName arg_CLR,
aktk 15:56703876e914 37 PinName arg_RCK,
aktk 15:56703876e914 38 PinName arg_SER,
aktk 15:56703876e914 39 PinName arg_OUT
aktk 15:56703876e914 40 ):
aktk 15:56703876e914 41 m_num_ch(arg_num_ch),
aktk 15:56703876e914 42 m_SCK(DigitalOut(arg_SCK)),
aktk 15:56703876e914 43 m_CLR(DigitalOut(arg_CLR)),
aktk 15:56703876e914 44 m_RCK(DigitalOut(arg_RCK)),
aktk 15:56703876e914 45 m_SER(DigitalOut(arg_SER)),
aktk 15:56703876e914 46 m_OUT(DigitalIn(arg_OUT))
aktk 15:56703876e914 47 {
aktk 15:56703876e914 48 init();
aktk 15:56703876e914 49 }
aktk 21:fa067e2a30f2 50 //------------------------------------------------------------------------------
aktk 15:56703876e914 51 void PMRC16ch::init()
aktk 15:56703876e914 52 {
aktk 15:56703876e914 53 m_CLR = 1;
aktk 15:56703876e914 54 m_SCK = m_RCK = 0;
aktk 21:fa067e2a30f2 55 allHiZ();
aktk 21:fa067e2a30f2 56 m_PMRC_mode = TWIN_ELECTRODES;
aktk 15:56703876e914 57 m_PMRC_POL = Cathodic;
aktk 15:56703876e914 58 }
aktk 15:56703876e914 59
aktk 20:26972de3cf90 60 void PMRC16ch::allGround()
aktk 15:56703876e914 61 {
aktk 21:fa067e2a30f2 62 if (m_PMRC_state == ALLGROUND) return;
aktk 15:56703876e914 63 sweep();
aktk 15:56703876e914 64 upload();
aktk 21:fa067e2a30f2 65 m_PMRC_state = ALLGROUND;
aktk 21:fa067e2a30f2 66 m_pos_stim = 0;
aktk 15:56703876e914 67 }
aktk 15:56703876e914 68
aktk 20:26972de3cf90 69 void PMRC16ch::allHiZ()
aktk 15:56703876e914 70 {
aktk 20:26972de3cf90 71 //reset shiftresister
aktk 20:26972de3cf90 72 m_CLR = 0;
aktk 20:26972de3cf90 73 update();
aktk 20:26972de3cf90 74 //enable insertion data to SR
aktk 20:26972de3cf90 75 m_CLR = 1;
aktk 20:26972de3cf90 76 upload();
aktk 21:fa067e2a30f2 77 m_PMRC_state = ALLHiZ;
aktk 21:fa067e2a30f2 78 m_pos_stim = 0;
aktk 21:fa067e2a30f2 79 }
aktk 21:fa067e2a30f2 80 //------------------------------------------------------------------------------
aktk 21:fa067e2a30f2 81 void PMRC16ch::setTwin(char arg_stim_ch, char arg_ref_ch)
aktk 21:fa067e2a30f2 82 {
aktk 21:fa067e2a30f2 83 m_PMRC_mode = TWIN_ELECTRODES;
aktk 21:fa067e2a30f2 84 m_PMRC_state = m_statearray[arg_stim_ch] + (m_statearray[arg_ref_ch] >> 1);
aktk 21:fa067e2a30f2 85 setBits(m_PMRC_state);
aktk 21:fa067e2a30f2 86 upload();
aktk 21:fa067e2a30f2 87 m_pos_stim = arg_stim_ch;
aktk 20:26972de3cf90 88 }
aktk 15:56703876e914 89
aktk 21:fa067e2a30f2 90 void PMRC16ch::setOvsO(char arg_ch)
aktk 15:56703876e914 91 {
aktk 21:fa067e2a30f2 92 int8_t num_of_shift;
aktk 15:56703876e914 93
aktk 21:fa067e2a30f2 94 num_of_shift = arg_ch - m_pos_stim;
aktk 21:fa067e2a30f2 95 // m_PMRC_mode == ONE_VS_THEOTHERS && m_pos_stim == 0
aktk 21:fa067e2a30f2 96 // => m_PMRC_state == ALLGROUND
aktk 21:fa067e2a30f2 97 if( num_of_shift < 0 || m_pos_stim == 0 || m_PMRC_mode != ONE_VS_THEOTHERS) {
aktk 15:56703876e914 98 sweep();
aktk 15:56703876e914 99 setStimbits();
aktk 21:fa067e2a30f2 100 num_of_shift = arg_ch - 1;
aktk 15:56703876e914 101 }
aktk 15:56703876e914 102 shiftby(num_of_shift);
aktk 21:fa067e2a30f2 103 m_PMRC_mode = ONE_VS_THEOTHERS;
aktk 21:fa067e2a30f2 104 m_PMRC_state = ALLGROUND + m_statearray[arg_ch];
aktk 21:fa067e2a30f2 105
aktk 15:56703876e914 106 upload();
aktk 21:fa067e2a30f2 107 m_pos_stim = arg_ch;
aktk 15:56703876e914 108 }
aktk 15:56703876e914 109
aktk 21:fa067e2a30f2 110 //------------------------------------------------------------------------------
aktk 15:56703876e914 111
aktk 15:56703876e914 112 void PMRC16ch::sweep()
aktk 15:56703876e914 113 {
aktk 21:fa067e2a30f2 114 uint32_t num_shift;
aktk 15:56703876e914 115
aktk 21:fa067e2a30f2 116 if(m_PMRC_mode != ONE_VS_THEOTHERS || m_PMRC_state == ALLHiZ) {
aktk 21:fa067e2a30f2 117 num_shift = m_num_ch;
aktk 21:fa067e2a30f2 118 } else if(m_PMRC_mode == ONE_VS_THEOTHERS) {
aktk 21:fa067e2a30f2 119 num_shift = m_num_ch - (m_pos_stim - 1);
aktk 21:fa067e2a30f2 120 }
aktk 21:fa067e2a30f2 121 shiftby(num_shift);
aktk 15:56703876e914 122 }
aktk 15:56703876e914 123
aktk 15:56703876e914 124 void PMRC16ch::shiftby(int arg_num)
aktk 15:56703876e914 125 {
aktk 15:56703876e914 126 for(int i = 0; i < arg_num; i++) {
aktk 16:e81a30a098dd 127 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 128 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 129 update();
aktk 16:e81a30a098dd 130 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 131 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 132 update();
aktk 15:56703876e914 133 }
aktk 15:56703876e914 134 }
aktk 15:56703876e914 135
aktk 15:56703876e914 136 void PMRC16ch::setStimbits()
aktk 15:56703876e914 137 {
aktk 16:e81a30a098dd 138 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 139 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 140 update();
aktk 16:e81a30a098dd 141 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 142 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 143 update();
aktk 15:56703876e914 144 m_PMRC_state = CH1;
aktk 15:56703876e914 145 }
aktk 21:fa067e2a30f2 146
aktk 21:fa067e2a30f2 147 void PMRC16ch::setBits(const uint32_t arg_bits)
aktk 21:fa067e2a30f2 148 {
aktk 21:fa067e2a30f2 149 uint8_t tmp_bit[2];
aktk 21:fa067e2a30f2 150 //reset shiftresister
aktk 21:fa067e2a30f2 151 m_CLR = 0;
aktk 21:fa067e2a30f2 152 update();
aktk 21:fa067e2a30f2 153 //enable insertion data to SR
aktk 21:fa067e2a30f2 154 m_CLR = 1;
aktk 21:fa067e2a30f2 155 for(int i = 0; i < m_num_ch; i++) {
aktk 21:fa067e2a30f2 156 tmp_bit[0] = 0b01 & (arg_bits >> (2 * i));
aktk 21:fa067e2a30f2 157 tmp_bit[1] = 0b01 & (arg_bits >> (2 * i + 1));
aktk 21:fa067e2a30f2 158 // if the chan. is not HiZ meaning Hi or Lw
aktk 21:fa067e2a30f2 159 if(tmp_bit[0] + tmp_bit[1] == 1) {
aktk 21:fa067e2a30f2 160 m_SER = (tmp_bit[0] ^ m_PMRC_POL); //XOR Polarity
aktk 21:fa067e2a30f2 161 update();
aktk 21:fa067e2a30f2 162 m_SER = (tmp_bit[1] ^ m_PMRC_POL); //XOR Polarity
aktk 21:fa067e2a30f2 163 update();
aktk 21:fa067e2a30f2 164 } else {
aktk 21:fa067e2a30f2 165 m_SER = (tmp_bit[0]);
aktk 21:fa067e2a30f2 166 update();
aktk 21:fa067e2a30f2 167 m_SER = (tmp_bit[1]);
aktk 21:fa067e2a30f2 168 update();
aktk 21:fa067e2a30f2 169 }
aktk 21:fa067e2a30f2 170 }
aktk 21:fa067e2a30f2 171 }
aktk 21:fa067e2a30f2 172 //------------------------------------------------------------------------------
aktk 15:56703876e914 173 void PMRC16ch::update()
aktk 15:56703876e914 174 {
aktk 15:56703876e914 175 //Shift-resister Clock update
aktk 15:56703876e914 176 m_SCK = 1;
aktk 15:56703876e914 177 m_SCK = 1;
aktk 15:56703876e914 178 m_SCK = 0;
aktk 15:56703876e914 179 m_SCK = 0;
aktk 15:56703876e914 180 }
aktk 15:56703876e914 181 void PMRC16ch::upload()
aktk 15:56703876e914 182 {
aktk 15:56703876e914 183 //FF Clock Update
aktk 15:56703876e914 184 m_RCK = 1;
aktk 15:56703876e914 185 m_RCK = 1;
aktk 15:56703876e914 186 m_RCK = 0;
aktk 15:56703876e914 187 m_RCK = 0;
aktk 15:56703876e914 188 }