Akifumi Takahashi / PMRC16ch

Library to use my Photo MOS Relays Circuit having 16 or less channels.

Fork of PMRC4ch by Akifumi Takahashi

PMRC16ch.cpp@16:e81a30a098dd, 2018-06-26 (annotated)

Committer:
aktk
Date:
Tue Jun 26 12:42:26 2018 +0000
Revision:
16:e81a30a098dd
Parent:
15:56703876e914
Child:
17:08a68860396b
modified the data to insert so that reflect the variable of POL: m_SER = hoge ^ m_PMRC_POL (xor POL)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aktk 15:56703876e914 1 #include "PMRC16ch.h"
aktk 15:56703876e914 2 // A constractor whose arguments have all default value
aktk 15:56703876e914 3 // is a default constractor.
aktk 15:56703876e914 4 PMRC16ch::PMRC16ch():
aktk 15:56703876e914 5 m_num_ch(16),
aktk 15:56703876e914 6 m_SCK(DigitalOut(p11)),
aktk 15:56703876e914 7 m_CLR(DigitalOut(p12)),
aktk 15:56703876e914 8 m_RCK(DigitalOut(p13)),
aktk 15:56703876e914 9 m_SER(DigitalOut(p14)),
aktk 15:56703876e914 10 m_OUT(DigitalIn(p10))
aktk 15:56703876e914 11 {
aktk 15:56703876e914 12 init();
aktk 15:56703876e914 13 }
aktk 15:56703876e914 14
aktk 15:56703876e914 15 PMRC16ch::PMRC16ch(
aktk 15:56703876e914 16 uint8_t arg_num_ch,
aktk 15:56703876e914 17 PinName arg_SCK,
aktk 15:56703876e914 18 PinName arg_CLR,
aktk 15:56703876e914 19 PinName arg_RCK,
aktk 15:56703876e914 20 PinName arg_SER,
aktk 15:56703876e914 21 PinName arg_OUT
aktk 15:56703876e914 22 ):
aktk 15:56703876e914 23 m_num_ch(arg_num_ch),
aktk 15:56703876e914 24 m_SCK(DigitalOut(arg_SCK)),
aktk 15:56703876e914 25 m_CLR(DigitalOut(arg_CLR)),
aktk 15:56703876e914 26 m_RCK(DigitalOut(arg_RCK)),
aktk 15:56703876e914 27 m_SER(DigitalOut(arg_SER)),
aktk 15:56703876e914 28 m_OUT(DigitalIn(arg_OUT))
aktk 15:56703876e914 29 {
aktk 15:56703876e914 30 init();
aktk 15:56703876e914 31 }
aktk 15:56703876e914 32
aktk 15:56703876e914 33 void PMRC16ch::init()
aktk 15:56703876e914 34 {
aktk 15:56703876e914 35 m_CLR = 1;
aktk 15:56703876e914 36 m_SCK = m_RCK = 0;
aktk 15:56703876e914 37 m_PMRC_state = NaN;
aktk 15:56703876e914 38 allOff();
aktk 15:56703876e914 39 m_PMRC_POL = Cathodic;
aktk 15:56703876e914 40 }
aktk 15:56703876e914 41
aktk 15:56703876e914 42 char PMRC16ch::allOff()
aktk 15:56703876e914 43 {
aktk 15:56703876e914 44 if (m_PMRC_state == ALLOFF) return 1;
aktk 15:56703876e914 45 /*
aktk 15:56703876e914 46 //reset shiftresister
aktk 15:56703876e914 47 m_CLR = 0;
aktk 15:56703876e914 48 update();
aktk 15:56703876e914 49 //enable insertion data to SR
aktk 15:56703876e914 50 m_CLR = 1;
aktk 15:56703876e914 51 */
aktk 15:56703876e914 52 //set all channel gnd
aktk 15:56703876e914 53 //shiftby(16);
aktk 15:56703876e914 54 sweep();
aktk 15:56703876e914 55 upload();
aktk 15:56703876e914 56 return static_cast<char>(m_PMRC_state = ALLOFF);
aktk 15:56703876e914 57 }
aktk 15:56703876e914 58
aktk 15:56703876e914 59 char PMRC16ch::setCh(State arg_state, Polarity arg_POL)
aktk 15:56703876e914 60 {
aktk 16:e81a30a098dd 61 m_PMRC_POL = arg_POL;
aktk 15:56703876e914 62 int num_of_shift = static_cast<int>(arg_state) - static_cast<int>(m_PMRC_state);
aktk 15:56703876e914 63
aktk 15:56703876e914 64 if( num_of_shift < 0 )
aktk 15:56703876e914 65 sweep();
aktk 15:56703876e914 66
aktk 15:56703876e914 67 if( m_PMRC_state == ALLOFF ) {
aktk 15:56703876e914 68 setStimbits();
aktk 15:56703876e914 69 num_of_shift = static_cast<char>(arg_state - 1);
aktk 15:56703876e914 70 }
aktk 15:56703876e914 71 shiftby(num_of_shift);
aktk 15:56703876e914 72 upload();
aktk 15:56703876e914 73
aktk 15:56703876e914 74 return static_cast<char>(m_PMRC_state = arg_state);
aktk 15:56703876e914 75 }
aktk 15:56703876e914 76 char PMRC16ch::setCh(char arg_state, Polarity arg_POL)
aktk 15:56703876e914 77 {
aktk 16:e81a30a098dd 78 m_PMRC_POL = arg_POL;
aktk 15:56703876e914 79 int8_t num_of_shift = arg_state - static_cast<int8_t>(m_PMRC_state);
aktk 15:56703876e914 80
aktk 15:56703876e914 81 if( num_of_shift < 0 )
aktk 15:56703876e914 82 sweep();
aktk 15:56703876e914 83
aktk 15:56703876e914 84 if( m_PMRC_state == ALLOFF ) {
aktk 15:56703876e914 85 setStimbits();
aktk 15:56703876e914 86 num_of_shift = static_cast<char>(arg_state - 1);
aktk 15:56703876e914 87 }
aktk 15:56703876e914 88 shiftby(num_of_shift);
aktk 15:56703876e914 89 upload();
aktk 15:56703876e914 90
aktk 15:56703876e914 91 return static_cast<char>(m_PMRC_state = static_cast<State>(arg_state));
aktk 15:56703876e914 92 }
aktk 15:56703876e914 93
aktk 15:56703876e914 94 void PMRC16ch::allHiZ()
aktk 15:56703876e914 95 {
aktk 15:56703876e914 96 //reset shiftresister
aktk 15:56703876e914 97 m_CLR = 0;
aktk 15:56703876e914 98 update();
aktk 15:56703876e914 99 //enable insertion data to SR
aktk 15:56703876e914 100 m_CLR = 1;
aktk 15:56703876e914 101 upload();
aktk 15:56703876e914 102 }
aktk 15:56703876e914 103
aktk 15:56703876e914 104 void PMRC16ch::setBits(const uint32_t bits, int num_of_bits, Polarity arg_POL)
aktk 15:56703876e914 105 {
aktk 16:e81a30a098dd 106 m_PMRC_POL = arg_POL;
aktk 15:56703876e914 107 //reset shiftresister
aktk 15:56703876e914 108 m_CLR = 0;
aktk 15:56703876e914 109 update();
aktk 15:56703876e914 110 //enable insertion data to SR
aktk 15:56703876e914 111 m_CLR = 1;
aktk 15:56703876e914 112 for(int i = 0; i < num_of_bits; i++){
aktk 16:e81a30a098dd 113 m_SER = (((bits >> i) & 0b0001) ^ m_PMRC_POL); //XOR Polarity
aktk 15:56703876e914 114 update();
aktk 15:56703876e914 115 }
aktk 15:56703876e914 116 upload();
aktk 15:56703876e914 117 }
aktk 15:56703876e914 118
aktk 15:56703876e914 119 void PMRC16ch::sweep()
aktk 15:56703876e914 120 {
aktk 15:56703876e914 121 int num_of_shift = (16 + 1) - static_cast<int>(m_PMRC_state);
aktk 15:56703876e914 122
aktk 15:56703876e914 123 shiftby(num_of_shift);
aktk 15:56703876e914 124 m_PMRC_state = ALLOFF;
aktk 15:56703876e914 125 }
aktk 15:56703876e914 126
aktk 15:56703876e914 127 void PMRC16ch::shiftby(int arg_num)
aktk 15:56703876e914 128 {
aktk 15:56703876e914 129 for(int i = 0; i < arg_num; i++) {
aktk 16:e81a30a098dd 130 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 131 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 132 update();
aktk 16:e81a30a098dd 133 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 134 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 135 update();
aktk 15:56703876e914 136 }
aktk 15:56703876e914 137 m_PMRC_state = static_cast<State>((static_cast<int>(m_PMRC_state) + arg_num) % (16 + 1));
aktk 15:56703876e914 138 }
aktk 15:56703876e914 139
aktk 15:56703876e914 140 void PMRC16ch::setStimbits()
aktk 15:56703876e914 141 {
aktk 16:e81a30a098dd 142 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 143 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 144 update();
aktk 16:e81a30a098dd 145 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 146 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 147 update();
aktk 15:56703876e914 148 m_PMRC_state = CH1;
aktk 15:56703876e914 149 }
aktk 15:56703876e914 150 void PMRC16ch::update()
aktk 15:56703876e914 151 {
aktk 15:56703876e914 152 //Shift-resister Clock update
aktk 15:56703876e914 153 m_SCK = 1;
aktk 15:56703876e914 154 m_SCK = 1;
aktk 15:56703876e914 155 m_SCK = 0;
aktk 15:56703876e914 156 m_SCK = 0;
aktk 15:56703876e914 157 }
aktk 15:56703876e914 158 void PMRC16ch::upload()
aktk 15:56703876e914 159 {
aktk 15:56703876e914 160 //FF Clock Update
aktk 15:56703876e914 161 m_RCK = 1;
aktk 15:56703876e914 162 m_RCK = 1;
aktk 15:56703876e914 163 m_RCK = 0;
aktk 15:56703876e914 164 m_RCK = 0;
aktk 15:56703876e914 165 }