Akifumi Takahashi / PMRC16ch

Library to use my Photo MOS Relays Circuit having 16 or less channels.

Fork of PMRC4ch by Akifumi Takahashi

PMRC16ch.h@39:c12b8ce1263b, 2018-11-07 (annotated)

Committer:
aktk
Date:
Wed Nov 07 18:44:34 2018 +0000
Revision:
39:c12b8ce1263b
Parent:
38:df92ed56a6a9
Child:
40:d30c68b7ec18
nennnekoshasshare

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aktk 34:013746eddc4a 1 /** PMRC16 class header file
aktk 37:0106e81d7dfc 2 * \file PMRC16ch.h
aktk 37:0106e81d7dfc 3 * \author Akifumi Takahashi
aktk 37:0106e81d7dfc 4 * \date 2016/dec/11-
aktk 31:0f491590ada9 5 * - ver.1; 8 channel
aktk 37:0106e81d7dfc 6 * \date 2018/jun/01-
aktk 31:0f491590ada9 7 * - ver.16.1; 16 channel
aktk 37:0106e81d7dfc 8 * \date 2018/jun/28-
aktk 31:0f491590ada9 9 * - ver.16.2; major change
aktk 29:9028bc6b5717 10 */
aktk 34:013746eddc4a 11 #ifndef PMRC_16CHANNEL_H
aktk 34:013746eddc4a 12 #define PMRC_16CHANNEL_H
aktk 29:9028bc6b5717 13 #include "mbed.h"
aktk 35:2329524f385a 14 /** PMCR16 nyaan
aktk 37:0106e81d7dfc 15 * \par About PMRC16 class
aktk 26:a47ab67a4d12 16 * - A Program with which to control Photo MOS Relay Circuit
aktk 15:56703876e914 17 * for 16 channels Electric Stimulation.
aktk 26:a47ab67a4d12 18 * - Photo Couplers are controlled by Shift Resisters. So this lib serves
aktk 22:4aad836d3333 19 * shift resister's utility.
aktk 23:cea3ec410735 20 *
aktk 37:0106e81d7dfc 21 * \par Image of Photo MOS Relay Array
aktk 25:953a60ea0e64 22 * - 32 Photo MOS Relay IN
aktk 25:953a60ea0e64 23 * - 16 channel OUT
aktk 34:013746eddc4a 24 *
aktk 37:0106e81d7dfc 25 * \verbatim
aktk 31:0f491590ada9 26 * +--i o----+----i o--+
aktk 31:0f491590ada9 27 * | [PMR01-1] | [PMR01-2] |
aktk 31:0f491590ada9 28 * | (ch1(B)out) |
aktk 31:0f491590ada9 29 * | |
aktk 31:0f491590ada9 30 * +--i o----+----i o--+
aktk 31:0f491590ada9 31 * | [PMR02-1] | [PMR02-2] |
aktk 31:0f491590ada9 32 * | (ch2(R)out) |
aktk 31:0f491590ada9 33 * | |
aktk 31:0f491590ada9 34 * . . .
aktk 31:0f491590ada9 35 * . . .
aktk 31:0f491590ada9 36 * . . .
aktk 31:0f491590ada9 37 * Vpp GND
aktk 37:0106e81d7dfc 38 * \endverbatim
aktk 24:4714402606f0 39 *
aktk 37:0106e81d7dfc 40 * \par Info. Shit-Resister circuit board
aktk 24:4714402606f0 41 * - nOE is connected to GND
aktk 34:013746eddc4a 42 *
aktk 37:0106e81d7dfc 43 * \verbatim
aktk 15:56703876e914 44 * in
aktk 15:56703876e914 45 * ->[PMR01-1]->[PMR01-2]->[PMR02-1]->[PMR02-2]
aktk 15:56703876e914 46 * ->[PMR03-1]->[PMR03-2]->[PMR04-1]->[PMR04-2]
aktk 15:56703876e914 47 * ->[PMR05-1]->[PMR05-2]->[PMR06-1]->[PMR06-2]
aktk 15:56703876e914 48 * ->[PMR07-1]->[PMR07-2]->[PMR08-1]->[PMR08-2]
aktk 15:56703876e914 49 * ->[PMR09-1]->[PMR09-2]->[PMR10-1]->[PMR10-2]
aktk 15:56703876e914 50 * ->[PMR11-1]->[PMR11-2]->[PMR12-1]->[PMR12-2]
aktk 15:56703876e914 51 * ->[PMR13-1]->[PMR13-2]->[PMR14-1]->[PMR14-2]
aktk 15:56703876e914 52 * ->[PMR15-1]->[PMR15-2]->[PMR16-1]->[PMR16-2]
aktk 15:56703876e914 53 * ->out
aktk 37:0106e81d7dfc 54 * \endverbatim
aktk 24:4714402606f0 55 *
aktk 37:0106e81d7dfc 56 * \version 1
aktk 34:013746eddc4a 57 * - 2016/dec/11-
aktk 36:d365db06cf17 58 * - program bersion for 8 channel circuit
aktk 37:0106e81d7dfc 59 * \version 16.1
aktk 34:013746eddc4a 60 * - 2018/jun/01-
aktk 35:2329524f385a 61 * - 16 channel version
aktk 37:0106e81d7dfc 62 * \version 16.2
aktk 34:013746eddc4a 63 * - 2018/jun/28-
aktk 34:013746eddc4a 64 * - major change
aktk 37:0106e81d7dfc 65 * \version 16.x
aktk 15:56703876e914 66 */
aktk 15:56703876e914 67 class PMRC16ch
aktk 15:56703876e914 68 {
aktk 15:56703876e914 69 public:
aktk 15:56703876e914 70 //
aktk 38:df92ed56a6a9 71 /// \par Constructors
aktk 15:56703876e914 72 //
aktk 38:df92ed56a6a9 73 /// Constructor default
aktk 15:56703876e914 74 PMRC16ch();
aktk 38:df92ed56a6a9 75 /// Constructor with setting num of channels
aktk 15:56703876e914 76 PMRC16ch(
aktk 39:c12b8ce1263b 77 uint8_t arg_num_ch ///<[in] number of channels to use
aktk 21:fa067e2a30f2 78 );
aktk 38:df92ed56a6a9 79 //* Construxtor with full configuration
aktk 38:df92ed56a6a9 80 /**
aktk 38:df92ed56a6a9 81 * \par Avalable Setting
aktk 38:df92ed56a6a9 82 * - number of channels to use
aktk 38:df92ed56a6a9 83 * - pin settings
aktk 38:df92ed56a6a9 84 */
aktk 21:fa067e2a30f2 85 PMRC16ch(
aktk 39:c12b8ce1263b 86 uint8_t arg_num_ch, ///<[in] number of channels to use
aktk 39:c12b8ce1263b 87 PinName arg_SCK, ///<[in] pin of shift registor clock
aktk 39:c12b8ce1263b 88 PinName arg_CLR, ///<[in] pin to clear the shift registor
aktk 39:c12b8ce1263b 89 PinName arg_RCK, ///<[in] pin of storage registor (buffer) clock
aktk 39:c12b8ce1263b 90 PinName arg_SER, ///<[in] pin to insert data
aktk 39:c12b8ce1263b 91 PinName arg_OUT ///<[in] pin to receive overflowed bit
aktk 19:1112aeb5cddd 92 );
aktk 15:56703876e914 93
aktk 15:56703876e914 94 // Const.
aktk 19:1112aeb5cddd 95 enum State {
aktk 21:fa067e2a30f2 96 ALLGROUND = 0x55555555,
aktk 21:fa067e2a30f2 97 CH1 = /*1V*/0b10000000000000000000000000000000/*16G*/,
aktk 21:fa067e2a30f2 98 CH2 = /*1V*/0b00100000000000000000000000000000/*16G*/,
aktk 21:fa067e2a30f2 99 CH3 = /*1V*/0b00001000000000000000000000000000/*16G*/,
aktk 21:fa067e2a30f2 100 CH4 = /*1V*/0b00000010000000000000000000000000/*16G*/,
aktk 21:fa067e2a30f2 101 CH5 = /*1V*/0b00000000100000000000000000000000/*16G*/,
aktk 21:fa067e2a30f2 102 CH6 = /*1V*/0b00000000001000000000000000000000/*16G*/,
aktk 21:fa067e2a30f2 103 CH7 = /*1V*/0b00000000000010000000000000000000/*16G*/,
aktk 21:fa067e2a30f2 104 CH8 = /*1V*/0b00000000000000100000000000000000/*16G*/,
aktk 21:fa067e2a30f2 105 CH9 = /*1V*/0b00000000000000001000000000000000/*16G*/,
aktk 21:fa067e2a30f2 106 CH10= /*1V*/0b00000000000000000010000000000000/*16G*/,
aktk 21:fa067e2a30f2 107 CH11= /*1V*/0b00000000000000000000100000000000/*16G*/,
aktk 21:fa067e2a30f2 108 CH12= /*1V*/0b00000000000000000000001000000000/*16G*/,
aktk 21:fa067e2a30f2 109 CH13= /*1V*/0b00000000000000000000000010000000/*16G*/,
aktk 21:fa067e2a30f2 110 CH14= /*1V*/0b00000000000000000000000000100000/*16G*/,
aktk 21:fa067e2a30f2 111 CH15= /*1V*/0b00000000000000000000000000001000/*16G*/,
aktk 21:fa067e2a30f2 112 CH16= /*1V*/0b00000000000000000000000000000010/*16G*/,
aktk 21:fa067e2a30f2 113 ALLHiZ = 0x00000000
aktk 19:1112aeb5cddd 114 };
aktk 15:56703876e914 115 enum Polarity {Anodic = 0, Cathodic = 1};
aktk 21:fa067e2a30f2 116 enum StimMode {ONE_VS_THEOTHERS, TWIN_ELECTRODES};
aktk 15:56703876e914 117 //
aktk 21:fa067e2a30f2 118 // Function to prepare channels
aktk 15:56703876e914 119 //
aktk 20:26972de3cf90 120 void allGround();
aktk 15:56703876e914 121 void allHiZ();
aktk 21:fa067e2a30f2 122 void setPol(Polarity pol); //inline definition
aktk 21:fa067e2a30f2 123 void setOvsO(char ch);
aktk 21:fa067e2a30f2 124 void setTwin(char stim_ch, char ref_ch);
aktk 15:56703876e914 125 //
aktk 15:56703876e914 126 // Function to get prameter
aktk 15:56703876e914 127 //
aktk 21:fa067e2a30f2 128 uint32_t getState(); //inline definition
aktk 21:fa067e2a30f2 129 bool getPol(); //inline definition
aktk 15:56703876e914 130
aktk 15:56703876e914 131 private:
aktk 21:fa067e2a30f2 132 // The number of channels to use
aktk 21:fa067e2a30f2 133 const uint8_t m_num_ch;
aktk 15:56703876e914 134 //
aktk 15:56703876e914 135 // Sig var to controll PRM circuit
aktk 15:56703876e914 136 //
aktk 15:56703876e914 137 DigitalOut m_SCK; // Shift-resister's clock
aktk 15:56703876e914 138 DigitalOut m_CLR; // To use when you want to clear shift-resister
aktk 15:56703876e914 139 DigitalOut m_RCK; // FF's clock
aktk 15:56703876e914 140 DigitalOut m_SER; // Serial input to shift data in a shift-resister
aktk 15:56703876e914 141 DigitalIn m_OUT; // Output data overflowed from shift-resister
aktk 21:fa067e2a30f2 142 //
aktk 21:fa067e2a30f2 143 // Var of state
aktk 21:fa067e2a30f2 144 //
aktk 21:fa067e2a30f2 145 // Position of stimulation bits
aktk 21:fa067e2a30f2 146 // 0: no stimbits, 1~m_num_ch: channel of stimulation
aktk 21:fa067e2a30f2 147 uint32_t m_pos_stim;
aktk 21:fa067e2a30f2 148 static const uint32_t m_statearray[];
aktk 21:fa067e2a30f2 149 uint32_t m_PMRC_state;
aktk 21:fa067e2a30f2 150 Polarity m_PMRC_POL;
aktk 21:fa067e2a30f2 151 StimMode m_PMRC_mode;
aktk 15:56703876e914 152 // Initialization
aktk 15:56703876e914 153 void init();
aktk 15:56703876e914 154 //
aktk 21:fa067e2a30f2 155 // Function to control buffer of shift-resister
aktk 15:56703876e914 156 //
aktk 15:56703876e914 157 // shift the bits arbitary times
aktk 15:56703876e914 158 void shiftby(int times);
aktk 21:fa067e2a30f2 159 // the function with which to rapidly set it all-ground
aktk 15:56703876e914 160 void sweep();
aktk 15:56703876e914 161 // set the simulation bits of 01
aktk 15:56703876e914 162 void setStimbits();
aktk 21:fa067e2a30f2 163 // set all bits arbitarily
aktk 21:fa067e2a30f2 164 void setBits(const uint32_t bits);
aktk 21:fa067e2a30f2 165 //
aktk 21:fa067e2a30f2 166 // Clock Function
aktk 21:fa067e2a30f2 167 //
aktk 15:56703876e914 168 //update the clock of shift-resister
aktk 15:56703876e914 169 void update();
aktk 15:56703876e914 170 // output the data by uploading them to FF Resitors
aktk 15:56703876e914 171 void upload();
aktk 15:56703876e914 172 };
aktk 21:fa067e2a30f2 173 inline void PMRC16ch::setPol(Polarity arg_pol)
aktk 21:fa067e2a30f2 174 {
aktk 21:fa067e2a30f2 175 m_PMRC_POL = arg_pol;
aktk 21:fa067e2a30f2 176 }
aktk 20:26972de3cf90 177 inline uint32_t PMRC16ch::getState()
aktk 15:56703876e914 178 {
aktk 21:fa067e2a30f2 179 return m_PMRC_state;
aktk 15:56703876e914 180 }
aktk 15:56703876e914 181 inline bool PMRC16ch::getPol()
aktk 15:56703876e914 182 {
aktk 15:56703876e914 183 //return false if cathodic
aktk 15:56703876e914 184 //return true if anodic
aktk 15:56703876e914 185 return static_cast<bool>(m_PMRC_POL);
aktk 15:56703876e914 186 }
aktk 15:56703876e914 187 #endif