Library to use my Photo MOS Relays Circuit having 16 or less channels.

Fork of PMRC4ch by Akifumi Takahashi

Committer:
aktk
Date:
Tue Nov 20 20:55:37 2018 +0000
Revision:
43:03e875137433
Parent:
42:a827fe9166b5
fixed compile error

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aktk 21:fa067e2a30f2 1
aktk 15:56703876e914 2 #include "PMRC16ch.h"
aktk 21:fa067e2a30f2 3 const uint32_t PMRC16ch::m_statearray[] = {
aktk 21:fa067e2a30f2 4 ALLGROUND, CH1, CH2, CH3, CH4, CH5, CH6, CH7, CH8, CH9,
aktk 21:fa067e2a30f2 5 CH10, CH11, CH12, CH13, CH14, CH15, CH16, ALLHiZ
aktk 21:fa067e2a30f2 6 };
aktk 15:56703876e914 7 // A constractor whose arguments have all default value
aktk 15:56703876e914 8 // is a default constractor.
aktk 15:56703876e914 9 PMRC16ch::PMRC16ch():
aktk 15:56703876e914 10 m_num_ch(16),
aktk 15:56703876e914 11 m_SCK(DigitalOut(p11)),
aktk 15:56703876e914 12 m_CLR(DigitalOut(p12)),
aktk 15:56703876e914 13 m_RCK(DigitalOut(p13)),
aktk 15:56703876e914 14 m_SER(DigitalOut(p14)),
aktk 15:56703876e914 15 m_OUT(DigitalIn(p10))
aktk 15:56703876e914 16 {
aktk 15:56703876e914 17 init();
aktk 15:56703876e914 18 }
aktk 21:fa067e2a30f2 19 PMRC16ch::PMRC16ch(
aktk 21:fa067e2a30f2 20 uint8_t arg_num_ch
aktk 21:fa067e2a30f2 21 ):
aktk 21:fa067e2a30f2 22 m_num_ch(arg_num_ch),
aktk 21:fa067e2a30f2 23 m_SCK(DigitalOut(p11)),
aktk 21:fa067e2a30f2 24 m_CLR(DigitalOut(p12)),
aktk 21:fa067e2a30f2 25 m_RCK(DigitalOut(p13)),
aktk 21:fa067e2a30f2 26 m_SER(DigitalOut(p14)),
aktk 21:fa067e2a30f2 27 m_OUT(DigitalIn(p10))
aktk 21:fa067e2a30f2 28 {
aktk 21:fa067e2a30f2 29 init();
aktk 21:fa067e2a30f2 30 }
aktk 21:fa067e2a30f2 31
aktk 15:56703876e914 32
aktk 15:56703876e914 33 PMRC16ch::PMRC16ch(
aktk 15:56703876e914 34 uint8_t arg_num_ch,
aktk 15:56703876e914 35 PinName arg_SCK,
aktk 15:56703876e914 36 PinName arg_CLR,
aktk 15:56703876e914 37 PinName arg_RCK,
aktk 15:56703876e914 38 PinName arg_SER,
aktk 15:56703876e914 39 PinName arg_OUT
aktk 15:56703876e914 40 ):
aktk 15:56703876e914 41 m_num_ch(arg_num_ch),
aktk 15:56703876e914 42 m_SCK(DigitalOut(arg_SCK)),
aktk 15:56703876e914 43 m_CLR(DigitalOut(arg_CLR)),
aktk 15:56703876e914 44 m_RCK(DigitalOut(arg_RCK)),
aktk 15:56703876e914 45 m_SER(DigitalOut(arg_SER)),
aktk 15:56703876e914 46 m_OUT(DigitalIn(arg_OUT))
aktk 15:56703876e914 47 {
aktk 15:56703876e914 48 init();
aktk 15:56703876e914 49 }
aktk 42:a827fe9166b5 50 // ----------------------------------------------------------------------------
aktk 15:56703876e914 51 void PMRC16ch::init()
aktk 15:56703876e914 52 {
aktk 15:56703876e914 53 m_CLR = 1;
aktk 15:56703876e914 54 m_SCK = m_RCK = 0;
aktk 21:fa067e2a30f2 55 allHiZ();
aktk 21:fa067e2a30f2 56 m_PMRC_mode = TWIN_ELECTRODES;
aktk 15:56703876e914 57 m_PMRC_POL = Cathodic;
aktk 15:56703876e914 58 }
aktk 15:56703876e914 59
aktk 20:26972de3cf90 60 void PMRC16ch::allGround()
aktk 15:56703876e914 61 {
aktk 21:fa067e2a30f2 62 if (m_PMRC_state == ALLGROUND) return;
aktk 15:56703876e914 63 sweep();
aktk 15:56703876e914 64 upload();
aktk 21:fa067e2a30f2 65 m_PMRC_state = ALLGROUND;
aktk 21:fa067e2a30f2 66 m_pos_stim = 0;
aktk 15:56703876e914 67 }
aktk 15:56703876e914 68
aktk 20:26972de3cf90 69 void PMRC16ch::allHiZ()
aktk 15:56703876e914 70 {
aktk 20:26972de3cf90 71 //reset shiftresister
aktk 20:26972de3cf90 72 m_CLR = 0;
aktk 20:26972de3cf90 73 update();
aktk 20:26972de3cf90 74 //enable insertion data to SR
aktk 20:26972de3cf90 75 m_CLR = 1;
aktk 20:26972de3cf90 76 upload();
aktk 21:fa067e2a30f2 77 m_PMRC_state = ALLHiZ;
aktk 21:fa067e2a30f2 78 m_pos_stim = 0;
aktk 21:fa067e2a30f2 79 }
aktk 42:a827fe9166b5 80 // ----------------------------------------------------------------------------
aktk 21:fa067e2a30f2 81 void PMRC16ch::setTwin(char arg_stim_ch, char arg_ref_ch)
aktk 21:fa067e2a30f2 82 {
aktk 21:fa067e2a30f2 83 m_PMRC_mode = TWIN_ELECTRODES;
aktk 21:fa067e2a30f2 84 m_PMRC_state = m_statearray[arg_stim_ch] + (m_statearray[arg_ref_ch] >> 1);
aktk 21:fa067e2a30f2 85 setBits(m_PMRC_state);
aktk 21:fa067e2a30f2 86 upload();
aktk 21:fa067e2a30f2 87 m_pos_stim = arg_stim_ch;
aktk 20:26972de3cf90 88 }
aktk 15:56703876e914 89
aktk 42:a827fe9166b5 90 void PMRC16ch::setTrio(char arg_stim_ch, char arg_ref_ch1, char arg_ref_ch2)
aktk 42:a827fe9166b5 91 {
aktk 42:a827fe9166b5 92 m_PMRC_mode = TWIN_ELECTRODES;
aktk 42:a827fe9166b5 93 m_PMRC_state = m_statearray[arg_stim_ch]
aktk 43:03e875137433 94 + (m_statearray[arg_ref_ch1] >> 1)
aktk 42:a827fe9166b5 95 + (m_statearray[arg_ref_ch2] >> 1);
aktk 42:a827fe9166b5 96 setBits(m_PMRC_state);
aktk 42:a827fe9166b5 97 upload();
aktk 42:a827fe9166b5 98 m_pos_stim = arg_stim_ch;
aktk 42:a827fe9166b5 99 }
aktk 42:a827fe9166b5 100
aktk 21:fa067e2a30f2 101 void PMRC16ch::setOvsO(char arg_ch)
aktk 15:56703876e914 102 {
aktk 21:fa067e2a30f2 103 int8_t num_of_shift;
aktk 15:56703876e914 104
aktk 21:fa067e2a30f2 105 num_of_shift = arg_ch - m_pos_stim;
aktk 21:fa067e2a30f2 106 // m_PMRC_mode == ONE_VS_THEOTHERS && m_pos_stim == 0
aktk 21:fa067e2a30f2 107 // => m_PMRC_state == ALLGROUND
aktk 21:fa067e2a30f2 108 if( num_of_shift < 0 || m_pos_stim == 0 || m_PMRC_mode != ONE_VS_THEOTHERS) {
aktk 15:56703876e914 109 sweep();
aktk 15:56703876e914 110 setStimbits();
aktk 21:fa067e2a30f2 111 num_of_shift = arg_ch - 1;
aktk 15:56703876e914 112 }
aktk 15:56703876e914 113 shiftby(num_of_shift);
aktk 21:fa067e2a30f2 114 m_PMRC_mode = ONE_VS_THEOTHERS;
aktk 21:fa067e2a30f2 115 m_PMRC_state = ALLGROUND + m_statearray[arg_ch];
aktk 21:fa067e2a30f2 116
aktk 15:56703876e914 117 upload();
aktk 21:fa067e2a30f2 118 m_pos_stim = arg_ch;
aktk 15:56703876e914 119 }
aktk 15:56703876e914 120
aktk 42:a827fe9166b5 121 // ----------------------------------------------------------------------------
aktk 15:56703876e914 122
aktk 15:56703876e914 123 void PMRC16ch::sweep()
aktk 15:56703876e914 124 {
aktk 21:fa067e2a30f2 125 uint32_t num_shift;
aktk 15:56703876e914 126
aktk 21:fa067e2a30f2 127 if(m_PMRC_mode != ONE_VS_THEOTHERS || m_PMRC_state == ALLHiZ) {
aktk 21:fa067e2a30f2 128 num_shift = m_num_ch;
aktk 21:fa067e2a30f2 129 } else if(m_PMRC_mode == ONE_VS_THEOTHERS) {
aktk 21:fa067e2a30f2 130 num_shift = m_num_ch - (m_pos_stim - 1);
aktk 21:fa067e2a30f2 131 }
aktk 21:fa067e2a30f2 132 shiftby(num_shift);
aktk 15:56703876e914 133 }
aktk 15:56703876e914 134
aktk 15:56703876e914 135 void PMRC16ch::shiftby(int arg_num)
aktk 15:56703876e914 136 {
aktk 15:56703876e914 137 for(int i = 0; i < arg_num; i++) {
aktk 16:e81a30a098dd 138 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 139 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 140 update();
aktk 16:e81a30a098dd 141 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 142 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 143 update();
aktk 15:56703876e914 144 }
aktk 15:56703876e914 145 }
aktk 15:56703876e914 146
aktk 15:56703876e914 147 void PMRC16ch::setStimbits()
aktk 15:56703876e914 148 {
aktk 16:e81a30a098dd 149 // insert 0 XOR Polarity
aktk 16:e81a30a098dd 150 m_SER = 0 ^ m_PMRC_POL;
aktk 15:56703876e914 151 update();
aktk 16:e81a30a098dd 152 // insert 1 XOR Polarity
aktk 16:e81a30a098dd 153 m_SER = 1 ^ m_PMRC_POL;
aktk 15:56703876e914 154 update();
aktk 15:56703876e914 155 m_PMRC_state = CH1;
aktk 15:56703876e914 156 }
aktk 21:fa067e2a30f2 157
aktk 21:fa067e2a30f2 158 void PMRC16ch::setBits(const uint32_t arg_bits)
aktk 21:fa067e2a30f2 159 {
aktk 42:a827fe9166b5 160 /* arg_bits: 0b xx xx xx xx ... xx xx xx
aktk 42:a827fe9166b5 161 * ch1 <- ->ch[m_num_ch]
aktk 42:a827fe9166b5 162 */
aktk 42:a827fe9166b5 163
aktk 21:fa067e2a30f2 164 uint8_t tmp_bit[2];
aktk 21:fa067e2a30f2 165 //reset shiftresister
aktk 21:fa067e2a30f2 166 m_CLR = 0;
aktk 21:fa067e2a30f2 167 update();
aktk 21:fa067e2a30f2 168 //enable insertion data to SR
aktk 21:fa067e2a30f2 169 m_CLR = 1;
aktk 21:fa067e2a30f2 170 for(int i = 0; i < m_num_ch; i++) {
aktk 21:fa067e2a30f2 171 tmp_bit[0] = 0b01 & (arg_bits >> (2 * i));
aktk 21:fa067e2a30f2 172 tmp_bit[1] = 0b01 & (arg_bits >> (2 * i + 1));
aktk 21:fa067e2a30f2 173 // if the chan. is not HiZ meaning Hi or Lw
aktk 21:fa067e2a30f2 174 if(tmp_bit[0] + tmp_bit[1] == 1) {
aktk 21:fa067e2a30f2 175 m_SER = (tmp_bit[0] ^ m_PMRC_POL); //XOR Polarity
aktk 21:fa067e2a30f2 176 update();
aktk 21:fa067e2a30f2 177 m_SER = (tmp_bit[1] ^ m_PMRC_POL); //XOR Polarity
aktk 21:fa067e2a30f2 178 update();
aktk 21:fa067e2a30f2 179 } else {
aktk 21:fa067e2a30f2 180 m_SER = (tmp_bit[0]);
aktk 21:fa067e2a30f2 181 update();
aktk 21:fa067e2a30f2 182 m_SER = (tmp_bit[1]);
aktk 21:fa067e2a30f2 183 update();
aktk 21:fa067e2a30f2 184 }
aktk 21:fa067e2a30f2 185 }
aktk 21:fa067e2a30f2 186 }
aktk 42:a827fe9166b5 187 // ----------------------------------------------------------------------------
aktk 15:56703876e914 188 void PMRC16ch::update()
aktk 15:56703876e914 189 {
aktk 15:56703876e914 190 //Shift-resister Clock update
aktk 15:56703876e914 191 m_SCK = 1;
aktk 15:56703876e914 192 m_SCK = 1;
aktk 15:56703876e914 193 m_SCK = 0;
aktk 15:56703876e914 194 m_SCK = 0;
aktk 15:56703876e914 195 }
aktk 15:56703876e914 196 void PMRC16ch::upload()
aktk 15:56703876e914 197 {
aktk 15:56703876e914 198 //FF Clock Update
aktk 15:56703876e914 199 m_RCK = 1;
aktk 15:56703876e914 200 m_RCK = 1;
aktk 15:56703876e914 201 m_RCK = 0;
aktk 15:56703876e914 202 m_RCK = 0;
aktk 15:56703876e914 203 }