a hambi / Mbed 2 deprecated Phase_Ramp_from_DDS_for_CQED

With the DDS RAM registers a desired function "phase (time)" can be implemented for one of the output channels and triggered either by the serial terminal or by an external signal on one of the mbed pins.

Dependencies:   mbed

main.cpp@1:163c47ba88bd, 2012-11-09 (annotated)

Committer:
ahambi
Date:
Fri Nov 09 16:27:38 2012 +0000
Revision:
1:163c47ba88bd
Parent:
0:461186c994f0 
With the DDS RAM registers a desired function "phase (time)" can be implemented for one of the output channels and triggered either by the serial terminal or by an external signal on one of the mbed pins.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ahambi 1:163c47ba88bd 1 // ****************************************
ahambi 1:163c47ba88bd 2 // *** phase ramps with the RAM ***
ahambi 0:461186c994f0 3 // ****************************************
ahambi 1:163c47ba88bd 4 // This program basically contains the same code as "Frequency_ramps_with_RAM".
ahambi 0:461186c994f0 5
ahambi 1:163c47ba88bd 6 /* Changes to be made comparing to Frequency Tuning via RAM:
ahambi 1:163c47ba88bd 7
ahambi 0:461186c994f0 8 CFR1: RAM Destination bit <30>=1 --> RAM drives the Phase Word
ahambi 0:461186c994f0 9 RAM write operation:
ahambi 0:461186c994f0 10 phase[j] = phase0 + (phase1-phase0)/trise*j*trise/RAM_used;
ahambi 0:461186c994f0 11 PHWO[j] = 0x3FFF & int(phase[j]/360.0*pow(2.0,14.0)); // PHWO = 0011 FFF = 3FFF --> implemented in PHWO_func
ahambi 0:461186c994f0 12 DDS.RAM_write_FTWO((PHWO[i] << 18) & 0xFFFFFFFF);
ahambi 0:461186c994f0 13 */
ahambi 0:461186c994f0 14
ahambi 0:461186c994f0 15 #include "mbed.h"
ahambi 0:461186c994f0 16 #include "DDS.h"
ahambi 0:461186c994f0 17
ahambi 0:461186c994f0 18 Serial pc(USBTX, USBRX);
ahambi 0:461186c994f0 19 DigitalOut myled(LED1);
ahambi 0:461186c994f0 20 DigitalOut cs2(p11);
ahambi 0:461186c994f0 21 DigitalOut cs1(p8);
ahambi 0:461186c994f0 22 DigitalOut rst(p9);
ahambi 0:461186c994f0 23 DigitalOut update(p10);
ahambi 0:461186c994f0 24 DigitalOut ps0(p12);
ahambi 0:461186c994f0 25 DigitalOut ps1(p14);
ahambi 0:461186c994f0 26 DigitalOut trigger(p13);
ahambi 0:461186c994f0 27 DigitalOut trigger1(p23);
ahambi 0:461186c994f0 28 DigitalOut trigger2(p24);
ahambi 0:461186c994f0 29 InterruptIn mcs(p21); //InterruptIn description: http://mbed.org/handbook/InterruptIn
ahambi 0:461186c994f0 30 DigitalIn mexp(p22); //DigitalIn description: http://mbed.org/handbook/DigitalIn
ahambi 0:461186c994f0 31 DDS DDS(p5, p6, p7, p8, p9, p10);
ahambi 0:461186c994f0 32
ahambi 0:461186c994f0 33 // counting variables:
ahambi 0:461186c994f0 34 int i = 0;
ahambi 0:461186c994f0 35 int j = 0;
ahambi 0:461186c994f0 36 // frequency of reference clock connected to the DDS board:
ahambi 0:461186c994f0 37 double ref_clock = 400.0e6;
ahambi 0:461186c994f0 38
ahambi 0:461186c994f0 39 // ##################### definition of functions ############################
ahambi 0:461186c994f0 40 int reset() {
ahambi 0:461186c994f0 41 rst = 0;
ahambi 0:461186c994f0 42 rst = 1;
ahambi 0:461186c994f0 43 wait(0.1);
ahambi 0:461186c994f0 44 rst = 0 ;
ahambi 0:461186c994f0 45 return 0;
ahambi 0:461186c994f0 46 }
ahambi 0:461186c994f0 47
ahambi 0:461186c994f0 48 // choosing one of the two output channels is done with this functions:
ahambi 0:461186c994f0 49 int ch_1() {
ahambi 0:461186c994f0 50 cs1 = 0;
ahambi 0:461186c994f0 51 cs2 = 1;
ahambi 0:461186c994f0 52 return 0;
ahambi 0:461186c994f0 53 }
ahambi 0:461186c994f0 54 int ch_2() {
ahambi 0:461186c994f0 55 cs1 = 1;
ahambi 0:461186c994f0 56 cs2 = 0;
ahambi 0:461186c994f0 57 return 0;
ahambi 0:461186c994f0 58 }
ahambi 0:461186c994f0 59
ahambi 1:163c47ba88bd 60 // This function always rounds values up (in mode ?? of the DDS a problem occurs
ahambi 1:163c47ba88bd 61 // if the final value is not reached
ahambi 0:461186c994f0 62 int round(double a) {
ahambi 0:461186c994f0 63 return int(a + 0.5);
ahambi 0:461186c994f0 64 }
ahambi 0:461186c994f0 65
ahambi 1:163c47ba88bd 66 // calculate Frequency tuning word (FTWO):
ahambi 0:461186c994f0 67 uint32_t FTWO_func(double frequency) {
ahambi 0:461186c994f0 68 return 0xFFFFFFFF & round(frequency/ref_clock*pow(2.0,32.0));
ahambi 0:461186c994f0 69 }
ahambi 1:163c47ba88bd 70
ahambi 1:163c47ba88bd 71 // calculate Phase tuning word (PHWO):
ahambi 0:461186c994f0 72 uint32_t PHWO_func(double phase) {
ahambi 0:461186c994f0 73 return 0x3FFF & int(phase/360.0*pow(2.0,14.0));
ahambi 0:461186c994f0 74 }
ahambi 0:461186c994f0 75
ahambi 1:163c47ba88bd 76 // RSCW0, RSCW1, RSCW2 and RSCW3 are the RAM profiles of the DDS which can be filled with different
ahambi 1:163c47ba88bd 77 // parts of the ramp:
ahambi 1:163c47ba88bd 78
ahambi 1:163c47ba88bd 79 // ************* RSCW0 ******************
ahambi 0:461186c994f0 80 void writeRSCW0(int r0, int r1, uint32_t RSCW, double f[]) {
ahambi 0:461186c994f0 81 int R_used = r1-r0;
ahambi 0:461186c994f0 82 uint32_t PHWO[R_used];
ahambi 0:461186c994f0 83 ps0 = 0;
ahambi 0:461186c994f0 84 ps1 = 0;
ahambi 0:461186c994f0 85 update = 0;
ahambi 0:461186c994f0 86 // Instruction byte: page 25, we want to write (0), so 0100
ahambi 0:461186c994f0 87 // + internal adress of the register to be written in
ahambi 0:461186c994f0 88 DDS._spi.write(0x00 | (0x07 & 0x1F));
ahambi 0:461186c994f0 89 // byte 5: Ramp rate first part
ahambi 0:461186c994f0 90 DDS._spi.write(0xFF & RSCW);
ahambi 0:461186c994f0 91 // byte 4: Ramp rate second part
ahambi 0:461186c994f0 92 DDS._spi.write(0xFF & (RSCW >> 8));
ahambi 0:461186c994f0 93 // byte 3: final address <7:0>
ahambi 0:461186c994f0 94 DDS._spi.write(0xFF & r1);
ahambi 0:461186c994f0 95 // byte 2
ahambi 0:461186c994f0 96 DDS._spi.write(((r0 << 2) & 0xFC) | ((r1 >> 8) & 0x03));
ahambi 0:461186c994f0 97 // byte 1: beginning address <9:6>
ahambi 0:461186c994f0 98 DDS._spi.write(0x40 | (((r0 >> 6) & 0x0F)));
ahambi 0:461186c994f0 99 update = 1;
ahambi 0:461186c994f0 100 wait_us(10);//5*1/(12.0e6));
ahambi 0:461186c994f0 101 update =0;
ahambi 0:461186c994f0 102
ahambi 0:461186c994f0 103 i = 0;
ahambi 0:461186c994f0 104 while (i<=(R_used)) {
ahambi 0:461186c994f0 105 //FTWO[i] = FTWO_func(frequency[i]);
ahambi 0:461186c994f0 106 PHWO[R_used-i] = PHWO_func(f[i]);
ahambi 0:461186c994f0 107 //pc.printf("written %i %lf \r \n", i, f[i]);
ahambi 0:461186c994f0 108 i += 1;
ahambi 0:461186c994f0 109 }
ahambi 0:461186c994f0 110
ahambi 0:461186c994f0 111 pc.printf("RSCW0 written: %lf %lf \r\n", f[0], f[R_used]);
ahambi 0:461186c994f0 112
ahambi 0:461186c994f0 113 ps0 = 0;
ahambi 0:461186c994f0 114 ps1 = 0;
ahambi 0:461186c994f0 115
ahambi 0:461186c994f0 116 DDS._spi.write(0x0B);
ahambi 0:461186c994f0 117
ahambi 0:461186c994f0 118 i = 0;
ahambi 0:461186c994f0 119 while (i<=(R_used)) {
ahambi 0:461186c994f0 120 DDS.RAM_write_FTWO((PHWO[i] << 18) & 0xFFFFFFFF);
ahambi 0:461186c994f0 121 // pc.printf("calculated %d : %x, %f \n", i, FTWO[i], frequency[i]);
ahambi 0:461186c994f0 122 i += 1;
ahambi 0:461186c994f0 123 }
ahambi 0:461186c994f0 124 }
ahambi 1:163c47ba88bd 125
ahambi 1:163c47ba88bd 126 // ************* RSCW1 ******************
ahambi 0:461186c994f0 127 void writeRSCW1(int r0, int r1, uint32_t RSCW, double f[]) {
ahambi 0:461186c994f0 128 int R_used = r1-r0;
ahambi 0:461186c994f0 129 uint32_t FTWO[R_used];
ahambi 0:461186c994f0 130 ps0 = 1;
ahambi 0:461186c994f0 131 ps1 = 0;
ahambi 0:461186c994f0 132 update = 0;
ahambi 0:461186c994f0 133 // Instruction byte: page 25, we want to write (0), so 0100
ahambi 0:461186c994f0 134 // + internal adress of the register to be written in
ahambi 0:461186c994f0 135 DDS._spi.write(0x00 | (0x08 & 0x1F));
ahambi 0:461186c994f0 136 // byte 5: Ramp rate first part
ahambi 0:461186c994f0 137 DDS._spi.write(0xFF & RSCW);
ahambi 0:461186c994f0 138 // byte 4: Ramp rate second part
ahambi 0:461186c994f0 139 DDS._spi.write(0xFF & (RSCW >> 8));
ahambi 0:461186c994f0 140 // byte 3: final address <7:0>
ahambi 0:461186c994f0 141 DDS._spi.write(0xFF & r1);
ahambi 0:461186c994f0 142 // byte 2
ahambi 0:461186c994f0 143 DDS._spi.write(((r0 << 2) & 0xFC) | ((r1 >> 8) & 0x03));
ahambi 0:461186c994f0 144 // byte 1: beginning address <9:6>
ahambi 0:461186c994f0 145 DDS._spi.write(0x20 | (((r0 >> 6) & 0x0F)));
ahambi 0:461186c994f0 146 update = 1;
ahambi 0:461186c994f0 147 wait_us(10);//5*1/(12.0e6));
ahambi 0:461186c994f0 148 update =0;
ahambi 0:461186c994f0 149
ahambi 0:461186c994f0 150 i = 0;
ahambi 0:461186c994f0 151 while (i<=(R_used)) {
ahambi 0:461186c994f0 152 //FTWO[i] = FTWO_func(frequency[i]);
ahambi 0:461186c994f0 153 FTWO[R_used-i] = FTWO_func(f[i]);
ahambi 0:461186c994f0 154 //pc.printf("written %i %lf \r \n", i, f[i]);
ahambi 0:461186c994f0 155 i += 1;
ahambi 0:461186c994f0 156 }
ahambi 0:461186c994f0 157
ahambi 0:461186c994f0 158 pc.printf("RSCW1 written: %lf %lf \r\n", f[0], f[R_used]);
ahambi 0:461186c994f0 159
ahambi 0:461186c994f0 160 ps0 = 1;
ahambi 0:461186c994f0 161 ps1 = 0;
ahambi 0:461186c994f0 162
ahambi 0:461186c994f0 163 DDS._spi.write(0x0B);
ahambi 0:461186c994f0 164
ahambi 0:461186c994f0 165 i = 0;
ahambi 0:461186c994f0 166 while (i<=(R_used)) {
ahambi 0:461186c994f0 167 DDS.RAM_write_FTWO(FTWO[i]);
ahambi 0:461186c994f0 168 // pc.printf("calculated %d : %x, %f \n", i, FTWO[i], frequency[i]);
ahambi 0:461186c994f0 169 i += 1;
ahambi 0:461186c994f0 170 }
ahambi 0:461186c994f0 171 }
ahambi 1:163c47ba88bd 172
ahambi 1:163c47ba88bd 173 // ************* RSCW2 ******************
ahambi 0:461186c994f0 174 void writeRSCW2(int r0, int r1, uint32_t RSCW, double f[]) {
ahambi 0:461186c994f0 175 int R_used = r1-r0;
ahambi 0:461186c994f0 176 uint32_t FTWO[R_used];
ahambi 0:461186c994f0 177 ps0 = 0;
ahambi 0:461186c994f0 178 ps1 = 1;
ahambi 0:461186c994f0 179 update = 0;
ahambi 0:461186c994f0 180 // Instruction byte: page 25, we want to write (0), so 0100
ahambi 0:461186c994f0 181 // + internal adress of the register to be written in
ahambi 0:461186c994f0 182 DDS._spi.write(0x00 | (0x09 & 0x1F));
ahambi 0:461186c994f0 183 // byte 5: Ramp rate first part
ahambi 0:461186c994f0 184 DDS._spi.write(0xFF & RSCW);
ahambi 0:461186c994f0 185 // byte 4: Ramp rate second part
ahambi 0:461186c994f0 186 DDS._spi.write(0xFF & (RSCW >> 8));
ahambi 0:461186c994f0 187 // byte 3: final address <7:0>
ahambi 0:461186c994f0 188 DDS._spi.write(0xFF & r1);
ahambi 0:461186c994f0 189 // byte 2
ahambi 0:461186c994f0 190 DDS._spi.write(((r0 << 2) & 0xFC) | ((r1 >> 8) & 0x03));
ahambi 0:461186c994f0 191 // byte 1: beginning address <9:6>
ahambi 0:461186c994f0 192 DDS._spi.write(0x20 | (((r0 >> 6) & 0x0F)));
ahambi 0:461186c994f0 193 update = 1;
ahambi 0:461186c994f0 194 wait_us(10);//5*1/(12.0e6));
ahambi 0:461186c994f0 195 update =0;
ahambi 0:461186c994f0 196
ahambi 0:461186c994f0 197 i = 0;
ahambi 0:461186c994f0 198 while (i<=(R_used)) {
ahambi 0:461186c994f0 199 //FTWO[i] = FTWO_func(frequency[i]);
ahambi 0:461186c994f0 200 FTWO[R_used-i] = FTWO_func(f[i]);
ahambi 0:461186c994f0 201 //pc.printf("written %i %lf \r \n", i, f[i]);
ahambi 0:461186c994f0 202 i += 1;
ahambi 0:461186c994f0 203 }
ahambi 0:461186c994f0 204
ahambi 0:461186c994f0 205 pc.printf("RSCW0 written: %lf %lf \r\n", f[0], f[R_used]);
ahambi 0:461186c994f0 206
ahambi 0:461186c994f0 207 ps0 = 0;
ahambi 0:461186c994f0 208 ps1 = 1;
ahambi 0:461186c994f0 209
ahambi 0:461186c994f0 210 DDS._spi.write(0x0B);
ahambi 0:461186c994f0 211
ahambi 0:461186c994f0 212 i = 0;
ahambi 0:461186c994f0 213 while (i<=(R_used)) {
ahambi 0:461186c994f0 214 DDS.RAM_write_FTWO(FTWO[i]);
ahambi 0:461186c994f0 215 // pc.printf("calculated %d : %x, %f \n", i, FTWO[i], frequency[i]);
ahambi 0:461186c994f0 216 i += 1;
ahambi 0:461186c994f0 217 }
ahambi 0:461186c994f0 218 }
ahambi 0:461186c994f0 219
ahambi 1:163c47ba88bd 220 // ************* RSCW3 ******************
ahambi 0:461186c994f0 221 void writeRSCW3(int r0, int r1, uint32_t RSCW, double f[]) {
ahambi 0:461186c994f0 222 int R_used = r1-r0;
ahambi 0:461186c994f0 223 uint32_t FTWO[R_used];
ahambi 0:461186c994f0 224 ps0 = 1;
ahambi 0:461186c994f0 225 ps1 = 1;
ahambi 0:461186c994f0 226 update = 0;
ahambi 0:461186c994f0 227 // Instruction byte: page 25, we want to write (0), so 0100
ahambi 0:461186c994f0 228 // + internal adress of the register to be written in
ahambi 0:461186c994f0 229 DDS._spi.write(0x00 | (0x10 & 0x1F));
ahambi 0:461186c994f0 230 // byte 5: Ramp rate first part
ahambi 0:461186c994f0 231 DDS._spi.write(0xFF & RSCW);
ahambi 0:461186c994f0 232 // byte 4: Ramp rate second part
ahambi 0:461186c994f0 233 DDS._spi.write(0xFF & (RSCW >> 8));
ahambi 0:461186c994f0 234 // byte 3: final address <7:0>
ahambi 0:461186c994f0 235 DDS._spi.write(0xFF & r1);
ahambi 0:461186c994f0 236 // byte 2
ahambi 0:461186c994f0 237 DDS._spi.write(((r0 << 2) & 0xFC) | ((r1 >> 8) & 0x03));
ahambi 0:461186c994f0 238 // byte 1: beginning address <9:6>
ahambi 0:461186c994f0 239 DDS._spi.write(0x20 | (((r0 >> 6) & 0x0F)));
ahambi 0:461186c994f0 240 update = 1;
ahambi 0:461186c994f0 241 wait_us(10);//5*1/(12.0e6));
ahambi 0:461186c994f0 242 update =0;
ahambi 0:461186c994f0 243
ahambi 0:461186c994f0 244 i = 0;
ahambi 0:461186c994f0 245 while (i<=(R_used)) {
ahambi 0:461186c994f0 246 //FTWO[i] = FTWO_func(frequency[i]);
ahambi 0:461186c994f0 247 FTWO[R_used-i] = FTWO_func(f[i]);
ahambi 0:461186c994f0 248 //pc.printf("written %i %lf \r \n", i, f[i]);
ahambi 0:461186c994f0 249 i += 1;
ahambi 0:461186c994f0 250 }
ahambi 0:461186c994f0 251
ahambi 0:461186c994f0 252 pc.printf("RSCW0 written: %lf %lf \r\n", f[0], f[R_used]);
ahambi 0:461186c994f0 253
ahambi 0:461186c994f0 254 ps0 = 1;
ahambi 0:461186c994f0 255 ps1 = 1;
ahambi 0:461186c994f0 256
ahambi 0:461186c994f0 257 DDS._spi.write(0x0B);
ahambi 0:461186c994f0 258
ahambi 0:461186c994f0 259 i = 0;
ahambi 0:461186c994f0 260 while (i<=(R_used)) {
ahambi 0:461186c994f0 261 DDS.RAM_write_FTWO(FTWO[i]);
ahambi 0:461186c994f0 262 // pc.printf("calculated %d : %x, %f \n", i, FTWO[i], frequency[i]);
ahambi 0:461186c994f0 263 i += 1;
ahambi 0:461186c994f0 264 }
ahambi 0:461186c994f0 265 }
ahambi 0:461186c994f0 266
ahambi 1:163c47ba88bd 267 // Function to calculate the RSCW-word used in RSCW1, RSCW2, RSCW3 and RSCW4
ahambi 0:461186c994f0 268 uint64_t RSCW_func(int ram0, int ram1, double trise) {
ahambi 0:461186c994f0 269 int RAM_used = ram1-ram0+1;
ahambi 0:461186c994f0 270 double tmin = 1.0*4.0/ref_clock*RAM_used; // minimum 1 dwell of time 4/clock at each address
ahambi 0:461186c994f0 271 double tmax = 65535.0*4.0/ref_clock*RAM_used; // 16 bit register corresponding to 65535 dwells
ahambi 0:461186c994f0 272 if (trise < tmin) { pc.printf("ERROR: ramp time too small. Minimum: %f \r \n", tmin); };
ahambi 0:461186c994f0 273 if (trise > tmax) { pc.printf("ERROR: ramp time too large. Maximum: %f \r \n", tmax); };
ahambi 0:461186c994f0 274 int dwells = round(trise/(4.0/ref_clock*RAM_used));
ahambi 0:461186c994f0 275 pc.printf(" %i dwells at each address ---> %f ramp time. \r \n", dwells, dwells*RAM_used*4.0/ref_clock);
ahambi 0:461186c994f0 276 return 0xFFFF & dwells;
ahambi 0:461186c994f0 277 }
ahambi 0:461186c994f0 278
ahambi 0:461186c994f0 279 int counter(double t) {// for t in us
ahambi 0:461186c994f0 280 int bins = int((t-91.8160e-9)/(41.6664e-9) + 0.5);
ahambi 0:461186c994f0 281 //pc.printf("bins = %i", bins);
ahambi 0:461186c994f0 282 return bins;
ahambi 0:461186c994f0 283 };
ahambi 1:163c47ba88bd 284
ahambi 1:163c47ba88bd 285 // The wait-function doesn't offer time resolution of mikroseconds. By using a process like
ahambi 1:163c47ba88bd 286 // counting up an integer number and measuring the time the mbed needs for this process a time
ahambi 1:163c47ba88bd 287 // resolution of some tens of nano-seconds can be reached. "counter()" is used in "start_ramp()"
ahambi 1:163c47ba88bd 288 // below:
ahambi 0:461186c994f0 289 int start_ramp(double trise, double tstay) {
ahambi 0:461186c994f0 290 int i = 0;
ahambi 0:461186c994f0 291 int count = counter(trise+tstay);
ahambi 0:461186c994f0 292 ps0 = 1;
ahambi 0:461186c994f0 293 ps1 = 0;
ahambi 0:461186c994f0 294 //-----------------------------
ahambi 0:461186c994f0 295 // NEVER EVER change this loop!
ahambi 0:461186c994f0 296 trigger = 0;
ahambi 0:461186c994f0 297 trigger = 1;
ahambi 0:461186c994f0 298 while(i<count){
ahambi 0:461186c994f0 299 i += 1;
ahambi 0:461186c994f0 300 }
ahambi 0:461186c994f0 301 trigger = 0;
ahambi 0:461186c994f0 302 //-----------------------------
ahambi 0:461186c994f0 303 ps0 = 0;
ahambi 0:461186c994f0 304 ps1 = 0;
ahambi 0:461186c994f0 305 i = 0;
ahambi 1:163c47ba88bd 306 while(i<count){
ahambi 1:163c47ba88bd 307 i += 1;
ahambi 1:163c47ba88bd 308 }
ahambi 0:461186c994f0 309 return 0;
ahambi 0:461186c994f0 310 };
ahambi 1:163c47ba88bd 311
ahambi 1:163c47ba88bd 312 // Functions used to select output channel 1 or 2:
ahambi 0:461186c994f0 313 void check_up(){
ahambi 0:461186c994f0 314 ps0 = 0;
ahambi 0:461186c994f0 315 ps1 = 0;
ahambi 0:461186c994f0 316 ch_1(); DDS.CFR1_write(0x00000200);
ahambi 0:461186c994f0 317 ch_2(); DDS.CFR1_write(0xC0000200);
ahambi 0:461186c994f0 318 };
ahambi 0:461186c994f0 319
ahambi 0:461186c994f0 320 void check_down() {
ahambi 0:461186c994f0 321 ps0 = 0;
ahambi 0:461186c994f0 322 ps1 = 0;
ahambi 0:461186c994f0 323 ch_2(); DDS.CFR1_write(0x00000200);
ahambi 0:461186c994f0 324 ch_1(); DDS.CFR1_write(0xC0000200);
ahambi 0:461186c994f0 325 };
ahambi 0:461186c994f0 326
ahambi 0:461186c994f0 327 void slow_ramp_360() {
ahambi 0:461186c994f0 328 pc.printf("entered r -> starting slow phase ramp 0-->360 degree \r \n");
ahambi 0:461186c994f0 329 int i;
ahambi 0:461186c994f0 330 int steps = 700;
ahambi 0:461186c994f0 331 double phase0 = 0;
ahambi 0:461186c994f0 332 double phase1 = 359;
ahambi 0:461186c994f0 333 double phase_array[steps+1];
ahambi 0:461186c994f0 334 uint32_t PHWO [steps+1];
ahambi 0:461186c994f0 335 i = 0;
ahambi 0:461186c994f0 336 while(i<=steps) {
ahambi 0:461186c994f0 337 phase_array[i] = phase0 + (phase1-phase0)/steps*i;
ahambi 0:461186c994f0 338 // pc.printf("phase value: %lf", phase_array[i]);
ahambi 0:461186c994f0 339 PHWO[i]=rint(phase_array[i]/360.0*pow(2.0,14.0));
ahambi 0:461186c994f0 340 i += 1;
ahambi 0:461186c994f0 341 }
ahambi 0:461186c994f0 342 // * The Ramp * //
ahambi 0:461186c994f0 343 while(1) {
ahambi 0:461186c994f0 344 DDS.PHWO_write(PHWO[0]);
ahambi 0:461186c994f0 345 trigger = 0;
ahambi 0:461186c994f0 346 wait(1e-3);
ahambi 0:461186c994f0 347 i = 0;
ahambi 0:461186c994f0 348 trigger = 1;
ahambi 0:461186c994f0 349 while(i<=steps) {
ahambi 0:461186c994f0 350 DDS.PHWO_write(PHWO[i]);
ahambi 0:461186c994f0 351 //if (i==0) {trigger = 1;};
ahambi 0:461186c994f0 352 i+=1;
ahambi 0:461186c994f0 353 }
ahambi 0:461186c994f0 354 trigger = 0;
ahambi 0:461186c994f0 355 wait(10e-3);
ahambi 0:461186c994f0 356 DDS.PHWO_write(PHWO[0]);
ahambi 0:461186c994f0 357 if (pc.readable()) break;
ahambi 0:461186c994f0 358 }
ahambi 0:461186c994f0 359 //
ahambi 0:461186c994f0 360 };
ahambi 0:461186c994f0 361
ahambi 1:163c47ba88bd 362 void initialize(double phase1, double trise_00) {
ahambi 0:461186c994f0 363 double tstay = 500.0e-6;
ahambi 0:461186c994f0 364
ahambi 0:461186c994f0 365 // intermediate frequencies
ahambi 1:163c47ba88bd 366 double phase0 = 0;
ahambi 1:163c47ba88bd 367 //double phase1 = 20;
ahambi 0:461186c994f0 368 // tuning word RSCW0 variables
ahambi 1:163c47ba88bd 369 //double trise_00 = 100e-6;//0.1e-6;//20.0e-6;
ahambi 0:461186c994f0 370 int ram0_00 = 50;
ahambi 0:461186c994f0 371 int ram1_00 = 100;
ahambi 0:461186c994f0 372 const int RAM_used_00 = ram1_00 - ram0_00;
ahambi 0:461186c994f0 373 double p00 [RAM_used_00+1];
ahambi 0:461186c994f0 374 double frequency_init [1];
ahambi 0:461186c994f0 375 double frequency0 = 80.0e6;
ahambi 0:461186c994f0 376 frequency_init[0] = frequency0;
ahambi 0:461186c994f0 377
ahambi 0:461186c994f0 378 j = 0;
ahambi 0:461186c994f0 379 while (j<=(RAM_used_00)) {
ahambi 0:461186c994f0 380 p00[j] = phase0 + (phase1-phase0)/trise_00*j*trise_00/RAM_used_00;
ahambi 0:461186c994f0 381 j += 1;
ahambi 0:461186c994f0 382 }
ahambi 0:461186c994f0 383
ahambi 0:461186c994f0 384 // ### calculation of RSCW-words ###
ahambi 0:461186c994f0 385 uint64_t RSCW0 = RSCW_func(ram0_00, ram1_00, trise_00);
ahambi 0:461186c994f0 386
ahambi 0:461186c994f0 387 // ### initialize both channels on the first intermediate frequency and write into their RAM
ahambi 0:461186c994f0 388
ahambi 0:461186c994f0 389 ch_1();
ahambi 0:461186c994f0 390
ahambi 0:461186c994f0 391 DDS.CFR1_write(0x00000200);
ahambi 0:461186c994f0 392 DDS.FTW0_write(FTWO_func(frequency0));
ahambi 0:461186c994f0 393 writeRSCW0(ram0_00, ram1_00, RSCW0, p00);
ahambi 0:461186c994f0 394
ahambi 0:461186c994f0 395 ch_2();
ahambi 0:461186c994f0 396
ahambi 0:461186c994f0 397 DDS.CFR1_write(0x00000200);
ahambi 0:461186c994f0 398 DDS.FTW0_write(FTWO_func(frequency0));
ahambi 0:461186c994f0 399 writeRSCW0(ram0_00, ram1_00, RSCW0, p00);
ahambi 1:163c47ba88bd 400 }
ahambi 1:163c47ba88bd 401
ahambi 1:163c47ba88bd 402 // ############################################################
ahambi 1:163c47ba88bd 403 // ##################### main part ############################
ahambi 1:163c47ba88bd 404
ahambi 1:163c47ba88bd 405 int main() {
ahambi 1:163c47ba88bd 406
ahambi 1:163c47ba88bd 407 pc.printf(" \r \r \n \n ***** Phase ramp with DDS in RAM mode***** \r \r \n \n");
ahambi 1:163c47ba88bd 408 pc.printf("Enter: \r\n");
ahambi 1:163c47ba88bd 409 pc.printf("'1' or '2' --> which output channel should be phase ramped. (Can be chosen over the mbed pin 'mcs' as well.) \r \n ");
ahambi 1:163c47ba88bd 410 pc.printf("'r' --> start a slow phase ramp from 0 to 359 degree in milliseconds. Trigger on mbed pin 13. Repetition rate of the ramp approx. 1 kHz. \r \n");
ahambi 1:163c47ba88bd 411 pc.printf("'a' --> starts the RAM phase ramp with rise time 'trise' and repeats the phase ramp until another key is pressed. \r \n ");
ahambi 1:163c47ba88bd 412 pc.printf("'t' --> change the parameter 'trise', i.e. the rise time to reach the final phase value (100 us initially) \r \n");
ahambi 1:163c47ba88bd 413 pc.printf("'p' --> final phase difference between the output channels (20 degree initially) \r \n");
ahambi 1:163c47ba88bd 414
ahambi 1:163c47ba88bd 415
ahambi 1:163c47ba88bd 416 reset();
ahambi 1:163c47ba88bd 417
ahambi 1:163c47ba88bd 418 double tstay = 10e-6;
ahambi 1:163c47ba88bd 419 double trise = 100e-6;
ahambi 1:163c47ba88bd 420 double phase1 = 20.0;
ahambi 1:163c47ba88bd 421
ahambi 1:163c47ba88bd 422 initialize(phase1, trise);
ahambi 0:461186c994f0 423 char up_or_down = '0';
ahambi 0:461186c994f0 424
ahambi 0:461186c994f0 425 while(1) {
ahambi 0:461186c994f0 426 if(pc.readable()) {
ahambi 0:461186c994f0 427 up_or_down = pc.getc();
ahambi 1:163c47ba88bd 428 if (up_or_down == 't') {
ahambi 1:163c47ba88bd 429 // Get out of RAM mode
ahambi 1:163c47ba88bd 430 ps0 = 0;
ahambi 1:163c47ba88bd 431 ps1 = 1;
ahambi 1:163c47ba88bd 432 ch_2(); DDS.CFR1_write(0x00000200);
ahambi 1:163c47ba88bd 433 ch_1(); DDS.CFR1_write(0x00000200);
ahambi 1:163c47ba88bd 434 // Get new time value
ahambi 1:163c47ba88bd 435 pc.printf("enter new trise value in us: \n");
ahambi 0:461186c994f0 436 pc.scanf("%lf", &trise);
ahambi 0:461186c994f0 437 trise = trise*1.0e-6;
ahambi 1:163c47ba88bd 438 // Initialize again
ahambi 1:163c47ba88bd 439 initialize(phase1, trise);
ahambi 1:163c47ba88bd 440 }
ahambi 1:163c47ba88bd 441 if (up_or_down == 'p') {
ahambi 1:163c47ba88bd 442 // Get out of RAM mode
ahambi 1:163c47ba88bd 443 ps0 = 0;
ahambi 1:163c47ba88bd 444 ps1 = 1;
ahambi 1:163c47ba88bd 445 ch_2(); DDS.CFR1_write(0x00000200);
ahambi 1:163c47ba88bd 446 ch_1(); DDS.CFR1_write(0x00000200);
ahambi 1:163c47ba88bd 447 // Get new time value
ahambi 1:163c47ba88bd 448 pc.printf("enter final phase value in degree: \n");
ahambi 1:163c47ba88bd 449 pc.scanf("%lf", &phase1);
ahambi 1:163c47ba88bd 450 // Initialize again
ahambi 1:163c47ba88bd 451 initialize(phase1, trise);
ahambi 0:461186c994f0 452 }
ahambi 0:461186c994f0 453 if (up_or_down == 'u') {
ahambi 0:461186c994f0 454 pc.printf("u");
ahambi 0:461186c994f0 455 trigger = 1;
ahambi 0:461186c994f0 456 wait(trise/4.0);
ahambi 0:461186c994f0 457 trigger = 0;
ahambi 0:461186c994f0 458 /////
ahambi 0:461186c994f0 459 ps0 = 1;
ahambi 0:461186c994f0 460 ps1 = 0;
ahambi 0:461186c994f0 461 /////
ahambi 0:461186c994f0 462 }
ahambi 0:461186c994f0 463 if (up_or_down == 'd') {
ahambi 0:461186c994f0 464 pc.printf("d");
ahambi 0:461186c994f0 465 trigger = 1;
ahambi 0:461186c994f0 466 wait(trise/4.0);
ahambi 0:461186c994f0 467 trigger = 0;
ahambi 0:461186c994f0 468 /////
ahambi 0:461186c994f0 469 ps0 = 0;
ahambi 0:461186c994f0 470 ps1 = 0;
ahambi 0:461186c994f0 471 /////
ahambi 0:461186c994f0 472 }
ahambi 0:461186c994f0 473 if (up_or_down == '1') {
ahambi 0:461186c994f0 474 trigger = 0;
ahambi 0:461186c994f0 475 trigger = 1;
ahambi 0:461186c994f0 476 /*ps0 = 0;
ahambi 0:461186c994f0 477 ch_2(); DDS.CFR1_write(0x00000200);
ahambi 0:461186c994f0 478 ch_1(); DDS.CFR1_write(0x80000200);*/
ahambi 0:461186c994f0 479 check_down();
ahambi 0:461186c994f0 480 trigger = 0;
ahambi 0:461186c994f0 481 pc.printf("ramping channel 1 \r\n");
ahambi 0:461186c994f0 482 }
ahambi 0:461186c994f0 483 if (up_or_down == '2') {
ahambi 0:461186c994f0 484 trigger = 0;
ahambi 0:461186c994f0 485 trigger = 1;
ahambi 0:461186c994f0 486 /*ps0 = 0;
ahambi 0:461186c994f0 487 ch_1(); DDS.CFR1_write(0x00000200);
ahambi 0:461186c994f0 488 ch_2(); DDS.CFR1_write(0x80000200);*/
ahambi 0:461186c994f0 489 check_up();
ahambi 0:461186c994f0 490 trigger = 0;
ahambi 0:461186c994f0 491 pc.printf("ramping channel 2 \r\n");
ahambi 0:461186c994f0 492 }
ahambi 0:461186c994f0 493 if (up_or_down == '0') {
ahambi 0:461186c994f0 494 ps0 = 0;
ahambi 0:461186c994f0 495 ps1 = 1;
ahambi 0:461186c994f0 496 ch_2(); DDS.CFR1_write(0x00000200);
ahambi 0:461186c994f0 497 ch_1(); DDS.CFR1_write(0x00000200);
ahambi 0:461186c994f0 498 }
ahambi 0:461186c994f0 499 if (up_or_down == 'r') {
ahambi 0:461186c994f0 500 slow_ramp_360();
ahambi 0:461186c994f0 501 }
ahambi 1:163c47ba88bd 502 if (up_or_down == 'a') {
ahambi 1:163c47ba88bd 503 while(1) {
ahambi 1:163c47ba88bd 504 /*
ahambi 1:163c47ba88bd 505 trigger = 0;
ahambi 1:163c47ba88bd 506 trigger = 1;
ahambi 1:163c47ba88bd 507 ps0 = 1;
ahambi 1:163c47ba88bd 508 wait(4*trise);
ahambi 1:163c47ba88bd 509 ps0 = 0;
ahambi 1:163c47ba88bd 510 trigger = 0;
ahambi 1:163c47ba88bd 511 wait(4*trise);
ahambi 1:163c47ba88bd 512 */
ahambi 1:163c47ba88bd 513 start_ramp(trise, 10*trise);
ahambi 1:163c47ba88bd 514 if (pc.readable()) break;
ahambi 1:163c47ba88bd 515 }
ahambi 1:163c47ba88bd 516 }
ahambi 0:461186c994f0 517 }
ahambi 1:163c47ba88bd 518 // Select the ramping channel with the mbed - mcs pin:
ahambi 0:461186c994f0 519 mcs.rise(&check_up);
ahambi 0:461186c994f0 520 mcs.fall(&check_down);
ahambi 1:163c47ba88bd 521 /*
ahambi 0:461186c994f0 522 if(mexp) {
ahambi 0:461186c994f0 523 while(mexp);
ahambi 0:461186c994f0 524 start_ramp(trise, tstay);
ahambi 0:461186c994f0 525 // pc.printf(" exp trigger in registered \r \n");
ahambi 1:163c47ba88bd 526 }*/
ahambi 0:461186c994f0 527 }
ahambi 0:461186c994f0 528
ahambi 0:461186c994f0 529 return 0;
ahambi 0:461186c994f0 530 }
ahambi 0:461186c994f0 531
ahambi 0:461186c994f0 532