a hambi / Mbed 2 deprecated Phase_Ramp_from_DDS_for_CQED

With the DDS RAM registers a desired function "phase (time)" can be implemented for one of the output channels and triggered either by the serial terminal or by an external signal on one of the mbed pins.

Dependencies:   mbed

DDS.h@1:163c47ba88bd, 2012-11-09 (annotated)

Committer:
ahambi
Date:
Fri Nov 09 16:27:38 2012 +0000
Revision:
1:163c47ba88bd
Parent:
0:461186c994f0 
With the DDS RAM registers a desired function "phase (time)" can be implemented for one of the output channels and triggered either by the serial terminal or by an external signal on one of the mbed pins.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ahambi 0:461186c994f0 1 #ifndef DDS_H
ahambi 0:461186c994f0 2 #define DDS_H
ahambi 0:461186c994f0 3
ahambi 0:461186c994f0 4 #include "mbed.h"
ahambi 0:461186c994f0 5
ahambi 0:461186c994f0 6 class DDS {
ahambi 0:461186c994f0 7
ahambi 0:461186c994f0 8 public:
ahambi 0:461186c994f0 9 SPI _spi;
ahambi 0:461186c994f0 10 DigitalOut _cs;
ahambi 0:461186c994f0 11 DigitalOut _rst;
ahambi 0:461186c994f0 12 DigitalOut update;
ahambi 0:461186c994f0 13
ahambi 0:461186c994f0 14 DDS(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName update) :
ahambi 0:461186c994f0 15 _spi(mosi, miso, sclk), _cs(cs), _rst(rst), update(update)
ahambi 0:461186c994f0 16 {
ahambi 0:461186c994f0 17 // see http://mbed.org/handbook/SPI and page 23 [manual] why format 0
ahambi 0:461186c994f0 18 _spi.format(8, 0);
ahambi 0:461186c994f0 19 _spi.frequency(12e6); // system clock: 1 MHz or 1 us
ahambi 0:461186c994f0 20 };
ahambi 0:461186c994f0 21
ahambi 0:461186c994f0 22 // ------------------------------------------------------------
ahambi 0:461186c994f0 23
ahambi 0:461186c994f0 24 // *** write and read functions ***
ahambi 0:461186c994f0 25
ahambi 0:461186c994f0 26 // writing to "n_byte" register, with address "address" the value "value"
ahambi 0:461186c994f0 27 void write(int n_byte, uint32_t address, uint64_t value) {
ahambi 0:461186c994f0 28 update = 0;
ahambi 0:461186c994f0 29 // Instruction byte: (page 25 [manual]) write (0) + internal adress of the register to be written in
ahambi 0:461186c994f0 30 _spi.write(0x00 | (address & 0x1F));
ahambi 0:461186c994f0 31 while(n_byte>0) {
ahambi 0:461186c994f0 32 n_byte = n_byte - 1;
ahambi 0:461186c994f0 33 _spi.write((value >> 8*n_byte) & 0xFF);
ahambi 0:461186c994f0 34 }
ahambi 0:461186c994f0 35 update = 1;
ahambi 0:461186c994f0 36 wait(5*1/(12.0e6));
ahambi 0:461186c994f0 37 update =0;
ahambi 0:461186c994f0 38 }
ahambi 0:461186c994f0 39
ahambi 0:461186c994f0 40 void ram_write(int n_byte, uint32_t value) {
ahambi 0:461186c994f0 41 while(n_byte>0) {
ahambi 0:461186c994f0 42 n_byte = n_byte - 1;
ahambi 0:461186c994f0 43 _spi.write((value >> 8*n_byte) & 0xFF);
ahambi 0:461186c994f0 44 }
ahambi 0:461186c994f0 45 }
ahambi 0:461186c994f0 46
ahambi 0:461186c994f0 47 /*
ahambi 0:461186c994f0 48 void RAM_enable() {
ahambi 0:461186c994f0 49 int n_byte = 4;
ahambi 0:461186c994f0 50 uint32_t value = 0x80000200;
ahambi 0:461186c994f0 51 _ps0 = 0;
ahambi 0:461186c994f0 52 _spi.write(0x00 | (0x00 & 0x1F));
ahambi 0:461186c994f0 53 while(n_byte>0) {
ahambi 0:461186c994f0 54 n_byte = n_byte - 1;
ahambi 0:461186c994f0 55 _spi.write((value >> 8*n_byte) & 0xFF);
ahambi 0:461186c994f0 56 }
ahambi 0:461186c994f0 57 _ps0 = 1;
ahambi 0:461186c994f0 58 }*/
ahambi 0:461186c994f0 59
ahambi 0:461186c994f0 60 // Write functions
ahambi 0:461186c994f0 61 void PLSCW_write(uint64_t reg) { write(5, 0x08, reg); }
ahambi 0:461186c994f0 62 void NLSCW_write(uint64_t reg) { write(5, 0x07, reg); }
ahambi 0:461186c994f0 63 // void RSCW0_write(uint64_t reg) { write(5, 0x07, reg); }
ahambi 0:461186c994f0 64 void CFR1_write(uint32_t reg) { write(4, 0x00, reg); }
ahambi 0:461186c994f0 65 void RAM_write_FTWO(uint32_t reg) { ram_write(4, reg); }
ahambi 0:461186c994f0 66 void RAM_write_PHWO(uint32_t reg) { ram_write(2, reg); }
ahambi 0:461186c994f0 67 void FTW0_write(uint32_t reg) { write(4, 0x04, reg); }
ahambi 0:461186c994f0 68 void FTW1_write(uint32_t reg) { write(4, 0x06, reg); }
ahambi 0:461186c994f0 69 void CFR2_write(uint32_t reg) { write(3, 0x01, reg); }
ahambi 0:461186c994f0 70 void PHWO_write(uint32_t reg) { write(2, 0x05, reg); }
ahambi 0:461186c994f0 71 void ASF_write(uint32_t reg) { write(2, 0x02, reg); }
ahambi 0:461186c994f0 72 void ARR_write(uint32_t reg) { write(1, 0x03, reg); }
ahambi 0:461186c994f0 73
ahambi 0:461186c994f0 74
ahambi 0:461186c994f0 75 // ------------------------------------------------------------
ahambi 0:461186c994f0 76
ahambi 0:461186c994f0 77 // Read 5 byte
ahambi 0:461186c994f0 78 uint64_t read_reg_5byte(uint32_t address) {
ahambi 0:461186c994f0 79 uint64_t value;
ahambi 0:461186c994f0 80 _spi.write(0x80 | (address & 0x0F)); // Instruction byte
ahambi 0:461186c994f0 81 value |= _spi.write(0x00);
ahambi 0:461186c994f0 82 value = value << 8;
ahambi 0:461186c994f0 83 value |= _spi.write(0x00);
ahambi 0:461186c994f0 84 value = value << 8;
ahambi 0:461186c994f0 85 value |= _spi.write(0x00);
ahambi 0:461186c994f0 86 value = value << 8;
ahambi 0:461186c994f0 87 value |= _spi.write(0x00);
ahambi 0:461186c994f0 88 value = value << 8;
ahambi 0:461186c994f0 89 value |= _spi.write(0x00);
ahambi 0:461186c994f0 90 return value;
ahambi 0:461186c994f0 91 }
ahambi 0:461186c994f0 92
ahambi 0:461186c994f0 93 // Read 4 byte.
ahambi 0:461186c994f0 94 uint32_t read_reg_4byte(uint32_t address) {
ahambi 0:461186c994f0 95 uint32_t value = 0x00000000;
ahambi 0:461186c994f0 96 _spi.write(0x80 | (address & 0x0F)); // Instruction byte
ahambi 0:461186c994f0 97 value |= _spi.write(0x00);
ahambi 0:461186c994f0 98 value = value << 8;
ahambi 0:461186c994f0 99 value |= _spi.write(0x00);
ahambi 0:461186c994f0 100 value = value << 8;
ahambi 0:461186c994f0 101 value |= _spi.write(0x00);
ahambi 0:461186c994f0 102 value = value << 8;
ahambi 0:461186c994f0 103 value |= _spi.write(0x00);
ahambi 0:461186c994f0 104 return value;
ahambi 0:461186c994f0 105 }
ahambi 0:461186c994f0 106
ahambi 0:461186c994f0 107 // Read 3 byte
ahambi 0:461186c994f0 108 uint32_t read_reg_3byte(uint32_t address) {
ahambi 0:461186c994f0 109 uint32_t value = 0x000000;
ahambi 0:461186c994f0 110 _spi.write(0x80 | (address & 0x0F)); // Instruction byte
ahambi 0:461186c994f0 111 value |= _spi.write(0x00);
ahambi 0:461186c994f0 112 value = value << 8;
ahambi 0:461186c994f0 113 value |= _spi.write(0x00);
ahambi 0:461186c994f0 114 value = value << 8;
ahambi 0:461186c994f0 115 value |= _spi.write(0x00);
ahambi 0:461186c994f0 116 return value;
ahambi 0:461186c994f0 117 }
ahambi 0:461186c994f0 118
ahambi 0:461186c994f0 119 // Read 2 byte
ahambi 0:461186c994f0 120 uint32_t read_reg_2byte(uint32_t address) {
ahambi 0:461186c994f0 121 uint32_t value = 0x000000;
ahambi 0:461186c994f0 122 _spi.write(0x80 | (address & 0x0F)); // Instruction byte
ahambi 0:461186c994f0 123 value |= _spi.write(0x00);
ahambi 0:461186c994f0 124 value = value << 8;
ahambi 0:461186c994f0 125 value |= _spi.write(0x00);
ahambi 0:461186c994f0 126 return value;
ahambi 0:461186c994f0 127 }
ahambi 0:461186c994f0 128
ahambi 0:461186c994f0 129 // Read 1 byte
ahambi 0:461186c994f0 130 uint32_t read_reg_1byte(uint32_t address) {
ahambi 0:461186c994f0 131 uint32_t value = 0x00;
ahambi 0:461186c994f0 132 _spi.write(0x80 | (address & 0x0F)); // Instruction byte
ahambi 0:461186c994f0 133 value |= _spi.write(0x00);
ahambi 0:461186c994f0 134 return value;
ahambi 0:461186c994f0 135 }
ahambi 0:461186c994f0 136
ahambi 0:461186c994f0 137
ahambi 0:461186c994f0 138 // Read functions
ahambi 0:461186c994f0 139 uint64_t RSCW0_read(void) { return read_reg_5byte(0x07); }
ahambi 0:461186c994f0 140 uint64_t PLSCW_read(void) { return read_reg_5byte(0x08); }
ahambi 0:461186c994f0 141 uint64_t NLSCW_read(void) { return read_reg_5byte(0x07); }
ahambi 0:461186c994f0 142 uint32_t CFR1_read(void) { return read_reg_4byte(0x00); }
ahambi 0:461186c994f0 143 uint32_t FTWO_read(void) { return read_reg_4byte(0x04); }
ahambi 0:461186c994f0 144 uint32_t CFR2_read(void) { return read_reg_3byte(0x01); }
ahambi 0:461186c994f0 145 uint32_t PHWO_read(void) { return read_reg_2byte(0x05); }
ahambi 0:461186c994f0 146 };
ahambi 0:461186c994f0 147
ahambi 0:461186c994f0 148 #endif