Aditya Mehrotra / SPINE_FIDDY_TEST

test code for SPI communications with any board

Dependencies:   mbed-dev

main.cpp@16:8f8adc5f8f0a, 2022-01-31 (annotated)

Committer:
adimmit
Date:
Mon Jan 31 21:44:38 2022 +0000
Revision:
16:8f8adc5f8f0a
Parent:
15:d3c93f01a02b
Child:
17:f200f87b4087
we learned C today ;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
adimmit 0:76c761d3caf1 1
adimmit 15:d3c93f01a02b 2
adimmit 0:76c761d3caf1 3 //GO THROUGH AND RE-CHECK ALL THE VARIABLES, STRUCT NAMES, SIZES, BUFFERS + ETC!!!
adimmit 0:76c761d3caf1 4 //ALSO GO THROUGH THE COMMENTS TO SEE IF THEY NEED CHANGING
adimmit 0:76c761d3caf1 5
adimmit 0:76c761d3caf1 6 #include "mbed.h"
adimmit 0:76c761d3caf1 7 #include "math_ops.h"
adimmit 0:76c761d3caf1 8 #include <cstring>
adimmit 0:76c761d3caf1 9 #include "leg_message.h"
adimmit 0:76c761d3caf1 10
adimmit 15:d3c93f01a02b 11 #define BYTES 196
adimmit 15:d3c93f01a02b 12 #define RX_LEN 196
adimmit 15:d3c93f01a02b 13 #define TX_LEN 124
adimmit 0:76c761d3caf1 14
adimmit 15:d3c93f01a02b 15 // spi buffers
adimmit 15:d3c93f01a02b 16 uint8_t rx_buff[RX_LEN];
adimmit 15:d3c93f01a02b 17 uint8_t tx_buff[TX_LEN];
adimmit 14:8a7fd1ebc209 18
adimmit 15:d3c93f01a02b 19 // vars
adimmit 0:76c761d3caf1 20 spi_data_t spi_data; // data from spine to up
adimmit 0:76c761d3caf1 21 spi_command_t spi_command; // data from up to spine
adimmit 15:d3c93f01a02b 22 spi_command_t tmp_crc_chk; // data from up to spine
adimmit 0:76c761d3caf1 23
adimmit 0:76c761d3caf1 24 Serial pc(PA_2, PA_3);
adimmit 0:76c761d3caf1 25
adimmit 0:76c761d3caf1 26 int spi_enabled = 0;
adimmit 0:76c761d3caf1 27 InterruptIn cs(PA_4);
adimmit 16:8f8adc5f8f0a 28 SPISlave *spi;
adimmit 16:8f8adc5f8f0a 29 //SPISlave spi(PA_7, PA_6, PA_5, PA_4);
adimmit 0:76c761d3caf1 30
adimmit 0:76c761d3caf1 31 uint32_t xor_checksum(uint32_t* data, size_t len)
adimmit 0:76c761d3caf1 32 {
adimmit 0:76c761d3caf1 33 uint32_t t = 0;
adimmit 0:76c761d3caf1 34 for(int i = 0; i < len; i++)
adimmit 0:76c761d3caf1 35 t = t ^ data[i];
adimmit 0:76c761d3caf1 36 return t;
adimmit 0:76c761d3caf1 37 }
adimmit 0:76c761d3caf1 38
adimmit 15:d3c93f01a02b 39 void process()
adimmit 15:d3c93f01a02b 40 {
adimmit 15:d3c93f01a02b 41 // update qs
adimmit 15:d3c93f01a02b 42 spi_data.q_1s[0] = spi_command.q_des_1s[0]+1.0;
adimmit 15:d3c93f01a02b 43 spi_data.q_2s[0] = spi_command.q_des_2s[0]+1.0;
adimmit 15:d3c93f01a02b 44 spi_data.q_3s[0] = spi_command.q_des_3s[0]+1.0;
adimmit 15:d3c93f01a02b 45 spi_data.q_1s[1] = spi_command.q_des_1s[1]+1.0;
adimmit 15:d3c93f01a02b 46 spi_data.q_2s[1] = spi_command.q_des_2s[1]+1.0;
adimmit 15:d3c93f01a02b 47 spi_data.q_3s[1] = spi_command.q_des_3s[1]+1.0;
adimmit 15:d3c93f01a02b 48 spi_data.q_1s[2] = spi_command.q_des_1s[2]+1.0;
adimmit 15:d3c93f01a02b 49 spi_data.q_2s[2] = spi_command.q_des_2s[2]+1.0;
adimmit 15:d3c93f01a02b 50 spi_data.q_3s[2] = spi_command.q_des_3s[2]+1.0;
adimmit 15:d3c93f01a02b 51 // update qds
adimmit 15:d3c93f01a02b 52 spi_data.qd_1s[0] = spi_command.qd_des_1s[0]+1.0;
adimmit 15:d3c93f01a02b 53 spi_data.qd_2s[0] = spi_command.qd_des_2s[0]+1.0;
adimmit 15:d3c93f01a02b 54 spi_data.qd_3s[0] = spi_command.qd_des_3s[0]+1.0;
adimmit 15:d3c93f01a02b 55 spi_data.qd_1s[1] = spi_command.qd_des_1s[1]+1.0;
adimmit 15:d3c93f01a02b 56 spi_data.qd_2s[1] = spi_command.qd_des_2s[1]+1.0;
adimmit 15:d3c93f01a02b 57 spi_data.qd_3s[1] = spi_command.qd_des_3s[1]+1.0;
adimmit 15:d3c93f01a02b 58 spi_data.qd_1s[2] = spi_command.qd_des_1s[2]+1.0;
adimmit 15:d3c93f01a02b 59 spi_data.qd_2s[2] = spi_command.qd_des_2s[2]+1.0;
adimmit 15:d3c93f01a02b 60 spi_data.qd_3s[2] = spi_command.qd_des_3s[2]+1.0;
adimmit 15:d3c93f01a02b 61 // update taus
adimmit 15:d3c93f01a02b 62 spi_data.tau_1s[0] = spi_command.tau_1s_ff[0]+1.0;
adimmit 15:d3c93f01a02b 63 spi_data.tau_2s[0] = spi_command.tau_2s_ff[0]+1.0;
adimmit 15:d3c93f01a02b 64 spi_data.tau_3s[0] = spi_command.tau_3s_ff[0]+1.0;
adimmit 15:d3c93f01a02b 65 spi_data.tau_1s[1] = spi_command.tau_1s_ff[1]+1.0;
adimmit 15:d3c93f01a02b 66 spi_data.tau_2s[1] = spi_command.tau_2s_ff[1]+1.0;
adimmit 15:d3c93f01a02b 67 spi_data.tau_3s[1] = spi_command.tau_3s_ff[1]+1.0;
adimmit 15:d3c93f01a02b 68 spi_data.tau_1s[2] = spi_command.tau_1s_ff[2]+1.0;
adimmit 15:d3c93f01a02b 69 spi_data.tau_2s[2] = spi_command.tau_2s_ff[2]+1.0;
adimmit 15:d3c93f01a02b 70 spi_data.tau_3s[2] = spi_command.tau_3s_ff[2]+1.0;
adimmit 15:d3c93f01a02b 71 // UDPATE FLAGS
adimmit 15:d3c93f01a02b 72 spi_data.flags[0] = 0;
adimmit 15:d3c93f01a02b 73 spi_data.flags[1] = 0;
adimmit 15:d3c93f01a02b 74 spi_data.flags[2] = 0;
adimmit 15:d3c93f01a02b 75 // UPDATE CHECKSUM
adimmit 15:d3c93f01a02b 76 spi_data.checksum = xor_checksum((uint32_t*)&spi_data, 30); //NOTE, CHECK THIS WE WANT TO DO IT ON THE FIRST 16 SPI BYTES
adimmit 2:32f69175c78e 77 }
adimmit 2:32f69175c78e 78
adimmit 0:76c761d3caf1 79 void spi_isr(void)
adimmit 0:76c761d3caf1 80 {
adimmit 0:76c761d3caf1 81 int bytecount = 0;
adimmit 15:d3c93f01a02b 82 //spi.reply(tx_buff[0]);
adimmit 15:d3c93f01a02b 83 while (cs==0){
adimmit 16:8f8adc5f8f0a 84 if(spi->receive()) {
adimmit 16:8f8adc5f8f0a 85 rx_buff[bytecount] = spi->read();
adimmit 16:8f8adc5f8f0a 86 if (bytecount<TX_LEN) {spi->reply(tx_buff[bytecount]);}
adimmit 0:76c761d3caf1 87 bytecount++;
adimmit 0:76c761d3caf1 88 }
adimmit 0:76c761d3caf1 89 }
adimmit 15:d3c93f01a02b 90
adimmit 15:d3c93f01a02b 91 //update crc_chk from buffer
adimmit 15:d3c93f01a02b 92 for(int i = 0; i < RX_LEN; i++) {((uint8_t*)(&tmp_crc_chk))[i] = rx_buff[i];}
adimmit 15:d3c93f01a02b 93 // CHECK THE CHECKSUM
adimmit 15:d3c93f01a02b 94 uint32_t _crc = xor_checksum((uint32_t*)&tmp_crc_chk, 48);
adimmit 15:d3c93f01a02b 95 // READ CHECKSUM
adimmit 15:d3c93f01a02b 96 uint32_t _rx_crc = tmp_crc_chk.checksum;
adimmit 15:d3c93f01a02b 97
adimmit 15:d3c93f01a02b 98 if(_crc == _rx_crc) {
adimmit 15:d3c93f01a02b 99 //pc.printf("CHECKSUM PASSED...");
adimmit 15:d3c93f01a02b 100 //update crc_chk from buffer
adimmit 15:d3c93f01a02b 101 spi_command = tmp_crc_chk;
adimmit 15:d3c93f01a02b 102 //do math on the input
adimmit 15:d3c93f01a02b 103 process();
adimmit 15:d3c93f01a02b 104 //populate the output
adimmit 15:d3c93f01a02b 105 for(int i = 0; i < TX_LEN; i++) {tx_buff[i] = ((uint8_t*)(&spi_data))[i];}
adimmit 15:d3c93f01a02b 106 }
adimmit 15:d3c93f01a02b 107 else {pc.printf("CRC FAILED...");}
adimmit 15:d3c93f01a02b 108 }
adimmit 0:76c761d3caf1 109
adimmit 0:76c761d3caf1 110
adimmit 0:76c761d3caf1 111 int main() {
adimmit 0:76c761d3caf1 112 wait(1);
adimmit 1:aa253b5f5b65 113 pc.baud(115200); //MAYBE CHANGE THIS IF NEEDED
adimmit 0:76c761d3caf1 114 //cs.fall(&spi_isr);
adimmit 0:76c761d3caf1 115
adimmit 15:d3c93f01a02b 116 memset(&tx_buff, 0, RX_LEN * sizeof(uint8_t));
adimmit 15:d3c93f01a02b 117 memset(&rx_buff, 0, TX_LEN * sizeof(uint8_t));
adimmit 1:aa253b5f5b65 118
adimmit 1:aa253b5f5b65 119 //just debugging things
adimmit 1:aa253b5f5b65 120 pc.printf("SETUP VARS ALL DONE\n");
adimmit 0:76c761d3caf1 121
adimmit 0:76c761d3caf1 122 // SPI doesn't work if enabled while the CS pin is pulled low
adimmit 0:76c761d3caf1 123 // Wait for CS to not be low, then enable SPI
adimmit 0:76c761d3caf1 124 if(!spi_enabled){
adimmit 15:d3c93f01a02b 125 while((spi_enabled==0) && (cs.read()==0)){pc.printf("waiting for CS Pin\n"); wait_us(10);}
adimmit 16:8f8adc5f8f0a 126 spi = new SPISlave(PA_7, PA_6, PA_5, PA_4);
adimmit 16:8f8adc5f8f0a 127 spi->format(8, 0);
adimmit 16:8f8adc5f8f0a 128 spi->frequency(500000);
adimmit 16:8f8adc5f8f0a 129 spi->reply(0x0);
adimmit 0:76c761d3caf1 130 spi_enabled = 1;
adimmit 15:d3c93f01a02b 131 cs.fall(&spi_isr);
adimmit 1:aa253b5f5b65 132 pc.printf("SPI ENABLED AND READY\n");
adimmit 0:76c761d3caf1 133 }
adimmit 0:76c761d3caf1 134
adimmit 15:d3c93f01a02b 135 //initialize the tx_buff
adimmit 15:d3c93f01a02b 136 for(int i = 0; i < TX_LEN; i++) {
adimmit 15:d3c93f01a02b 137 tx_buff[i] = ((uint8_t*)(&spi_data))[i];
adimmit 15:d3c93f01a02b 138 }
adimmit 15:d3c93f01a02b 139 //initialize the tx_buff
adimmit 15:d3c93f01a02b 140 for(int i = 0; i < RX_LEN; i++) {
adimmit 15:d3c93f01a02b 141 tx_buff[i] = ((uint8_t*)(&spi_command))[i];
adimmit 15:d3c93f01a02b 142 }
adimmit 15:d3c93f01a02b 143
adimmit 0:76c761d3caf1 144 while(1) {
adimmit 15:d3c93f01a02b 145 //do a thing
adimmit 13:ad3ca70bf929 146 }
adimmit 2:32f69175c78e 147
adimmit 0:76c761d3caf1 148 }