semin ahn
/
zeta_stm_kinetic
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MPU9250/MPU9250RegisterMap.h@3:a4677501ae87, 2021-11-30 (annotated)
- Committer:
- _seminahn
- Date:
- Tue Nov 30 08:13:05 2021 +0000
- Revision:
- 3:a4677501ae87
- Parent:
- 0:4ff8aeb3e4d1
v1.2.5, change imu freq
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| _seminahn | 0:4ff8aeb3e4d1 | 1 | #ifndef MPU9250REGISTERMAP_H |
| _seminahn | 0:4ff8aeb3e4d1 | 2 | #define MPU9250REGISTERMAP_H |
| _seminahn | 0:4ff8aeb3e4d1 | 3 | #include <cmath> |
| _seminahn | 0:4ff8aeb3e4d1 | 4 | #include "mbed.h" |
| _seminahn | 0:4ff8aeb3e4d1 | 5 | //Magnetometer Registers ================================ |
| _seminahn | 0:4ff8aeb3e4d1 | 6 | #define AK8963_WHO_AM_I 0x00 // should return 0x48 |
| _seminahn | 0:4ff8aeb3e4d1 | 7 | #define AK8963_INFO 0x01 |
| _seminahn | 0:4ff8aeb3e4d1 | 8 | #define AK8963_ST1 0x02 // data ready status bit 0 |
| _seminahn | 0:4ff8aeb3e4d1 | 9 | #define AK8963_XOUT_L 0x03 // data |
| _seminahn | 0:4ff8aeb3e4d1 | 10 | #define AK8963_XOUT_H 0x04 |
| _seminahn | 0:4ff8aeb3e4d1 | 11 | #define AK8963_YOUT_L 0x05 |
| _seminahn | 0:4ff8aeb3e4d1 | 12 | #define AK8963_YOUT_H 0x06 |
| _seminahn | 0:4ff8aeb3e4d1 | 13 | #define AK8963_ZOUT_L 0x07 |
| _seminahn | 0:4ff8aeb3e4d1 | 14 | #define AK8963_ZOUT_H 0x08 |
| _seminahn | 0:4ff8aeb3e4d1 | 15 | #define AK8963_ST2 0x09 // Data overflow bit 3 and data read error status bit 2 |
| _seminahn | 0:4ff8aeb3e4d1 | 16 | #define AK8963_CNTL 0x0A // Power down (0000), single-measurement (0001), self-test (1000) and Fuse ROM (1111) modes on bits 3:0 |
| _seminahn | 0:4ff8aeb3e4d1 | 17 | #define AK8963_CNTL2 0x0B |
| _seminahn | 0:4ff8aeb3e4d1 | 18 | #define AK8963_ASTC 0x0C // Self test control |
| _seminahn | 0:4ff8aeb3e4d1 | 19 | #define AK8963_I2CDIS 0x0F // I2C disable |
| _seminahn | 0:4ff8aeb3e4d1 | 20 | #define AK8963_ASAX 0x10 // Fuse ROM x-axis sensitivity adjustment value |
| _seminahn | 0:4ff8aeb3e4d1 | 21 | #define AK8963_ASAY 0x11 // Fuse ROM y-axis sensitivity adjustment value |
| _seminahn | 0:4ff8aeb3e4d1 | 22 | #define AK8963_ASAZ 0x12 // Fuse ROM z-axis sensitivity adjustment value |
| _seminahn | 0:4ff8aeb3e4d1 | 23 | //IMU Registers ========================================== |
| _seminahn | 0:4ff8aeb3e4d1 | 24 | #define SELF_TEST_X_GYRO 0x00 |
| _seminahn | 0:4ff8aeb3e4d1 | 25 | #define SELF_TEST_Y_GYRO 0x01 |
| _seminahn | 0:4ff8aeb3e4d1 | 26 | #define SELF_TEST_Z_GYRO 0x02 |
| _seminahn | 0:4ff8aeb3e4d1 | 27 | #define SELF_TEST_X_ACCEL 0x0D |
| _seminahn | 0:4ff8aeb3e4d1 | 28 | #define SELF_TEST_Y_ACCEL 0x0E |
| _seminahn | 0:4ff8aeb3e4d1 | 29 | #define SELF_TEST_Z_ACCEL 0x0F |
| _seminahn | 0:4ff8aeb3e4d1 | 30 | #define SELF_TEST_A 0x10 |
| _seminahn | 0:4ff8aeb3e4d1 | 31 | #define XG_OFFSET_H 0x13 // User-defined trim values for gyroscope |
| _seminahn | 0:4ff8aeb3e4d1 | 32 | #define XG_OFFSET_L 0x14 |
| _seminahn | 0:4ff8aeb3e4d1 | 33 | #define YG_OFFSET_H 0x15 |
| _seminahn | 0:4ff8aeb3e4d1 | 34 | #define YG_OFFSET_L 0x16 |
| _seminahn | 0:4ff8aeb3e4d1 | 35 | #define ZG_OFFSET_H 0x17 |
| _seminahn | 0:4ff8aeb3e4d1 | 36 | #define ZG_OFFSET_L 0x18 |
| _seminahn | 0:4ff8aeb3e4d1 | 37 | #define SMPLRT_DIV 0x19 |
| _seminahn | 0:4ff8aeb3e4d1 | 38 | #define MPU_CONFIG 0x1A |
| _seminahn | 0:4ff8aeb3e4d1 | 39 | #define GYRO_CONFIG 0x1B |
| _seminahn | 0:4ff8aeb3e4d1 | 40 | #define ACCEL_CONFIG 0x1C |
| _seminahn | 0:4ff8aeb3e4d1 | 41 | #define ACCEL_CONFIG2 0x1D |
| _seminahn | 0:4ff8aeb3e4d1 | 42 | #define LP_ACCEL_ODR 0x1E |
| _seminahn | 0:4ff8aeb3e4d1 | 43 | #define WOM_THR 0x1F |
| _seminahn | 0:4ff8aeb3e4d1 | 44 | #define MOT_DUR 0x20 // Duration counter threshold for motion interrupt generation, 1 kHz rate, LSB = 1 ms |
| _seminahn | 0:4ff8aeb3e4d1 | 45 | #define ZMOT_THR 0x21 // Zero-motion detection threshold bits [7:0] |
| _seminahn | 0:4ff8aeb3e4d1 | 46 | #define ZRMOT_DUR 0x22 // Duration counter threshold for zero motion interrupt generation, 16 Hz rate, LSB = 64 ms |
| _seminahn | 0:4ff8aeb3e4d1 | 47 | #define FIFO_EN 0x23 |
| _seminahn | 0:4ff8aeb3e4d1 | 48 | #define I2C_MST_CTRL 0x24 |
| _seminahn | 0:4ff8aeb3e4d1 | 49 | #define I2C_SLV0_ADDR 0x25 |
| _seminahn | 0:4ff8aeb3e4d1 | 50 | #define I2C_SLV0_REG 0x26 |
| _seminahn | 0:4ff8aeb3e4d1 | 51 | #define I2C_SLV0_CTRL 0x27 |
| _seminahn | 0:4ff8aeb3e4d1 | 52 | #define I2C_SLV1_ADDR 0x28 |
| _seminahn | 0:4ff8aeb3e4d1 | 53 | #define I2C_SLV1_REG 0x29 |
| _seminahn | 0:4ff8aeb3e4d1 | 54 | #define I2C_SLV1_CTRL 0x2A |
| _seminahn | 0:4ff8aeb3e4d1 | 55 | #define I2C_SLV2_ADDR 0x2B |
| _seminahn | 0:4ff8aeb3e4d1 | 56 | #define I2C_SLV2_REG 0x2C |
| _seminahn | 0:4ff8aeb3e4d1 | 57 | #define I2C_SLV2_CTRL 0x2D |
| _seminahn | 0:4ff8aeb3e4d1 | 58 | #define I2C_SLV3_ADDR 0x2E |
| _seminahn | 0:4ff8aeb3e4d1 | 59 | #define I2C_SLV3_REG 0x2F |
| _seminahn | 0:4ff8aeb3e4d1 | 60 | #define I2C_SLV3_CTRL 0x30 |
| _seminahn | 0:4ff8aeb3e4d1 | 61 | #define I2C_SLV4_ADDR 0x31 |
| _seminahn | 0:4ff8aeb3e4d1 | 62 | #define I2C_SLV4_REG 0x32 |
| _seminahn | 0:4ff8aeb3e4d1 | 63 | #define I2C_SLV4_DO 0x33 |
| _seminahn | 0:4ff8aeb3e4d1 | 64 | #define I2C_SLV4_CTRL 0x34 |
| _seminahn | 0:4ff8aeb3e4d1 | 65 | #define I2C_SLV4_DI 0x35 |
| _seminahn | 0:4ff8aeb3e4d1 | 66 | #define I2C_MST_STATUS 0x36 |
| _seminahn | 0:4ff8aeb3e4d1 | 67 | #define INT_PIN_CFG 0x37 |
| _seminahn | 0:4ff8aeb3e4d1 | 68 | #define INT_ENABLE 0x38 |
| _seminahn | 0:4ff8aeb3e4d1 | 69 | #define DMP_INT_STATUS 0x39 // Check DMP interrupt |
| _seminahn | 0:4ff8aeb3e4d1 | 70 | #define INT_STATUS 0x3A |
| _seminahn | 0:4ff8aeb3e4d1 | 71 | #define ACCEL_XOUT_H 0x3B |
| _seminahn | 0:4ff8aeb3e4d1 | 72 | #define ACCEL_XOUT_L 0x3C |
| _seminahn | 0:4ff8aeb3e4d1 | 73 | #define ACCEL_YOUT_H 0x3D |
| _seminahn | 0:4ff8aeb3e4d1 | 74 | #define ACCEL_YOUT_L 0x3E |
| _seminahn | 0:4ff8aeb3e4d1 | 75 | #define ACCEL_ZOUT_H 0x3F |
| _seminahn | 0:4ff8aeb3e4d1 | 76 | #define ACCEL_ZOUT_L 0x40 |
| _seminahn | 0:4ff8aeb3e4d1 | 77 | #define TEMP_OUT_H 0x41 |
| _seminahn | 0:4ff8aeb3e4d1 | 78 | #define TEMP_OUT_L 0x42 |
| _seminahn | 0:4ff8aeb3e4d1 | 79 | #define GYRO_XOUT_H 0x43 |
| _seminahn | 0:4ff8aeb3e4d1 | 80 | #define GYRO_XOUT_L 0x44 |
| _seminahn | 0:4ff8aeb3e4d1 | 81 | #define GYRO_YOUT_H 0x45 |
| _seminahn | 0:4ff8aeb3e4d1 | 82 | #define GYRO_YOUT_L 0x46 |
| _seminahn | 0:4ff8aeb3e4d1 | 83 | #define GYRO_ZOUT_H 0x47 |
| _seminahn | 0:4ff8aeb3e4d1 | 84 | #define GYRO_ZOUT_L 0x48 |
| _seminahn | 0:4ff8aeb3e4d1 | 85 | #define EXT_SENS_DATA_00 0x49 |
| _seminahn | 0:4ff8aeb3e4d1 | 86 | #define EXT_SENS_DATA_01 0x4A |
| _seminahn | 0:4ff8aeb3e4d1 | 87 | #define EXT_SENS_DATA_02 0x4B |
| _seminahn | 0:4ff8aeb3e4d1 | 88 | #define EXT_SENS_DATA_03 0x4C |
| _seminahn | 0:4ff8aeb3e4d1 | 89 | #define EXT_SENS_DATA_04 0x4D |
| _seminahn | 0:4ff8aeb3e4d1 | 90 | #define EXT_SENS_DATA_05 0x4E |
| _seminahn | 0:4ff8aeb3e4d1 | 91 | #define EXT_SENS_DATA_06 0x4F |
| _seminahn | 0:4ff8aeb3e4d1 | 92 | #define EXT_SENS_DATA_07 0x50 |
| _seminahn | 0:4ff8aeb3e4d1 | 93 | #define EXT_SENS_DATA_08 0x51 |
| _seminahn | 0:4ff8aeb3e4d1 | 94 | #define EXT_SENS_DATA_09 0x52 |
| _seminahn | 0:4ff8aeb3e4d1 | 95 | #define EXT_SENS_DATA_10 0x53 |
| _seminahn | 0:4ff8aeb3e4d1 | 96 | #define EXT_SENS_DATA_11 0x54 |
| _seminahn | 0:4ff8aeb3e4d1 | 97 | #define EXT_SENS_DATA_12 0x55 |
| _seminahn | 0:4ff8aeb3e4d1 | 98 | #define EXT_SENS_DATA_13 0x56 |
| _seminahn | 0:4ff8aeb3e4d1 | 99 | #define EXT_SENS_DATA_14 0x57 |
| _seminahn | 0:4ff8aeb3e4d1 | 100 | #define EXT_SENS_DATA_15 0x58 |
| _seminahn | 0:4ff8aeb3e4d1 | 101 | #define EXT_SENS_DATA_16 0x59 |
| _seminahn | 0:4ff8aeb3e4d1 | 102 | #define EXT_SENS_DATA_17 0x5A |
| _seminahn | 0:4ff8aeb3e4d1 | 103 | #define EXT_SENS_DATA_18 0x5B |
| _seminahn | 0:4ff8aeb3e4d1 | 104 | #define EXT_SENS_DATA_19 0x5C |
| _seminahn | 0:4ff8aeb3e4d1 | 105 | #define EXT_SENS_DATA_20 0x5D |
| _seminahn | 0:4ff8aeb3e4d1 | 106 | #define EXT_SENS_DATA_21 0x5E |
| _seminahn | 0:4ff8aeb3e4d1 | 107 | #define EXT_SENS_DATA_22 0x5F |
| _seminahn | 0:4ff8aeb3e4d1 | 108 | #define EXT_SENS_DATA_23 0x60 |
| _seminahn | 0:4ff8aeb3e4d1 | 109 | #define MOT_DETECT_STATUS 0x61 |
| _seminahn | 0:4ff8aeb3e4d1 | 110 | #define I2C_SLV0_DO 0x63 |
| _seminahn | 0:4ff8aeb3e4d1 | 111 | #define I2C_SLV1_DO 0x64 |
| _seminahn | 0:4ff8aeb3e4d1 | 112 | #define I2C_SLV2_DO 0x65 |
| _seminahn | 0:4ff8aeb3e4d1 | 113 | #define I2C_SLV3_DO 0x66 |
| _seminahn | 0:4ff8aeb3e4d1 | 114 | #define I2C_MST_DELAY_CTRL 0x67 |
| _seminahn | 0:4ff8aeb3e4d1 | 115 | #define SIGNAL_PATH_RESET 0x68 |
| _seminahn | 0:4ff8aeb3e4d1 | 116 | #define MOT_DETECT_CTRL 0x69 |
| _seminahn | 0:4ff8aeb3e4d1 | 117 | #define USER_CTRL 0x6A // Bit 7 enable DMP, bit 3 reset DMP |
| _seminahn | 0:4ff8aeb3e4d1 | 118 | #define PWR_MGMT_1 0x6B // Device defaults to the SLEEP mode |
| _seminahn | 0:4ff8aeb3e4d1 | 119 | #define PWR_MGMT_2 0x6C |
| _seminahn | 0:4ff8aeb3e4d1 | 120 | #define DMP_BANK 0x6D // Activates a specific bank in the DMP |
| _seminahn | 0:4ff8aeb3e4d1 | 121 | #define DMP_RW_PNT 0x6E // Set read/write pointer to a specific start address in specified DMP bank |
| _seminahn | 0:4ff8aeb3e4d1 | 122 | #define DMP_REG 0x6F // Register in DMP from which to read or to which to write |
| _seminahn | 0:4ff8aeb3e4d1 | 123 | #define DMP_REG_1 0x70 |
| _seminahn | 0:4ff8aeb3e4d1 | 124 | #define DMP_REG_2 0x71 |
| _seminahn | 0:4ff8aeb3e4d1 | 125 | #define FIFO_COUNTH 0x72 |
| _seminahn | 0:4ff8aeb3e4d1 | 126 | #define FIFO_COUNTL 0x73 |
| _seminahn | 0:4ff8aeb3e4d1 | 127 | #define FIFO_R_W 0x74 |
| _seminahn | 0:4ff8aeb3e4d1 | 128 | #define WHO_AM_I_MPU9250 0x75 // Should return 0x71 |
| _seminahn | 0:4ff8aeb3e4d1 | 129 | #define XA_OFFSET_H 0x77 |
| _seminahn | 0:4ff8aeb3e4d1 | 130 | #define XA_OFFSET_L 0x78 |
| _seminahn | 0:4ff8aeb3e4d1 | 131 | #define YA_OFFSET_H 0x7A |
| _seminahn | 0:4ff8aeb3e4d1 | 132 | #define YA_OFFSET_L 0x7B |
| _seminahn | 0:4ff8aeb3e4d1 | 133 | #define ZA_OFFSET_H 0x7D |
| _seminahn | 0:4ff8aeb3e4d1 | 134 | #define ZA_OFFSET_L 0x7E |
| _seminahn | 0:4ff8aeb3e4d1 | 135 | // =================== Importat values |
| _seminahn | 0:4ff8aeb3e4d1 | 136 | #define AK8963_I2C_ADDR 0x0C |
| _seminahn | 0:4ff8aeb3e4d1 | 137 | #define AK8963_RESET 0x01// @ CNTL2 |
| _seminahn | 0:4ff8aeb3e4d1 | 138 | #define MPU9250_WHOAMI_DEFAULT_VALUE 0x71 // 고유번호 |
| _seminahn | 0:4ff8aeb3e4d1 | 139 | #define AK8963_WHOAMI_DEFAULT_VALUE 0x48 |
| _seminahn | 0:4ff8aeb3e4d1 | 140 | #define SPI_LS_CLOCK 15000000 // 1 MHz |
| _seminahn | 0:4ff8aeb3e4d1 | 141 | #define SPI_HS_CLOCK 15000000 // 15 MHz |
| _seminahn | 0:4ff8aeb3e4d1 | 142 | #define I2C_READ_FLAG 0x80 // for all I2C |
| _seminahn | 0:4ff8aeb3e4d1 | 143 | #define SPI_READ 0x80 //SPI READ |
| _seminahn | 0:4ff8aeb3e4d1 | 144 | #define I2C_MST_EN 0x20 // @ USER_CTRL |
| _seminahn | 0:4ff8aeb3e4d1 | 145 | #define I2C_MST_CLK 0x0D // @I2C_MST_CTRL 400KHz |
| _seminahn | 0:4ff8aeb3e4d1 | 146 | #define I2C_SLV0_EN 0x80 // @I2C_SLV0_CTRL slave 0 enable |
| _seminahn | 0:4ff8aeb3e4d1 | 147 | #define CLOCK_SEL_PLL 0x01 // @ PWR_MGMNT_1 |
| _seminahn | 0:4ff8aeb3e4d1 | 148 | #define PWR_RESET 0x80 // @ PWR_MGMNT_1 |
| _seminahn | 0:4ff8aeb3e4d1 | 149 | #define SEN_ENABLE 0x00 // @ PWR_MGMNT_2 |
| _seminahn | 0:4ff8aeb3e4d1 | 150 | // some conversion |
| _seminahn | 0:4ff8aeb3e4d1 | 151 | #ifndef M_PI |
| _seminahn | 0:4ff8aeb3e4d1 | 152 | #define M_PI 3.14159265358979323846 |
| _seminahn | 0:4ff8aeb3e4d1 | 153 | #endif |
| _seminahn | 0:4ff8aeb3e4d1 | 154 | #define DEG_TO_RAD ( M_PI /180) |
| _seminahn | 0:4ff8aeb3e4d1 | 155 | #define RAD_TO_DEG (180/M_PI) |
| _seminahn | 0:4ff8aeb3e4d1 | 156 | #define TWO_PI (2*M_PI) |
| _seminahn | 0:4ff8aeb3e4d1 | 157 | // complementary filter |
| _seminahn | 0:4ff8aeb3e4d1 | 158 | |
| _seminahn | 0:4ff8aeb3e4d1 | 159 | |
| _seminahn | 0:4ff8aeb3e4d1 | 160 | |
| _seminahn | 0:4ff8aeb3e4d1 | 161 | #endif // MPU9250REGISTERMAP_H |
| _seminahn | 0:4ff8aeb3e4d1 | 162 |