Mateusz Kowalik / Application

USB Serial application

Fork of USBSerial_HelloWorld by Samuel Mokrani

mbed-dev/targets/TARGET_NXP/TARGET_LPC43XX/README.txt@10:41552d038a69, 2017-01-10 (annotated)

Committer:
Zaitsev
Date:
Tue Jan 10 20:42:26 2017 +0000
Revision:
10:41552d038a69
USB Serial bi-directional bridge

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Zaitsev 10:41552d038a69 1 mbed port to NXP LPC43xx
Zaitsev 10:41552d038a69 2 ========================
Zaitsev 10:41552d038a69 3 Updated: 07/11/14
Zaitsev 10:41552d038a69 4
Zaitsev 10:41552d038a69 5 The NXP LPC43xx microcontrollers includes multiple Cortex-M cores in a single
Zaitsev 10:41552d038a69 6 microcontroller package. This port allows mbed developers to take advantage
Zaitsev 10:41552d038a69 7 of the LPC43xx in their application using APIs that they are familiar with.
Zaitsev 10:41552d038a69 8 Some of the key features of the LPC43xx include:
Zaitsev 10:41552d038a69 9
Zaitsev 10:41552d038a69 10 * Dual core ARM Cortex-M4/M0 both capable of up to 204 MHz
Zaitsev 10:41552d038a69 11 * Up to 264 KB SRAM, 1 MB internal flash
Zaitsev 10:41552d038a69 12 * Two High-speed USB 2.0 interfaces
Zaitsev 10:41552d038a69 13 * Ethernet MAC
Zaitsev 10:41552d038a69 14 * LCD interface
Zaitsev 10:41552d038a69 15 * Quad-SPI Flash Interface (SPIFI)
Zaitsev 10:41552d038a69 16 * State Configurable Timer (SCT)
Zaitsev 10:41552d038a69 17 * Serial GPIO (SGPIO)
Zaitsev 10:41552d038a69 18 * Up to 164 GPIO
Zaitsev 10:41552d038a69 19
Zaitsev 10:41552d038a69 20 The NXP LPC18xx is a single core Cortex-M3 implementation that is compatible
Zaitsev 10:41552d038a69 21 with the LPC43XX for cost-sensitive applications not requiring multiple cores.
Zaitsev 10:41552d038a69 22
Zaitsev 10:41552d038a69 23 mbed port to the LPC43XX - Micromint USA <support@micromint.com>
Zaitsev 10:41552d038a69 24
Zaitsev 10:41552d038a69 25 Compatibility
Zaitsev 10:41552d038a69 26 -------------
Zaitsev 10:41552d038a69 27 * This port has been tested with the following boards:
Zaitsev 10:41552d038a69 28 Board MCU RAM/Flash
Zaitsev 10:41552d038a69 29 Micromint Bambino 200 LPC4330 264K SRAM/4 MB SPIFI flash
Zaitsev 10:41552d038a69 30 Micromint Bambino 200E LPC4330 264K SRAM/8 MB SPIFI flash
Zaitsev 10:41552d038a69 31 Micromint Bambino 210 LPC4330 264K SRAM/4 MB SPIFI flash
Zaitsev 10:41552d038a69 32 Micromint Bambino 210E LPC4330 264K SRAM/8 MB SPIFI flash
Zaitsev 10:41552d038a69 33
Zaitsev 10:41552d038a69 34 * CMSIS-DAP debugging is implemented with the Micromint Bambino 210/210E.
Zaitsev 10:41552d038a69 35 To debug other LPC4330 targets, use a JTAG. The NXP DFU tool can be used
Zaitsev 10:41552d038a69 36 for flash programming.
Zaitsev 10:41552d038a69 37
Zaitsev 10:41552d038a69 38 * This port should support NXP LPC43XX and LPC18XX variants with a single
Zaitsev 10:41552d038a69 39 codebase. The core declaration specifies the binaries to be built:
Zaitsev 10:41552d038a69 40 mbed define CMSIS define MCU Target
Zaitsev 10:41552d038a69 41 __CORTEX_M4 CORE_M4 LPC43xx Cortex-M4
Zaitsev 10:41552d038a69 42 __CORTEX_M0 CORE_M0 LPC43xx Cortex-M0
Zaitsev 10:41552d038a69 43 __CORTEX_M3 CORE_M3 LPC18xx Cortex-M3
Zaitsev 10:41552d038a69 44 These MCUs all share the peripheral IP, common driver code is feasible.
Zaitsev 10:41552d038a69 45 Yet each variant can have different memory segments, peripherals, etc.
Zaitsev 10:41552d038a69 46 Plus, each board design can integrate different external peripherals
Zaitsev 10:41552d038a69 47 or interfaces. A future release of the mbed SDK and its build tools will
Zaitsev 10:41552d038a69 48 support specifying the target board when building binaries. At this time
Zaitsev 10:41552d038a69 49 building binaries for different targets requires an external project or
Zaitsev 10:41552d038a69 50 Makefile.
Zaitsev 10:41552d038a69 51
Zaitsev 10:41552d038a69 52 * No testing has been done with LPC18xx hardware.
Zaitsev 10:41552d038a69 53
Zaitsev 10:41552d038a69 54 Notes
Zaitsev 10:41552d038a69 55 -----
Zaitsev 10:41552d038a69 56 * On the LPC43xx the hardware pin name and the GPIO pin name are not the same,
Zaitsev 10:41552d038a69 57 requiring different offsets for the SCU and GPIO registers. To simplify logic
Zaitsev 10:41552d038a69 58 the pin identifier encodes the offsets. Macros are used for decoding.
Zaitsev 10:41552d038a69 59 For example, P6_11 corresponds to GPIO3[7] and is encoded/decoded as follows:
Zaitsev 10:41552d038a69 60
Zaitsev 10:41552d038a69 61 P6_11 = MBED_PIN(0x06, 11, 3, 7) = 0x032C0067
Zaitsev 10:41552d038a69 62
Zaitsev 10:41552d038a69 63 MBED_SCU_REG(P6_11) = 0x4008632C MBED_GPIO_PORT(P6_11) = 3
Zaitsev 10:41552d038a69 64 MBED_GPIO_REG(P6_11) = 0x400F4000 MBED_GPIO_PIN(P6_11) = 7
Zaitsev 10:41552d038a69 65
Zaitsev 10:41552d038a69 66 * Pin names use multiple aliases to support Arduino naming conventions as well
Zaitsev 10:41552d038a69 67 as others. For example, to use pin p21 on the Bambino 210 from mbed applications
Zaitsev 10:41552d038a69 68 the following aliases are equivalent: p21, D0, UART0_TX, COM1_TX, P6_4.
Zaitsev 10:41552d038a69 69 See the board pinout graphic and the PinNames.h for available aliases.
Zaitsev 10:41552d038a69 70
Zaitsev 10:41552d038a69 71 * The LPC43xx implements GPIO pin and group interrupts. Any pin in the 8 32-bit
Zaitsev 10:41552d038a69 72 GPIO ports can interrupt (LPC4350 supports up to 164). On group interrupts a
Zaitsev 10:41552d038a69 73 pin can only interrupt on the rising or falling edge, not both as required
Zaitsev 10:41552d038a69 74 by the mbed InterruptIn class. Also, group interrupts can't be cleared
Zaitsev 10:41552d038a69 75 individually. This implementation uses pin interrupts (8 on M4/M3, 1 on M0).
Zaitsev 10:41552d038a69 76 A future implementation may provide group interrupt support.
Zaitsev 10:41552d038a69 77
Zaitsev 10:41552d038a69 78 * The LPC3xx PWM driver uses the State Configurable Timer (SCT). The default
Zaitsev 10:41552d038a69 79 build (PWM_MODE=0) uses the unified 32-bit times. Applications that use PWM
Zaitsev 10:41552d038a69 80 and require other SCT uses can use the dual 16-bit mode by changing PWM_MODE
Zaitsev 10:41552d038a69 81 when building the library.