Yuta Togashi / QEI_hw

LPC1549でQEI(ハードウェアでエンコーダ読み取り)を実現します。 (.cppでピン指定しています(基本的にはどこでも使用可))

Dependents:   Tourobo2022_TBCMotorDriver

qeihw.h@6:cd0694454594, 2022-08-07 (annotated)

Committer:
YutaTogashi
Date:
Sun Aug 07 02:53:43 2022 +0000
Revision:
6:cd0694454594
Parent:
4:9385032f963b 
change encoder pin P0_3,P0_2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hexley 0:20a27391f6dc 1 /* mbed Library - QEIhw
hexley 0:20a27391f6dc 2 * Copyright (c) 2010, hball
hexley 0:20a27391f6dc 3 * released under MIT license http://mbed.org/licence/mit
hexley 0:20a27391f6dc 4 */
hexley 0:20a27391f6dc 5
YutaTogashi 4:9385032f963b 6 //qei.Direction() 回転方向
YutaTogashi 4:9385032f963b 7 //qei.GetPosition() パルスのcount数
YutaTogashi 4:9385032f963b 8 //qei.CalculateRPM(qei.GetVelocityCap(),100) RPM
YutaTogashi 4:9385032f963b 9
hexley 0:20a27391f6dc 10 /***********************************************************************//**
hexley 0:20a27391f6dc 11 * @file qeihw.h
hexley 0:20a27391f6dc 12 * @brief Header file for the qeihw driver. Adapted from the CMSIS
hexley 0:20a27391f6dc 13 * header, lpc17xx_qei.h, v 2.0
hexley 0:20a27391f6dc 14 * @version 0.0
hexley 0:20a27391f6dc 15 * @date 10 Dec 2010
hexley 0:20a27391f6dc 16 * @author hb
hexley 0:20a27391f6dc 17 **************************************************************************/
hexley 0:20a27391f6dc 18
hexley 0:20a27391f6dc 19
hexley 0:20a27391f6dc 20 #ifndef MBED_QEIHW_H
hexley 0:20a27391f6dc 21 #define MBED_QEIHW_H
hexley 0:20a27391f6dc 22
hexley 0:20a27391f6dc 23 /* Includes ------------------------------------------------------------------- */
hexley 0:20a27391f6dc 24 #include "mbed.h"
wt8008 3:68844cd35e64 25 #include "qeihw_lpc1549.h"
hexley 0:20a27391f6dc 26
hexley 0:20a27391f6dc 27 /* Public Types --------------------------------------------------------------- */
hexley 0:20a27391f6dc 28
hexley 0:20a27391f6dc 29 /* Flag Status type definition */
hexley 0:20a27391f6dc 30 typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
hexley 0:20a27391f6dc 31
hexley 0:20a27391f6dc 32 /* Functional State Definition */
hexley 0:20a27391f6dc 33 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
hexley 0:20a27391f6dc 34
hexley 0:20a27391f6dc 35
hexley 0:20a27391f6dc 36 /* Other definitions */
hexley 0:20a27391f6dc 37 #define XTAL_FREQ 12000000
hexley 0:20a27391f6dc 38
hexley 0:20a27391f6dc 39 /* Public Functions ----------------------------------------------------------- */
hexley 0:20a27391f6dc 40 /** @defgroup QEI_Public_Functions QEI Public Functions
hexley 0:20a27391f6dc 41 */
hexley 1:018226f83d80 42
hexley 1:018226f83d80 43 /** QEI hardware interface class
hexley 1:018226f83d80 44 * Requires mbed hardware modification: connect
hexley 1:018226f83d80 45 * encoder PhA to p1.20, and PhB to p1.23.
hexley 1:018226f83d80 46 *
hexley 1:018226f83d80 47 * Example:
hexley 1:018226f83d80 48 * @code
hexley 1:018226f83d80 49 * // Display changes in encoder position and direction
hexley 1:018226f83d80 50 #include "mbed.h"
hexley 1:018226f83d80 51 * #include "qeihw.h"
hexley 1:018226f83d80 52 *
hexley 1:018226f83d80 53 * DigitalOut led1(LED1);
hexley 1:018226f83d80 54 * DigitalOut led3(LED3);
hexley 1:018226f83d80 55 * QEIHW qei(QEI_DIRINV_NONE, QEI_SIGNALMODE_QUAD, QEI_CAPMODE_2X, QEI_INVINX_NONE );
hexley 1:018226f83d80 56 *
hexley 1:018226f83d80 57 * int main() {
hexley 1:018226f83d80 58 * int32_t temp, position = 0;
hexley 1:018226f83d80 59 * qei.SetDigiFilter(480UL);
hexley 1:018226f83d80 60 * qei.SetMaxPosition(0xFFFFFFFF);
hexley 1:018226f83d80 61 *
hexley 1:018226f83d80 62 * while(1) {
hexley 1:018226f83d80 63 * while(position == (temp = qei.GetPosition()) );
hexley 1:018226f83d80 64 * position = temp;
hexley 1:018226f83d80 65 * printf("New position = %d.\r\n", temp);
hexley 1:018226f83d80 66 * led1 = qei.Direction() == SET ? 1 : 0;
hexley 1:018226f83d80 67 * led3 = !led1;
hexley 1:018226f83d80 68 * wait(0.1);
hexley 1:018226f83d80 69 * }
hexley 1:018226f83d80 70 * }
hexley 1:018226f83d80 71 * @endcode
hexley 1:018226f83d80 72 */
hexley 1:018226f83d80 73
hexley 0:20a27391f6dc 74 class QEIHW {
hexley 0:20a27391f6dc 75 public:
hexley 0:20a27391f6dc 76
hexley 0:20a27391f6dc 77 /** Create a QEI object and configure it
hexley 0:20a27391f6dc 78 *
hexley 0:20a27391f6dc 79 * @param _dirinv Direction invert. When = 1, complements the QEICONF register DIR bit
hexley 0:20a27391f6dc 80 * @param _sigmode Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock
hexley 0:20a27391f6dc 81 * @param _capmode Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode).
hexley 0:20a27391f6dc 82 * @param _invinx Invert index. When = 1, inverts the sense of the index signal
hexley 0:20a27391f6dc 83 */
hexley 0:20a27391f6dc 84 QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx);
hexley 0:20a27391f6dc 85
hexley 0:20a27391f6dc 86 /** Resets value for each type of QEI value, such as velocity, position, etc.
hexley 0:20a27391f6dc 87 *
hexley 0:20a27391f6dc 88 * @param[in] ulResetType QEI Reset Type, should be one of the following:
hexley 0:20a27391f6dc 89 * - QEI_RESET_POS: Reset Position Counter
hexley 0:20a27391f6dc 90 * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal
hexley 0:20a27391f6dc 91 * - QEI_RESET_VEL: Reset Velocity
hexley 0:20a27391f6dc 92 * - QEI_RESET_IDX: Reset Index Counter
hexley 0:20a27391f6dc 93 */
hexley 0:20a27391f6dc 94 void Reset(uint32_t ulResetType);
hexley 0:20a27391f6dc 95
hexley 0:20a27391f6dc 96 /** Powers down the QEI block, returns pins to GPIO mode
hexley 0:20a27391f6dc 97 *
hexley 0:20a27391f6dc 98 */
hexley 0:20a27391f6dc 99 void DeInit();
hexley 0:20a27391f6dc 100
hexley 0:20a27391f6dc 101 /** Report direction (QEISTAT bit DIR)
hexley 0:20a27391f6dc 102 *
hexley 0:20a27391f6dc 103 * @return State of the DIR bit (SET or RESET)
hexley 0:20a27391f6dc 104 */
hexley 0:20a27391f6dc 105 FlagStatus Direction();
hexley 0:20a27391f6dc 106
hexley 0:20a27391f6dc 107 /**
hexley 0:20a27391f6dc 108 * @brief Get current position value in QEI peripheral
hexley 0:20a27391f6dc 109 *
hexley 0:20a27391f6dc 110 * @return Current position value of QEI peripheral
hexley 0:20a27391f6dc 111 */
hexley 0:20a27391f6dc 112 uint32_t GetPosition();
hexley 0:20a27391f6dc 113
hexley 0:20a27391f6dc 114 /** Set max position value for QEI peripheral
hexley 0:20a27391f6dc 115 *
hexley 0:20a27391f6dc 116 * @param[in] ulMaxPos Max position value to set
hexley 0:20a27391f6dc 117 * @return None
hexley 0:20a27391f6dc 118 */
hexley 0:20a27391f6dc 119 void SetMaxPosition(uint32_t ulMaxPos);
hexley 0:20a27391f6dc 120
hexley 0:20a27391f6dc 121 /** Set position compare value for QEI peripheral
hexley 0:20a27391f6dc 122 * @param[in] bPosCompCh Compare Position channel, should be:
hexley 0:20a27391f6dc 123 * - QEI_COMPPOS_CH_0: QEI compare position channel 0
hexley 0:20a27391f6dc 124 * - QEI_COMPPOS_CH_1: QEI compare position channel 1
hexley 0:20a27391f6dc 125 * - QEI_COMPPOS_CH_2: QEI compare position channel 2
hexley 0:20a27391f6dc 126 * @param[in] ulPosComp Compare Position value to set
hexley 0:20a27391f6dc 127 * @return None
hexley 0:20a27391f6dc 128 */
hexley 0:20a27391f6dc 129 void SetPositionComp( uint8_t bPosCompCh, uint32_t ulPosComp);
hexley 0:20a27391f6dc 130
hexley 0:20a27391f6dc 131 /** Get current index counter of QEI peripheral
hexley 0:20a27391f6dc 132 *
hexley 0:20a27391f6dc 133 * @return Current value of QEI index counter
hexley 0:20a27391f6dc 134 */
hexley 0:20a27391f6dc 135 uint32_t GetIndex();
hexley 0:20a27391f6dc 136
hexley 0:20a27391f6dc 137 /** Set value for index compare in QEI peripheral
hexley 0:20a27391f6dc 138 * @param[in] ulIndexComp Compare Index Value to set
hexley 0:20a27391f6dc 139 * @return None
hexley 0:20a27391f6dc 140 */
hexley 0:20a27391f6dc 141 void SetIndexComp( uint32_t ulIndexComp);
hexley 0:20a27391f6dc 142
hexley 0:20a27391f6dc 143 /** Set Velocity timer reload value
hexley 0:20a27391f6dc 144 *
hexley 0:20a27391f6dc 145 * @param[in] ulReloadValue Velocity timer reload count
hexley 0:20a27391f6dc 146 * @return None
hexley 0:20a27391f6dc 147 */
hexley 0:20a27391f6dc 148 void SetVelocityTimerReload( uint32_t ulReloadValue);
hexley 0:20a27391f6dc 149
hexley 0:20a27391f6dc 150 /** Set Velocity timer reload value in microseconds
hexley 0:20a27391f6dc 151 *
hexley 0:20a27391f6dc 152 * @param[in] ulReloadValue Velocity timer reload count
hexley 0:20a27391f6dc 153 * @return None
hexley 0:20a27391f6dc 154 */
hexley 0:20a27391f6dc 155 void SetVelocityTimerReload_us( uint32_t ulReloadValue);
hexley 0:20a27391f6dc 156
hexley 0:20a27391f6dc 157 /** Get current timer counter in QEI peripheral
hexley 0:20a27391f6dc 158 *
hexley 0:20a27391f6dc 159 * @return Current timer counter in QEI peripheral
hexley 0:20a27391f6dc 160 */
hexley 0:20a27391f6dc 161 uint32_t GetTimer();
hexley 0:20a27391f6dc 162
hexley 0:20a27391f6dc 163 /** Get current velocity pulse counter in current time period
hexley 0:20a27391f6dc 164 *
hexley 0:20a27391f6dc 165 * @return Current velocity pulse counter value
hexley 0:20a27391f6dc 166 */
hexley 0:20a27391f6dc 167 uint32_t GetVelocity();
hexley 0:20a27391f6dc 168
hexley 0:20a27391f6dc 169 /** Get the most recently measured velocity of the QEI. When
hexley 0:20a27391f6dc 170 * the Velocity timer in QEI is over-flow, the current velocity
hexley 0:20a27391f6dc 171 * value will be loaded into Velocity Capture register.
hexley 0:20a27391f6dc 172 *
hexley 0:20a27391f6dc 173 * @return The most recently measured velocity value
hexley 0:20a27391f6dc 174 */
hexley 0:20a27391f6dc 175 uint32_t GetVelocityCap();
hexley 0:20a27391f6dc 176
hexley 0:20a27391f6dc 177 /** Set Velocity Compare value for QEI peripheral
hexley 0:20a27391f6dc 178 *
hexley 0:20a27391f6dc 179 * @param[in] ulVelComp Compare Velocity value to set
hexley 0:20a27391f6dc 180 * @return None
hexley 0:20a27391f6dc 181 */
hexley 0:20a27391f6dc 182 void SetVelocityComp( uint32_t ulVelComp);
hexley 0:20a27391f6dc 183
hexley 0:20a27391f6dc 184 /** Set value of sampling count for the digital filter in
hexley 0:20a27391f6dc 185 * QEI peripheral
hexley 0:20a27391f6dc 186 *
hexley 0:20a27391f6dc 187 * @param[in] ulSamplingPulse Value of sampling count to set
hexley 0:20a27391f6dc 188 * @return None
hexley 0:20a27391f6dc 189 */
hexley 0:20a27391f6dc 190 void SetDigiFilter( uint32_t ulSamplingPulse);
hexley 0:20a27391f6dc 191
hexley 0:20a27391f6dc 192 /** Check whether if specified interrupt flag status in QEI
hexley 0:20a27391f6dc 193 * peripheral is set or not
hexley 0:20a27391f6dc 194 *
hexley 0:20a27391f6dc 195 * @param[in] ulIntType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 196 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 197 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 198 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 199 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 200 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 201 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 202 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 203 current position interrupt
hexley 0:20a27391f6dc 204 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 205 current position interrupt
hexley 0:20a27391f6dc 206 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 207 current position interrupt
hexley 0:20a27391f6dc 208 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 209 index count interrupt
hexley 0:20a27391f6dc 210 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 211 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 212 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 213 * @return New State of specified interrupt flag status (SET or RESET)
hexley 0:20a27391f6dc 214 */
hexley 0:20a27391f6dc 215 FlagStatus GetIntStatus( uint32_t ulIntType);
hexley 0:20a27391f6dc 216
hexley 0:20a27391f6dc 217 /** Enable/Disable specified interrupt in QEI peripheral
hexley 0:20a27391f6dc 218 *
hexley 0:20a27391f6dc 219 * @param[in] ulIntType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 220 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 221 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 222 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 223 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 224 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 225 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 226 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 227 * current position interrupt
hexley 0:20a27391f6dc 228 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 229 * current position interrupt
hexley 0:20a27391f6dc 230 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 231 * current position interrupt
hexley 0:20a27391f6dc 232 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 233 * index count interrupt
hexley 0:20a27391f6dc 234 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 235 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 236 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 237 * @param[in] NewState New function state, should be:
hexley 0:20a27391f6dc 238 * - DISABLE
hexley 0:20a27391f6dc 239 * - ENABLE
hexley 0:20a27391f6dc 240 * @return None
hexley 0:20a27391f6dc 241 */
hexley 0:20a27391f6dc 242 void IntCmd( uint32_t ulIntType, FunctionalState NewState);
hexley 0:20a27391f6dc 243
hexley 0:20a27391f6dc 244 /** Asserts specified interrupt in QEI peripheral
hexley 0:20a27391f6dc 245 *
hexley 0:20a27391f6dc 246 * @param[in] ulIntType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 247 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 248 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 249 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 250 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 251 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 252 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 253 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 254 current position interrupt
hexley 0:20a27391f6dc 255 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 256 current position interrupt
hexley 0:20a27391f6dc 257 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 258 current position interrupt
hexley 0:20a27391f6dc 259 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 260 index count interrupt
hexley 0:20a27391f6dc 261 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 262 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 263 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 264 * @return None
hexley 0:20a27391f6dc 265 */
hexley 0:20a27391f6dc 266 void IntSet( uint32_t ulIntType);
hexley 0:20a27391f6dc 267
hexley 0:20a27391f6dc 268 /** De-asserts specified interrupt (pending) in QEI peripheral
hexley 0:20a27391f6dc 269 *
hexley 0:20a27391f6dc 270 * @param[in] ulIntType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 271 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 272 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 273 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 274 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 275 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 276 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 277 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 278 current position interrupt
hexley 0:20a27391f6dc 279 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 280 current position interrupt
hexley 0:20a27391f6dc 281 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 282 current position interrupt
hexley 0:20a27391f6dc 283 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 284 index count interrupt
hexley 0:20a27391f6dc 285 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 286 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 287 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 288 * @return None
hexley 0:20a27391f6dc 289 */
hexley 0:20a27391f6dc 290 void IntClear( uint32_t ulIntType);
hexley 0:20a27391f6dc 291
hexley 0:20a27391f6dc 292 /** Append interrupt handler for specific QEI interrupt source
hexley 0:20a27391f6dc 293 *
hexley 0:20a27391f6dc 294 * @param[in] ulISRType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 295 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 296 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 297 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 298 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 299 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 300 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 301 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 302 * current position interrupt
hexley 0:20a27391f6dc 303 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 304 * current position interrupt
hexley 0:20a27391f6dc 305 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 306 * current position interrupt
hexley 0:20a27391f6dc 307 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 308 * index count interrupt
hexley 0:20a27391f6dc 309 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 310 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 311 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 312 *
hexley 0:20a27391f6dc 313 * @return none
hexley 0:20a27391f6dc 314 */
hexley 0:20a27391f6dc 315 void AppendISR(uint32_t ulISRType, void(*fptr)(void));
hexley 0:20a27391f6dc 316
hexley 0:20a27391f6dc 317 /** Unappend interrupt handler for specific QEI interrupt source
hexley 0:20a27391f6dc 318 *
hexley 0:20a27391f6dc 319 * @param[in] ulISRType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 320 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 321 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 322 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 323 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 324 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 325 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 326 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 327 * current position interrupt
hexley 0:20a27391f6dc 328 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 329 * current position interrupt
hexley 0:20a27391f6dc 330 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 331 * current position interrupt
hexley 0:20a27391f6dc 332 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 333 * index count interrupt
hexley 0:20a27391f6dc 334 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 335 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 336 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 337 *
hexley 0:20a27391f6dc 338 * @return none
hexley 0:20a27391f6dc 339 */
hexley 0:20a27391f6dc 340 void UnAppendISR(uint32_t ulISRType);
hexley 0:20a27391f6dc 341
hexley 0:20a27391f6dc 342
hexley 0:20a27391f6dc 343 /**
hexley 0:20a27391f6dc 344 * @brief Calculates the actual velocity in RPM passed via velocity
hexley 0:20a27391f6dc 345 * capture value and Pulse Per Revolution (of the encoder) value
hexley 0:20a27391f6dc 346 * parameter input.
hexley 0:20a27391f6dc 347 *
hexley 0:20a27391f6dc 348 * @param[in] ulVelCapValue Velocity capture input value that can
hexley 0:20a27391f6dc 349 * be got from QEI_GetVelocityCap() function
hexley 0:20a27391f6dc 350 * @param[in] ulPPR Pulse per round of encoder
hexley 0:20a27391f6dc 351 * @return The actual value of velocity in RPM (Revolutions per minute)
hexley 0:20a27391f6dc 352 */
hexley 0:20a27391f6dc 353 uint32_t CalculateRPM( uint32_t ulVelCapValue, uint32_t ulPPR);
hexley 0:20a27391f6dc 354
hexley 0:20a27391f6dc 355
hexley 0:20a27391f6dc 356 /* Public Macros -------------------------------------------------------------- */
hexley 0:20a27391f6dc 357 /* QEI Reset types */
hexley 0:20a27391f6dc 358 #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
hexley 0:20a27391f6dc 359 #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
hexley 0:20a27391f6dc 360 #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
hexley 0:20a27391f6dc 361 #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
hexley 0:20a27391f6dc 362
hexley 0:20a27391f6dc 363 /* QEI Direction Invert Type Option */
hexley 0:20a27391f6dc 364 #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
hexley 0:20a27391f6dc 365 #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
hexley 0:20a27391f6dc 366
hexley 0:20a27391f6dc 367 /* QEI Signal Mode Option */
hexley 0:20a27391f6dc 368 #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
hexley 0:20a27391f6dc 369 #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
hexley 0:20a27391f6dc 370
hexley 0:20a27391f6dc 371 /* QEI Capture Mode Option */
hexley 0:20a27391f6dc 372 #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
hexley 0:20a27391f6dc 373 #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
hexley 0:20a27391f6dc 374
hexley 0:20a27391f6dc 375 /* QEI Invert Index Signal Option */
hexley 0:20a27391f6dc 376 #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
hexley 0:20a27391f6dc 377 #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
hexley 0:20a27391f6dc 378
hexley 0:20a27391f6dc 379 /* QEI timer reload option */
hexley 0:20a27391f6dc 380 #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
hexley 0:20a27391f6dc 381 #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
hexley 0:20a27391f6dc 382
hexley 0:20a27391f6dc 383 /* QEI Flag Status type */
hexley 0:20a27391f6dc 384 #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
hexley 0:20a27391f6dc 385
hexley 0:20a27391f6dc 386 /* QEI Compare Position channel option */
hexley 0:20a27391f6dc 387 #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
hexley 0:20a27391f6dc 388 #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
hexley 0:20a27391f6dc 389 #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
hexley 0:20a27391f6dc 390
hexley 0:20a27391f6dc 391 /* QEI interrupt flag type */
hexley 0:20a27391f6dc 392 #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
hexley 0:20a27391f6dc 393 #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
hexley 0:20a27391f6dc 394 #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
hexley 0:20a27391f6dc 395 #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
hexley 0:20a27391f6dc 396 #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
hexley 0:20a27391f6dc 397 #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
hexley 0:20a27391f6dc 398 #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
hexley 0:20a27391f6dc 399 current position interrupt */
hexley 0:20a27391f6dc 400 #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
hexley 0:20a27391f6dc 401 current position interrupt */
hexley 0:20a27391f6dc 402 #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
hexley 0:20a27391f6dc 403 current position interrupt */
hexley 0:20a27391f6dc 404 #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
hexley 0:20a27391f6dc 405 index count interrupt */
hexley 0:20a27391f6dc 406 #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
hexley 0:20a27391f6dc 407 #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
hexley 0:20a27391f6dc 408 #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
hexley 0:20a27391f6dc 409
hexley 0:20a27391f6dc 410 /* QEI Process position reporting options */
hexley 0:20a27391f6dc 411 #define QEI_PROCESS_OPERATE 0;
hexley 0:20a27391f6dc 412 #define QEI_PROCESS_RESET 1;
hexley 0:20a27391f6dc 413 #define QEI_PROCESS_INCREMENTAL 0;
hexley 0:20a27391f6dc 414 #define QEI_PROCESS_ACCUMULATE 1;
hexley 0:20a27391f6dc 415 #define QEI_PROCESS_LINEAR 0;
hexley 0:20a27391f6dc 416 #define QEI_PROCESS_WEIGHTED 1;
hexley 0:20a27391f6dc 417
hexley 0:20a27391f6dc 418 private:
hexley 0:20a27391f6dc 419 static void _Qeiisr(void);
hexley 0:20a27391f6dc 420 void Qeiisr(void);
hexley 0:20a27391f6dc 421 static QEIHW *instance;
hexley 0:20a27391f6dc 422
hexley 0:20a27391f6dc 423 void(*_qei_isr[13])();
hexley 0:20a27391f6dc 424
hexley 0:20a27391f6dc 425
hexley 0:20a27391f6dc 426 /* Private Macros ------------------------------------------------------------- */
hexley 0:20a27391f6dc 427 /* --------------------- BIT DEFINITIONS -------------------------------------- */
hexley 0:20a27391f6dc 428 /* Quadrature Encoder Interface Control Register Definition --------------------- */
hexley 0:20a27391f6dc 429 /*********************************************************************//**
hexley 0:20a27391f6dc 430 * Macro defines for QEI Control register
hexley 0:20a27391f6dc 431 **********************************************************************/
hexley 0:20a27391f6dc 432 #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
hexley 0:20a27391f6dc 433 #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
hexley 0:20a27391f6dc 434 #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
hexley 0:20a27391f6dc 435 #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
hexley 0:20a27391f6dc 436 #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
hexley 0:20a27391f6dc 437
hexley 0:20a27391f6dc 438 /*********************************************************************//**
hexley 0:20a27391f6dc 439 * Macro defines for QEI Configuration register
hexley 0:20a27391f6dc 440 **********************************************************************/
hexley 0:20a27391f6dc 441 #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
hexley 0:20a27391f6dc 442 #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
hexley 0:20a27391f6dc 443 #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
hexley 0:20a27391f6dc 444 #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
hexley 0:20a27391f6dc 445 #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
hexley 0:20a27391f6dc 446
hexley 0:20a27391f6dc 447 /*********************************************************************//**
hexley 0:20a27391f6dc 448 * Macro defines for QEI Status register
hexley 0:20a27391f6dc 449 **********************************************************************/
hexley 0:20a27391f6dc 450 #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
hexley 0:20a27391f6dc 451 #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
hexley 0:20a27391f6dc 452
hexley 0:20a27391f6dc 453 /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
hexley 0:20a27391f6dc 454 /*********************************************************************//**
hexley 0:20a27391f6dc 455 * Macro defines for QEI Interrupt Status register
hexley 0:20a27391f6dc 456 **********************************************************************/
hexley 0:20a27391f6dc 457 #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
hexley 0:20a27391f6dc 458 #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
hexley 0:20a27391f6dc 459 #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
hexley 0:20a27391f6dc 460 #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
hexley 0:20a27391f6dc 461 #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
hexley 0:20a27391f6dc 462 #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
hexley 0:20a27391f6dc 463 #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
hexley 0:20a27391f6dc 464 current position */
hexley 0:20a27391f6dc 465 #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
hexley 0:20a27391f6dc 466 current position */
hexley 0:20a27391f6dc 467 #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
hexley 0:20a27391f6dc 468 current position */
hexley 0:20a27391f6dc 469 #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
hexley 0:20a27391f6dc 470 index count */
hexley 0:20a27391f6dc 471 #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
hexley 0:20a27391f6dc 472 both the POS0_Int bit is set and the REV_Int is set */
hexley 0:20a27391f6dc 473 #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
hexley 0:20a27391f6dc 474 both the POS1_Int bit is set and the REV_Int is set */
hexley 0:20a27391f6dc 475 #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
hexley 0:20a27391f6dc 476 both the POS2_Int bit is set and the REV_Int is set */
hexley 0:20a27391f6dc 477 #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
hexley 0:20a27391f6dc 478
hexley 0:20a27391f6dc 479 /*********************************************************************//**
hexley 0:20a27391f6dc 480 * Macro defines for QEI Interrupt Set register
hexley 0:20a27391f6dc 481 **********************************************************************/
hexley 0:20a27391f6dc 482 #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
hexley 0:20a27391f6dc 483 #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
hexley 0:20a27391f6dc 484 #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
hexley 0:20a27391f6dc 485 #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
hexley 0:20a27391f6dc 486 #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
hexley 0:20a27391f6dc 487 #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
hexley 0:20a27391f6dc 488 #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
hexley 0:20a27391f6dc 489 current position */
hexley 0:20a27391f6dc 490 #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
hexley 0:20a27391f6dc 491 current position */
hexley 0:20a27391f6dc 492 #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
hexley 0:20a27391f6dc 493 current position */
hexley 0:20a27391f6dc 494 #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
hexley 0:20a27391f6dc 495 index count */
hexley 0:20a27391f6dc 496 #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
hexley 0:20a27391f6dc 497 #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
hexley 0:20a27391f6dc 498 #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
hexley 0:20a27391f6dc 499 #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
hexley 0:20a27391f6dc 500
hexley 0:20a27391f6dc 501 /*********************************************************************//**
hexley 0:20a27391f6dc 502 * Macro defines for QEI Interrupt Clear register
hexley 0:20a27391f6dc 503 **********************************************************************/
hexley 0:20a27391f6dc 504 #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
hexley 0:20a27391f6dc 505 #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
hexley 0:20a27391f6dc 506 #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
hexley 0:20a27391f6dc 507 #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
hexley 0:20a27391f6dc 508 #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
hexley 0:20a27391f6dc 509 #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
hexley 0:20a27391f6dc 510 #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
hexley 0:20a27391f6dc 511 current position */
hexley 0:20a27391f6dc 512 #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
hexley 0:20a27391f6dc 513 current position */
hexley 0:20a27391f6dc 514 #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
hexley 0:20a27391f6dc 515 current position */
hexley 0:20a27391f6dc 516 #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
hexley 0:20a27391f6dc 517 index count */
hexley 0:20a27391f6dc 518 #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
hexley 0:20a27391f6dc 519 #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
hexley 0:20a27391f6dc 520 #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
hexley 0:20a27391f6dc 521 #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */
hexley 0:20a27391f6dc 522
hexley 0:20a27391f6dc 523 /*********************************************************************//**
hexley 0:20a27391f6dc 524 * Macro defines for QEI Interrupt Enable register
hexley 0:20a27391f6dc 525 **********************************************************************/
hexley 0:20a27391f6dc 526 #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
hexley 0:20a27391f6dc 527 #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
hexley 0:20a27391f6dc 528 #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
hexley 0:20a27391f6dc 529 #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
hexley 0:20a27391f6dc 530 #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
hexley 0:20a27391f6dc 531 #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
hexley 0:20a27391f6dc 532 #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
hexley 0:20a27391f6dc 533 current position */
hexley 0:20a27391f6dc 534 #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
hexley 0:20a27391f6dc 535 current position */
hexley 0:20a27391f6dc 536 #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
hexley 0:20a27391f6dc 537 current position */
hexley 0:20a27391f6dc 538 #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
hexley 0:20a27391f6dc 539 index count */
hexley 0:20a27391f6dc 540 #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
hexley 0:20a27391f6dc 541 #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
hexley 0:20a27391f6dc 542 #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
hexley 0:20a27391f6dc 543 #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
hexley 0:20a27391f6dc 544
hexley 0:20a27391f6dc 545 /*********************************************************************//**
hexley 0:20a27391f6dc 546 * Macro defines for QEI Interrupt Enable Set register
hexley 0:20a27391f6dc 547 **********************************************************************/
hexley 0:20a27391f6dc 548 #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
hexley 0:20a27391f6dc 549 #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
hexley 0:20a27391f6dc 550 #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
hexley 0:20a27391f6dc 551 #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
hexley 0:20a27391f6dc 552 #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
hexley 0:20a27391f6dc 553 #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
hexley 0:20a27391f6dc 554 #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
hexley 0:20a27391f6dc 555 current position */
hexley 0:20a27391f6dc 556 #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
hexley 0:20a27391f6dc 557 current position */
hexley 0:20a27391f6dc 558 #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
hexley 0:20a27391f6dc 559 current position */
hexley 0:20a27391f6dc 560 #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
hexley 0:20a27391f6dc 561 index count */
hexley 0:20a27391f6dc 562 #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
hexley 0:20a27391f6dc 563 #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
hexley 0:20a27391f6dc 564 #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
hexley 0:20a27391f6dc 565 #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
hexley 0:20a27391f6dc 566
hexley 0:20a27391f6dc 567 /*********************************************************************//**
hexley 0:20a27391f6dc 568 * Macro defines for QEI Interrupt Enable Clear register
hexley 0:20a27391f6dc 569 **********************************************************************/
hexley 0:20a27391f6dc 570 #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
hexley 0:20a27391f6dc 571 #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
hexley 0:20a27391f6dc 572 #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
hexley 0:20a27391f6dc 573 #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
hexley 0:20a27391f6dc 574 #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
hexley 0:20a27391f6dc 575 #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
hexley 0:20a27391f6dc 576 #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
hexley 0:20a27391f6dc 577 current position */
hexley 0:20a27391f6dc 578 #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
hexley 0:20a27391f6dc 579 current position */
hexley 0:20a27391f6dc 580 #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
hexley 0:20a27391f6dc 581 current position */
hexley 0:20a27391f6dc 582 #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
hexley 0:20a27391f6dc 583 index count */
hexley 0:20a27391f6dc 584 #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
hexley 0:20a27391f6dc 585 #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
hexley 0:20a27391f6dc 586 #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
hexley 0:20a27391f6dc 587 #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */
hexley 0:20a27391f6dc 588
hexley 0:20a27391f6dc 589 /*********************************************************************//**
hexley 0:20a27391f6dc 590 * Macro defines for PCONP register QEI-related bits
hexley 0:20a27391f6dc 591 **********************************************************************/
hexley 0:20a27391f6dc 592 #define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */
hexley 0:20a27391f6dc 593 #define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */
hexley 0:20a27391f6dc 594
hexley 0:20a27391f6dc 595 /*********************************************************************//**
hexley 0:20a27391f6dc 596 * Macro defines for PCLKSELx register QEI-related bits
hexley 0:20a27391f6dc 597 **********************************************************************/
hexley 0:20a27391f6dc 598 #define PCLKSEL_CCLK_DIV_1 1UL /**< Set PCLK to CCLK/1 */
hexley 0:20a27391f6dc 599 #define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */
hexley 0:20a27391f6dc 600 #define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */
hexley 0:20a27391f6dc 601 #define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */
hexley 0:20a27391f6dc 602 #define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */
hexley 0:20a27391f6dc 603 /*********************************************************************//**
hexley 0:20a27391f6dc 604 * Macro defines for PINSEL3 register QEI-related bits
hexley 0:20a27391f6dc 605 **********************************************************************/
hexley 0:20a27391f6dc 606 #define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */
hexley 0:20a27391f6dc 607 #define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */
hexley 0:20a27391f6dc 608 #define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */
hexley 0:20a27391f6dc 609 #define PINSEL3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI2 (PhB) pin mask */
hexley 0:20a27391f6dc 610 #define PINSEL3_MCI2 ((uint32_t)(1<<16)) /**< MCI2 (Index) pin select */
hexley 0:20a27391f6dc 611 #define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */
hexley 0:20a27391f6dc 612
hexley 0:20a27391f6dc 613 /*********************************************************************//**
hexley 0:20a27391f6dc 614 * Macro defines for PINMODE3 register QEI-related bits
hexley 0:20a27391f6dc 615 **********************************************************************/
hexley 0:20a27391f6dc 616 #define PIN_PULL_UP 0UL
hexley 0:20a27391f6dc 617 #define PIN_REPEATER 1UL
hexley 0:20a27391f6dc 618 #define PIN_NORESISTOR 2UL
hexley 0:20a27391f6dc 619 #define PIN_PULL_DOWN 3UL
hexley 0:20a27391f6dc 620
hexley 0:20a27391f6dc 621 #define PINMODE3_MCI0 ((uint32_t)(PIN_NORESISTOR<<8)) /**< MCIO (PhA) resistor selection */
hexley 0:20a27391f6dc 622 #define PINMODE3_GPIO1p20 ((uint32_t)(PIN_PULL_DOWN<<8)) /**< GPIO 1.20) resistor selection */
hexley 0:20a27391f6dc 623 #define PINMODE3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) resistor mask */
hexley 0:20a27391f6dc 624
hexley 0:20a27391f6dc 625 #define PINMODE3_MCI1 ((uint32_t)(PIN_NORESISTOR<<14)) /**< MCI1 (PhB) resistor selection */
hexley 0:20a27391f6dc 626 #define PINMODE3_GPIO1p23 ((uint32_t)(PIN_PULL_DOWN<<14)) /**< GPIO 1.23) resistor selection */
hexley 0:20a27391f6dc 627 #define PINMODE3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI1 (PhB) resistor mask */
hexley 0:20a27391f6dc 628
hexley 0:20a27391f6dc 629 #define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */
hexley 0:20a27391f6dc 630 #define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */
hexley 0:20a27391f6dc 631 #define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */
hexley 0:20a27391f6dc 632
hexley 0:20a27391f6dc 633 };
hexley 0:20a27391f6dc 634
hexley 0:20a27391f6dc 635
hexley 0:20a27391f6dc 636 #endif /* MBED_QEI_H */
hexley 0:20a27391f6dc 637 /* --------------------------------- End Of File ------------------------------ */