Knight KE / Mbed OS Game_Master

游戏王对战板，目前code还是空的

mbed-os/targets/TARGET_STM/sleep.c@0:9b3d4731edbb, 2018-06-21 (annotated)

Committer:
WFKnight
Date:
Thu Jun 21 13:51:43 2018 +0000
Revision:
0:9b3d4731edbb
UART, RTOS, LED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
WFKnight 0:9b3d4731edbb 1 /* mbed Microcontroller Library
WFKnight 0:9b3d4731edbb 2 *******************************************************************************
WFKnight 0:9b3d4731edbb 3 * Copyright (c) 2018, STMicroelectronics
WFKnight 0:9b3d4731edbb 4 * All rights reserved.
WFKnight 0:9b3d4731edbb 5 *
WFKnight 0:9b3d4731edbb 6 * Redistribution and use in source and binary forms, with or without
WFKnight 0:9b3d4731edbb 7 * modification, are permitted provided that the following conditions are met:
WFKnight 0:9b3d4731edbb 8 *
WFKnight 0:9b3d4731edbb 9 * 1. Redistributions of source code must retain the above copyright notice,
WFKnight 0:9b3d4731edbb 10 * this list of conditions and the following disclaimer.
WFKnight 0:9b3d4731edbb 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
WFKnight 0:9b3d4731edbb 12 * this list of conditions and the following disclaimer in the documentation
WFKnight 0:9b3d4731edbb 13 * and/or other materials provided with the distribution.
WFKnight 0:9b3d4731edbb 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
WFKnight 0:9b3d4731edbb 15 * may be used to endorse or promote products derived from this software
WFKnight 0:9b3d4731edbb 16 * without specific prior written permission.
WFKnight 0:9b3d4731edbb 17 *
WFKnight 0:9b3d4731edbb 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
WFKnight 0:9b3d4731edbb 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
WFKnight 0:9b3d4731edbb 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
WFKnight 0:9b3d4731edbb 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
WFKnight 0:9b3d4731edbb 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
WFKnight 0:9b3d4731edbb 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
WFKnight 0:9b3d4731edbb 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
WFKnight 0:9b3d4731edbb 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
WFKnight 0:9b3d4731edbb 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
WFKnight 0:9b3d4731edbb 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
WFKnight 0:9b3d4731edbb 28 *******************************************************************************
WFKnight 0:9b3d4731edbb 29 */
WFKnight 0:9b3d4731edbb 30 #if DEVICE_SLEEP
WFKnight 0:9b3d4731edbb 31
WFKnight 0:9b3d4731edbb 32 #include "sleep_api.h"
WFKnight 0:9b3d4731edbb 33 #include "us_ticker_api.h"
WFKnight 0:9b3d4731edbb 34 #include "hal_tick.h"
WFKnight 0:9b3d4731edbb 35 #include "mbed_critical.h"
WFKnight 0:9b3d4731edbb 36 #include "mbed_error.h"
WFKnight 0:9b3d4731edbb 37
WFKnight 0:9b3d4731edbb 38 extern void rtc_synchronize(void);
WFKnight 0:9b3d4731edbb 39
WFKnight 0:9b3d4731edbb 40 /* Wait loop - assuming tick is 1 us */
WFKnight 0:9b3d4731edbb 41 static void wait_loop(uint32_t timeout)
WFKnight 0:9b3d4731edbb 42 {
WFKnight 0:9b3d4731edbb 43 uint32_t t1, t2, elapsed = 0;
WFKnight 0:9b3d4731edbb 44 t1 = us_ticker_read();
WFKnight 0:9b3d4731edbb 45 do {
WFKnight 0:9b3d4731edbb 46 t2 = us_ticker_read();
WFKnight 0:9b3d4731edbb 47 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t)t2 + 0xFFFFFFFF - t1 + 1);
WFKnight 0:9b3d4731edbb 48 } while (elapsed < timeout);
WFKnight 0:9b3d4731edbb 49 return;
WFKnight 0:9b3d4731edbb 50 }
WFKnight 0:9b3d4731edbb 51
WFKnight 0:9b3d4731edbb 52
WFKnight 0:9b3d4731edbb 53 // On L4 platforms we've seen unstable PLL CLK configuraiton
WFKnight 0:9b3d4731edbb 54 // when DEEP SLEEP exits just few µs after being entered
WFKnight 0:9b3d4731edbb 55 // So we need to force MSI usage before setting clocks again
WFKnight 0:9b3d4731edbb 56 static void ForcePeriphOutofDeepSleep(void)
WFKnight 0:9b3d4731edbb 57 {
WFKnight 0:9b3d4731edbb 58 uint32_t pFLatency = 0;
WFKnight 0:9b3d4731edbb 59 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
WFKnight 0:9b3d4731edbb 60
WFKnight 0:9b3d4731edbb 61 #if (TARGET_STM32L4 || TARGET_STM32L1) /* MSI used for L4 */
WFKnight 0:9b3d4731edbb 62 /* Get the Clocks configuration according to the internal RCC registers */
WFKnight 0:9b3d4731edbb 63 HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
WFKnight 0:9b3d4731edbb 64
WFKnight 0:9b3d4731edbb 65 // Select HSI ss system clock source as a first step
WFKnight 0:9b3d4731edbb 66 #ifdef RCC_CLOCKTYPE_PCLK2
WFKnight 0:9b3d4731edbb 67 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
WFKnight 0:9b3d4731edbb 68 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
WFKnight 0:9b3d4731edbb 69 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
WFKnight 0:9b3d4731edbb 70 #else
WFKnight 0:9b3d4731edbb 71 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
WFKnight 0:9b3d4731edbb 72 | RCC_CLOCKTYPE_PCLK1);
WFKnight 0:9b3d4731edbb 73 #endif
WFKnight 0:9b3d4731edbb 74 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
WFKnight 0:9b3d4731edbb 75 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
WFKnight 0:9b3d4731edbb 76 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
WFKnight 0:9b3d4731edbb 77 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
WFKnight 0:9b3d4731edbb 78 error("clock issue\r\n");
WFKnight 0:9b3d4731edbb 79 }
WFKnight 0:9b3d4731edbb 80 #else /* HSI used on others */
WFKnight 0:9b3d4731edbb 81 /* Get the Clocks configuration according to the internal RCC registers */
WFKnight 0:9b3d4731edbb 82 HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
WFKnight 0:9b3d4731edbb 83
WFKnight 0:9b3d4731edbb 84 /**Initializes the CPU, AHB and APB busses clocks
WFKnight 0:9b3d4731edbb 85 */
WFKnight 0:9b3d4731edbb 86 #ifdef RCC_CLOCKTYPE_PCLK2
WFKnight 0:9b3d4731edbb 87 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
WFKnight 0:9b3d4731edbb 88 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2);
WFKnight 0:9b3d4731edbb 89 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
WFKnight 0:9b3d4731edbb 90 #else
WFKnight 0:9b3d4731edbb 91 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
WFKnight 0:9b3d4731edbb 92 |RCC_CLOCKTYPE_PCLK1);
WFKnight 0:9b3d4731edbb 93 #endif
WFKnight 0:9b3d4731edbb 94 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
WFKnight 0:9b3d4731edbb 95 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
WFKnight 0:9b3d4731edbb 96 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
WFKnight 0:9b3d4731edbb 97 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
WFKnight 0:9b3d4731edbb 98 error("clock issue");
WFKnight 0:9b3d4731edbb 99 }
WFKnight 0:9b3d4731edbb 100 #endif // TARGET_STM32L4
WFKnight 0:9b3d4731edbb 101 }
WFKnight 0:9b3d4731edbb 102
WFKnight 0:9b3d4731edbb 103 static void ForceOscOutofDeepSleep(void)
WFKnight 0:9b3d4731edbb 104 {
WFKnight 0:9b3d4731edbb 105 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
WFKnight 0:9b3d4731edbb 106
WFKnight 0:9b3d4731edbb 107 /* Enable Power Control clock */
WFKnight 0:9b3d4731edbb 108 __HAL_RCC_PWR_CLK_ENABLE();
WFKnight 0:9b3d4731edbb 109
WFKnight 0:9b3d4731edbb 110 /* Get the Oscillators configuration according to the internal RCC registers */
WFKnight 0:9b3d4731edbb 111 HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
WFKnight 0:9b3d4731edbb 112
WFKnight 0:9b3d4731edbb 113 #if (TARGET_STM32L4 || TARGET_STM32L1) /* MSI used for L4 */
WFKnight 0:9b3d4731edbb 114 /**Initializes the CPU, AHB and APB busses clocks
WFKnight 0:9b3d4731edbb 115 */
WFKnight 0:9b3d4731edbb 116 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
WFKnight 0:9b3d4731edbb 117 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
WFKnight 0:9b3d4731edbb 118 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
WFKnight 0:9b3d4731edbb 119 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4; // Intermediate freq, 1MHz range
WFKnight 0:9b3d4731edbb 120 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
WFKnight 0:9b3d4731edbb 121 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
WFKnight 0:9b3d4731edbb 122 error("clock issue\r\n");
WFKnight 0:9b3d4731edbb 123 }
WFKnight 0:9b3d4731edbb 124 #else /* HSI used on others */
WFKnight 0:9b3d4731edbb 125 /**Initializes the CPU, AHB and APB busses clocks
WFKnight 0:9b3d4731edbb 126 */
WFKnight 0:9b3d4731edbb 127 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
WFKnight 0:9b3d4731edbb 128 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
WFKnight 0:9b3d4731edbb 129 RCC_OscInitStruct.HSICalibrationValue = 16;
WFKnight 0:9b3d4731edbb 130 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
WFKnight 0:9b3d4731edbb 131 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
WFKnight 0:9b3d4731edbb 132 error("clock issue");
WFKnight 0:9b3d4731edbb 133 }
WFKnight 0:9b3d4731edbb 134 #endif // TARGET_STM32L4
WFKnight 0:9b3d4731edbb 135 }
WFKnight 0:9b3d4731edbb 136
WFKnight 0:9b3d4731edbb 137 /* The content of this function has been split into 2 separate functions
WFKnight 0:9b3d4731edbb 138 so that the involved structures are not allocated on the stack in parallel.
WFKnight 0:9b3d4731edbb 139 This will reduce the maximum stack usage in case on non-optimized / debug
WFKnight 0:9b3d4731edbb 140 compilers settings */
WFKnight 0:9b3d4731edbb 141 static void ForceClockOutofDeepSleep(void)
WFKnight 0:9b3d4731edbb 142 {
WFKnight 0:9b3d4731edbb 143 ForceOscOutofDeepSleep();
WFKnight 0:9b3d4731edbb 144 ForcePeriphOutofDeepSleep();
WFKnight 0:9b3d4731edbb 145 }
WFKnight 0:9b3d4731edbb 146
WFKnight 0:9b3d4731edbb 147 void hal_sleep(void)
WFKnight 0:9b3d4731edbb 148 {
WFKnight 0:9b3d4731edbb 149 // Disable IRQs
WFKnight 0:9b3d4731edbb 150 core_util_critical_section_enter();
WFKnight 0:9b3d4731edbb 151
WFKnight 0:9b3d4731edbb 152 // Request to enter SLEEP mode
WFKnight 0:9b3d4731edbb 153 HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
WFKnight 0:9b3d4731edbb 154
WFKnight 0:9b3d4731edbb 155 // Enable IRQs
WFKnight 0:9b3d4731edbb 156 core_util_critical_section_exit();
WFKnight 0:9b3d4731edbb 157 }
WFKnight 0:9b3d4731edbb 158
WFKnight 0:9b3d4731edbb 159 void hal_deepsleep(void)
WFKnight 0:9b3d4731edbb 160 {
WFKnight 0:9b3d4731edbb 161 // Disable IRQs
WFKnight 0:9b3d4731edbb 162 core_util_critical_section_enter();
WFKnight 0:9b3d4731edbb 163
WFKnight 0:9b3d4731edbb 164 uint32_t EnterTimeUS = us_ticker_read();
WFKnight 0:9b3d4731edbb 165
WFKnight 0:9b3d4731edbb 166 // Request to enter STOP mode with regulator in low power mode
WFKnight 0:9b3d4731edbb 167 #if TARGET_STM32L4
WFKnight 0:9b3d4731edbb 168 int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
WFKnight 0:9b3d4731edbb 169 int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
WFKnight 0:9b3d4731edbb 170
WFKnight 0:9b3d4731edbb 171 if (!pwrClockEnabled) {
WFKnight 0:9b3d4731edbb 172 __HAL_RCC_PWR_CLK_ENABLE();
WFKnight 0:9b3d4731edbb 173 }
WFKnight 0:9b3d4731edbb 174 if (lowPowerModeEnabled) {
WFKnight 0:9b3d4731edbb 175 HAL_PWREx_DisableLowPowerRunMode();
WFKnight 0:9b3d4731edbb 176 }
WFKnight 0:9b3d4731edbb 177
WFKnight 0:9b3d4731edbb 178 HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
WFKnight 0:9b3d4731edbb 179
WFKnight 0:9b3d4731edbb 180 if (lowPowerModeEnabled) {
WFKnight 0:9b3d4731edbb 181 HAL_PWREx_EnableLowPowerRunMode();
WFKnight 0:9b3d4731edbb 182 }
WFKnight 0:9b3d4731edbb 183 if (!pwrClockEnabled) {
WFKnight 0:9b3d4731edbb 184 __HAL_RCC_PWR_CLK_DISABLE();
WFKnight 0:9b3d4731edbb 185 }
WFKnight 0:9b3d4731edbb 186 #else /* TARGET_STM32L4 */
WFKnight 0:9b3d4731edbb 187 HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
WFKnight 0:9b3d4731edbb 188 #endif /* TARGET_STM32L4 */
WFKnight 0:9b3d4731edbb 189 // Verify Clock Out of Deep Sleep
WFKnight 0:9b3d4731edbb 190 ForceClockOutofDeepSleep();
WFKnight 0:9b3d4731edbb 191
WFKnight 0:9b3d4731edbb 192 // After wake-up from STOP reconfigure the PLL
WFKnight 0:9b3d4731edbb 193 SetSysClock();
WFKnight 0:9b3d4731edbb 194
WFKnight 0:9b3d4731edbb 195 /* Wait for clock to be stabilized.
WFKnight 0:9b3d4731edbb 196 * TO DO: a better way of doing this, would be to rely on
WFKnight 0:9b3d4731edbb 197 * HW Flag. At least this ensures proper operation out of
WFKnight 0:9b3d4731edbb 198 * deep sleep */
WFKnight 0:9b3d4731edbb 199 wait_loop(500);
WFKnight 0:9b3d4731edbb 200
WFKnight 0:9b3d4731edbb 201 TIM_HandleTypeDef TimMasterHandle;
WFKnight 0:9b3d4731edbb 202 TimMasterHandle.Instance = TIM_MST;
WFKnight 0:9b3d4731edbb 203 __HAL_TIM_SET_COUNTER(&TimMasterHandle, EnterTimeUS);
WFKnight 0:9b3d4731edbb 204
WFKnight 0:9b3d4731edbb 205 #if DEVICE_RTC
WFKnight 0:9b3d4731edbb 206 /* Wait for RTC RSF bit synchro if RTC is configured */
WFKnight 0:9b3d4731edbb 207 #if (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7)
WFKnight 0:9b3d4731edbb 208 if (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) {
WFKnight 0:9b3d4731edbb 209 #else /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */
WFKnight 0:9b3d4731edbb 210 if (__HAL_RCC_GET_RTC_SOURCE()) {
WFKnight 0:9b3d4731edbb 211 #endif /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */
WFKnight 0:9b3d4731edbb 212 rtc_synchronize();
WFKnight 0:9b3d4731edbb 213 }
WFKnight 0:9b3d4731edbb 214 #endif
WFKnight 0:9b3d4731edbb 215 // Enable IRQs
WFKnight 0:9b3d4731edbb 216 core_util_critical_section_exit();
WFKnight 0:9b3d4731edbb 217 }
WFKnight 0:9b3d4731edbb 218
WFKnight 0:9b3d4731edbb 219 #endif