Vesrion IAP with LPC11U24_EEPROM_ONLY options

Fork of IAP by Tedd OKANO

This is IAP library from http://mbed.org/users/okano/notebook/iap-in-application-programming-internal-flash-eras/ Added option LPC11U24_EEPROM_ONLY in IAP.h that disable flash write/read functions if they not needed and working only EEPROM write/read functions. It make for clear memory allocation for flash write functions (4k).

Committer:
Verbix
Date:
Sat Dec 28 21:01:05 2013 +0000
Revision:
2:0c7ec806673e
Parent:
1:ff906ad52cf9
Added option LPC11U24_EEPROM_ONLY disabling Flash write/read functions and RAM allocation for it. Only EEPROM functions for LPC11U24 will work.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
okano 0:ada7fb504504 1 /** IAP : internal Flash memory access library
okano 0:ada7fb504504 2 *
okano 0:ada7fb504504 3 * The internal Flash memory access is described in the LPC1768 and LPC11U24 usermanual.
okano 0:ada7fb504504 4 * http://www.nxp.com/documents/user_manual/UM10360.pdf
okano 0:ada7fb504504 5 * http://www.nxp.com/documents/user_manual/UM10462.pdf
okano 0:ada7fb504504 6 *
okano 0:ada7fb504504 7 * LPC1768 --
okano 0:ada7fb504504 8 * Chapter 2: "LPC17xx Memory map"
okano 0:ada7fb504504 9 * Chapter 32: "LPC17xx Flash memory interface and programming"
okano 0:ada7fb504504 10 * refering Rev. 01 - 4 January 2010
okano 0:ada7fb504504 11 *
okano 0:ada7fb504504 12 * LPC11U24 --
okano 0:ada7fb504504 13 * Chapter 2: "LPC11Uxx Memory mapping"
okano 0:ada7fb504504 14 * Chapter 20: "LPC11Uxx Flash programming firmware"
okano 0:ada7fb504504 15 * refering Rev. 03 - 16 July 2012
okano 0:ada7fb504504 16 *
okano 0:ada7fb504504 17 * Released under the MIT License: http://mbed.org/license/mit
okano 0:ada7fb504504 18 *
okano 0:ada7fb504504 19 * revision 1.0 09-Mar-2010 1st release
okano 0:ada7fb504504 20 * revision 1.1 12-Mar-2010 chaged: to make possible to reserve flash area for user
okano 0:ada7fb504504 21 * it can be set by USER_FLASH_AREA_START and USER_FLASH_AREA_SIZE in IAP.h
okano 1:ff906ad52cf9 22 * revision 2.0 26-Nov-2012 LPC11U24 code added
okano 1:ff906ad52cf9 23 * revision 2.1 26-Nov-2012 EEPROM access code imported from Suga koubou san's (http://mbed.org/users/okini3939/) library
okano 1:ff906ad52cf9 24 * http://mbed.org/users/okini3939/code/M0_EEPROM_test/
okano 0:ada7fb504504 25 */
okano 0:ada7fb504504 26
okano 0:ada7fb504504 27 #include "mbed.h"
okano 0:ada7fb504504 28 #include "IAP.h"
okano 0:ada7fb504504 29
okano 0:ada7fb504504 30 #define USER_FLASH_AREA_START_STR( x ) STR( x )
okano 0:ada7fb504504 31 #define STR( x ) #x
okano 0:ada7fb504504 32
Verbix 2:0c7ec806673e 33 #ifndef LPC11U24_EEPROM_ONLY
okano 0:ada7fb504504 34 unsigned char user_area[ USER_FLASH_AREA_SIZE ] __attribute__((section( ".ARM.__at_" USER_FLASH_AREA_START_STR( USER_FLASH_AREA_START ) ), zero_init));
Verbix 2:0c7ec806673e 35 #endif
okano 0:ada7fb504504 36
okano 0:ada7fb504504 37 /*
okano 0:ada7fb504504 38 * Reserve of flash area is explained by Igor. Please refer next URL
okano 0:ada7fb504504 39 * http://mbed.org/users/okano/notebook/iap-in-application-programming-internal-flash-eras/?page=1#comment-271
okano 0:ada7fb504504 40 */
okano 0:ada7fb504504 41
okano 0:ada7fb504504 42 //unsigned char user_area[ size ] __attribute__((section(".ARM.__at_0x78000"), zero_init));
okano 0:ada7fb504504 43
okano 0:ada7fb504504 44 /*
okano 0:ada7fb504504 45 * IAP command codes
okano 0:ada7fb504504 46 * Table 589. "IAP Command Summary", Chapter 8. "IAP commands", usermanual
okano 0:ada7fb504504 47 */
okano 0:ada7fb504504 48
okano 0:ada7fb504504 49 enum command_code
okano 0:ada7fb504504 50 {
okano 0:ada7fb504504 51 IAPCommand_Prepare_sector_for_write_operation = 50,
okano 0:ada7fb504504 52 IAPCommand_Copy_RAM_to_Flash,
okano 0:ada7fb504504 53 IAPCommand_Erase_sector,
okano 0:ada7fb504504 54 IAPCommand_Blank_check_sector,
okano 0:ada7fb504504 55 IAPCommand_Read_part_ID,
okano 0:ada7fb504504 56 IAPCommand_Read_Boot_Code_version,
okano 0:ada7fb504504 57 IAPCommand_Compare,
okano 0:ada7fb504504 58 IAPCommand_Reinvoke_ISP,
okano 1:ff906ad52cf9 59 IAPCommand_Read_device_serial_number,
okano 1:ff906ad52cf9 60 #if defined(TARGET_LPC11U24)
okano 1:ff906ad52cf9 61 IAPCommand_EEPROM_Write = 61,
okano 1:ff906ad52cf9 62 IAPCommand_EEPROM_Read,
okano 1:ff906ad52cf9 63 #endif
okano 0:ada7fb504504 64 };
okano 0:ada7fb504504 65
okano 0:ada7fb504504 66
okano 0:ada7fb504504 67 /** Read part identification number
okano 0:ada7fb504504 68 *
okano 0:ada7fb504504 69 * @return device ID
okano 0:ada7fb504504 70 * @see read_serial()
okano 0:ada7fb504504 71 */
okano 0:ada7fb504504 72
okano 0:ada7fb504504 73 int IAP::read_ID( void ) {
okano 0:ada7fb504504 74 IAP_command[ 0 ] = IAPCommand_Read_part_ID;
okano 0:ada7fb504504 75
okano 0:ada7fb504504 76 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 77
okano 0:ada7fb504504 78 // return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 79 return ( (int)IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS)
okano 0:ada7fb504504 80 }
okano 0:ada7fb504504 81
okano 0:ada7fb504504 82
okano 0:ada7fb504504 83 /** Read device serial number
okano 0:ada7fb504504 84 *
okano 0:ada7fb504504 85 * @return device serial number
okano 0:ada7fb504504 86 * @see read_ID()
okano 0:ada7fb504504 87 */
okano 0:ada7fb504504 88
okano 0:ada7fb504504 89 int IAP::read_serial( void ) {
okano 0:ada7fb504504 90 IAP_command[ 0 ] = IAPCommand_Read_device_serial_number;
okano 0:ada7fb504504 91
okano 0:ada7fb504504 92 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 93
okano 0:ada7fb504504 94 // return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 95 return ( (int)IAP_result[ 1 ] ); // to return the number itself (this command always returns CMD_SUCCESS)
okano 0:ada7fb504504 96 }
okano 0:ada7fb504504 97
okano 0:ada7fb504504 98
okano 0:ada7fb504504 99 /** Blank check sector(s)
okano 0:ada7fb504504 100 *
okano 0:ada7fb504504 101 * @param start a Start Sector Number
okano 0:ada7fb504504 102 * @param end an End Sector Number (should be greater than or equal to start sector number).
okano 0:ada7fb504504 103 * @return error code: CMD_SUCCESS | BUSY | SECTOR_NOT_BLANK | INVALID_SECTOR
okano 0:ada7fb504504 104 */
okano 0:ada7fb504504 105
Verbix 2:0c7ec806673e 106 #ifndef LPC11U24_EEPROM_ONLY
okano 0:ada7fb504504 107 int IAP::blank_check( int start, int end ) {
okano 0:ada7fb504504 108 IAP_command[ 0 ] = IAPCommand_Blank_check_sector;
okano 0:ada7fb504504 109 IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number
okano 0:ada7fb504504 110 IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number)
okano 0:ada7fb504504 111
okano 0:ada7fb504504 112 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 113
okano 0:ada7fb504504 114 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 115 }
okano 0:ada7fb504504 116
okano 0:ada7fb504504 117
okano 0:ada7fb504504 118 /** Erase Sector(s)
okano 0:ada7fb504504 119 *
okano 0:ada7fb504504 120 * @param start a Start Sector Number
okano 0:ada7fb504504 121 * @param end an End Sector Number (should be greater than or equal to start sector number).
okano 0:ada7fb504504 122 * @return error code: CMD_SUCCESS | BUSY | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | INVALID_SECTOR
okano 0:ada7fb504504 123 */
okano 0:ada7fb504504 124
okano 0:ada7fb504504 125 int IAP::erase( int start, int end ) {
okano 0:ada7fb504504 126 IAP_command[ 0 ] = IAPCommand_Erase_sector;
okano 0:ada7fb504504 127 IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number
okano 0:ada7fb504504 128 IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number)
okano 0:ada7fb504504 129 IAP_command[ 3 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz
okano 0:ada7fb504504 130
okano 0:ada7fb504504 131 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 132
okano 0:ada7fb504504 133 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 134 }
okano 0:ada7fb504504 135
okano 0:ada7fb504504 136
okano 0:ada7fb504504 137 /** Prepare sector(s) for write operation
okano 0:ada7fb504504 138 *
okano 0:ada7fb504504 139 * @param start a Start Sector Number
okano 0:ada7fb504504 140 * @param end an End Sector Number (should be greater than or equal to start sector number).
okano 0:ada7fb504504 141 * @return error code: CMD_SUCCESS | BUSY | INVALID_SECTOR
okano 0:ada7fb504504 142 */
okano 0:ada7fb504504 143
okano 0:ada7fb504504 144 int IAP::prepare( int start, int end ) {
okano 0:ada7fb504504 145 IAP_command[ 0 ] = IAPCommand_Prepare_sector_for_write_operation;
okano 0:ada7fb504504 146 IAP_command[ 1 ] = (unsigned int)start; // Start Sector Number
okano 0:ada7fb504504 147 IAP_command[ 2 ] = (unsigned int)end; // End Sector Number (should be greater than or equal to start sector number).
okano 0:ada7fb504504 148
okano 0:ada7fb504504 149 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 150
okano 0:ada7fb504504 151 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 152 }
okano 0:ada7fb504504 153
okano 0:ada7fb504504 154
okano 0:ada7fb504504 155 /** Copy RAM to Flash
okano 0:ada7fb504504 156 *
okano 0:ada7fb504504 157 * @param source_addr Source RAM address from which data bytes are to be read. This address should be a word boundary.
okano 0:ada7fb504504 158 * @param target_addr Destination flash address where data bytes are to be written. This address should be a 256 byte boundary.
okano 0:ada7fb504504 159 * @param size Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
okano 0:ada7fb504504 160 * @return error code: CMD_SUCCESS | SRC_ADDR_ERROR (Address not a word boundary) | DST_ADDR_ERROR (Address not on correct boundary) | SRC_ADDR_NOT_MAPPED | DST_ADDR_NOT_MAPPED | COUNT_ERROR (Byte count is not 256 | 512 | 1024 | 4096) | SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION | BUSY
okano 0:ada7fb504504 161 */
okano 0:ada7fb504504 162
okano 0:ada7fb504504 163 int IAP::write( char *source_addr, char *target_addr, int size ) {
okano 0:ada7fb504504 164 IAP_command[ 0 ] = IAPCommand_Copy_RAM_to_Flash;
okano 0:ada7fb504504 165 IAP_command[ 1 ] = (unsigned int)target_addr; // Destination flash address where data bytes are to be written. This address should be a 256 byte boundary.
okano 0:ada7fb504504 166 IAP_command[ 2 ] = (unsigned int)source_addr; // Source RAM address from which data bytes are to be read. This address should be a word boundary.
okano 0:ada7fb504504 167 IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
okano 0:ada7fb504504 168 IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz.
okano 0:ada7fb504504 169
okano 0:ada7fb504504 170 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 171
okano 0:ada7fb504504 172 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 173 }
okano 0:ada7fb504504 174
okano 0:ada7fb504504 175
okano 0:ada7fb504504 176 /** Compare <address1> <address2> <no of bytes>
okano 0:ada7fb504504 177 *
okano 0:ada7fb504504 178 * @param source_addr Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
okano 0:ada7fb504504 179 * @param target_addr Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
okano 0:ada7fb504504 180 * @param size Number of bytes to be compared; should be a multiple of 4.
okano 0:ada7fb504504 181 * @return error code: CMD_SUCCESS | COMPARE_ERROR | COUNT_ERROR (Byte count is not a multiple of 4) | ADDR_ERROR | ADDR_NOT_MAPPED
okano 0:ada7fb504504 182 */
okano 0:ada7fb504504 183
okano 0:ada7fb504504 184 int IAP::compare( char *source_addr, char *target_addr, int size ) {
okano 0:ada7fb504504 185 IAP_command[ 0 ] = IAPCommand_Compare;
okano 0:ada7fb504504 186 IAP_command[ 1 ] = (unsigned int)target_addr; // Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
okano 0:ada7fb504504 187 IAP_command[ 2 ] = (unsigned int)source_addr; // Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
okano 0:ada7fb504504 188 IAP_command[ 3 ] = size; // Number of bytes to be compared; should be a multiple of 4.
okano 0:ada7fb504504 189
okano 0:ada7fb504504 190 iap_entry( IAP_command, IAP_result );
okano 0:ada7fb504504 191
okano 0:ada7fb504504 192 return ( (int)IAP_result[ 0 ] );
okano 0:ada7fb504504 193 }
okano 0:ada7fb504504 194
okano 0:ada7fb504504 195 /** Compare <address1> <address2> <no of bytes>
okano 0:ada7fb504504 196 *
okano 0:ada7fb504504 197 * @param source_addr Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
okano 0:ada7fb504504 198 * @param target_addr Starting flash or RAM address of data bytes to be compared. This address should be a word boundary.
okano 0:ada7fb504504 199 * @param size Number of bytes to be compared; should be a multiple of 4.
okano 0:ada7fb504504 200 * @return error code: CMD_SUCCESS | COMPARE_ERROR | COUNT_ERROR (Byte count is not a multiple of 4) | ADDR_ERROR | ADDR_NOT_MAPPED
okano 0:ada7fb504504 201 */
okano 0:ada7fb504504 202
okano 0:ada7fb504504 203 int IAP::read_BootVer(void) {
okano 0:ada7fb504504 204 IAP_command[0] = IAPCommand_Read_Boot_Code_version;
okano 0:ada7fb504504 205 IAP_result[1] = 0; // not sure if in high or low bits.
okano 0:ada7fb504504 206 iap_entry(IAP_command, IAP_result);
okano 0:ada7fb504504 207 return ((int)IAP_result[1]);
okano 0:ada7fb504504 208 }
okano 0:ada7fb504504 209
okano 0:ada7fb504504 210 /** Get user reserved flash start address
okano 0:ada7fb504504 211 *
okano 0:ada7fb504504 212 * @return start address of user reserved flash memory
okano 0:ada7fb504504 213 * @see reserved_flash_area_size()
okano 0:ada7fb504504 214 */
okano 0:ada7fb504504 215
okano 0:ada7fb504504 216 char * IAP::reserved_flash_area_start( void )
okano 0:ada7fb504504 217 {
okano 0:ada7fb504504 218 return ( (char *)USER_FLASH_AREA_START );
okano 0:ada7fb504504 219 }
okano 0:ada7fb504504 220
okano 0:ada7fb504504 221
okano 0:ada7fb504504 222 /** Get user reserved flash size
okano 0:ada7fb504504 223 *
okano 0:ada7fb504504 224 * @return size of user reserved flash memory
okano 0:ada7fb504504 225 * @see reserved_flash_area_start()
okano 0:ada7fb504504 226 */
okano 0:ada7fb504504 227
okano 0:ada7fb504504 228 int IAP::reserved_flash_area_size( void )
okano 0:ada7fb504504 229 {
okano 0:ada7fb504504 230 return ( USER_FLASH_AREA_SIZE );
okano 0:ada7fb504504 231 }
Verbix 2:0c7ec806673e 232 #endif
okano 0:ada7fb504504 233
okano 1:ff906ad52cf9 234 #if defined(TARGET_LPC11U24)
okano 1:ff906ad52cf9 235 /** Copy RAM to EEPROM (LPC11U24)
okano 1:ff906ad52cf9 236 *
okano 1:ff906ad52cf9 237 * @param source_addr Source RAM address from which data bytes are to be read.
okano 1:ff906ad52cf9 238 * @param target_addr Destination EEPROM address where data bytes are to be written.
okano 1:ff906ad52cf9 239 * @param size Number of bytes to be written.
okano 1:ff906ad52cf9 240 * @return error code: CMD_SUCCESS | SRC_ADDR_NOT_MAPPED | DST_ADDR_NOT_MAPPED
okano 1:ff906ad52cf9 241 * Remark: The top 64 bytes of the EEPROM memory are reserved and cannot be written to.
okano 1:ff906ad52cf9 242 */
okano 1:ff906ad52cf9 243 int IAP::write_eeprom( char *source_addr, char *target_addr, int size ) {
okano 1:ff906ad52cf9 244 IAP_command[ 0 ] = IAPCommand_EEPROM_Write;
okano 1:ff906ad52cf9 245 IAP_command[ 1 ] = (unsigned int)target_addr; // Destination EEPROM address where data bytes are to be written. This address should be a 256 byte boundary.
okano 1:ff906ad52cf9 246 IAP_command[ 2 ] = (unsigned int)source_addr; // Source RAM address from which data bytes are to be read. This address should be a word boundary.
okano 1:ff906ad52cf9 247 IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
okano 1:ff906ad52cf9 248 IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz.
okano 1:ff906ad52cf9 249
okano 1:ff906ad52cf9 250 iap_entry( IAP_command, IAP_result );
okano 1:ff906ad52cf9 251
okano 1:ff906ad52cf9 252 return ( (int)IAP_result[ 0 ] );
okano 1:ff906ad52cf9 253 }
okano 1:ff906ad52cf9 254
okano 1:ff906ad52cf9 255 /** Copy EEPROM to RAM (LPC11U24)
okano 1:ff906ad52cf9 256 *
okano 1:ff906ad52cf9 257 * @param source_addr Source EEPROM address from which data bytes are to be read.
okano 1:ff906ad52cf9 258 * @param target_addr Destination RAM address where data bytes are to be written.
okano 1:ff906ad52cf9 259 * @param size Number of bytes to be written.
okano 1:ff906ad52cf9 260 * @return error code: CMD_SUCCESS | SRC_ADDR_NOT_MAPPED | DST_ADDR_NOT_MAPPED
okano 1:ff906ad52cf9 261 * Remark: The top 64 bytes of the EEPROM memory are reserved and cannot be written to.
okano 1:ff906ad52cf9 262 */
okano 1:ff906ad52cf9 263 int IAP::read_eeprom( char *source_addr, char *target_addr, int size ) {
okano 1:ff906ad52cf9 264 IAP_command[ 0 ] = IAPCommand_EEPROM_Read;
okano 1:ff906ad52cf9 265 IAP_command[ 1 ] = (unsigned int)source_addr; // Source EEPROM address from which data bytes are to be read. This address should be a word boundary.
okano 1:ff906ad52cf9 266 IAP_command[ 2 ] = (unsigned int)target_addr; // Destination RAM address where data bytes are to be written. This address should be a 256 byte boundary.
okano 1:ff906ad52cf9 267 IAP_command[ 3 ] = size; // Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
okano 1:ff906ad52cf9 268 IAP_command[ 4 ] = cclk_kHz; // CPU Clock Frequency (CCLK) in kHz.
okano 1:ff906ad52cf9 269
okano 1:ff906ad52cf9 270 iap_entry( IAP_command, IAP_result );
okano 1:ff906ad52cf9 271
okano 1:ff906ad52cf9 272 return ( (int)IAP_result[ 0 ] );
okano 1:ff906ad52cf9 273 }
okano 1:ff906ad52cf9 274 #endif