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targets/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c@174:b96e65c34a4d, 2017-10-02 (annotated)
- Committer:
- AnnaBridge
- Date:
- Mon Oct 02 15:33:19 2017 +0100
- Revision:
- 174:b96e65c34a4d
- Parent:
- 151:5eaa88a5bcc7
- Child:
- 181:96ed750bd169
This updates the lib to the mbed lib v 152
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| <> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
| <> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
| <> | 144:ef7eb2e8f9f7 | 3 | * |
| <> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| <> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
| <> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
| <> | 144:ef7eb2e8f9f7 | 7 | * |
| <> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| <> | 144:ef7eb2e8f9f7 | 9 | * |
| <> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
| <> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| <> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| <> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
| <> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
| <> | 144:ef7eb2e8f9f7 | 15 | */ |
| <> | 144:ef7eb2e8f9f7 | 16 | #include <stddef.h> |
| <> | 144:ef7eb2e8f9f7 | 17 | #include "us_ticker_api.h" |
| <> | 144:ef7eb2e8f9f7 | 18 | #include "PeripheralNames.h" |
| <> | 144:ef7eb2e8f9f7 | 19 | #include "ostm_iodefine.h" |
| <> | 144:ef7eb2e8f9f7 | 20 | |
| <> | 144:ef7eb2e8f9f7 | 21 | #include "RZ_A1_Init.h" |
| <> | 144:ef7eb2e8f9f7 | 22 | #include "MBRZA1H.h" |
| <> | 151:5eaa88a5bcc7 | 23 | #include "vfp_neon_push_pop.h" |
| <> | 144:ef7eb2e8f9f7 | 24 | |
| <> | 144:ef7eb2e8f9f7 | 25 | #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn) |
| <> | 144:ef7eb2e8f9f7 | 26 | #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ |
| <> | 144:ef7eb2e8f9f7 | 27 | |
| <> | 144:ef7eb2e8f9f7 | 28 | #define US_TICKER_CLOCK_US_DEV (1000000) |
| <> | 144:ef7eb2e8f9f7 | 29 | |
| <> | 144:ef7eb2e8f9f7 | 30 | int us_ticker_inited = 0; |
| <> | 144:ef7eb2e8f9f7 | 31 | static double count_clock = 0; |
| <> | 144:ef7eb2e8f9f7 | 32 | static uint32_t last_read = 0; |
| <> | 144:ef7eb2e8f9f7 | 33 | static uint32_t wrap_arround = 0; |
| <> | 144:ef7eb2e8f9f7 | 34 | static uint64_t ticker_us_last64 = 0; |
| <> | 151:5eaa88a5bcc7 | 35 | static uint64_t set_cmp_val64 = 0; |
| <> | 151:5eaa88a5bcc7 | 36 | static uint64_t timestamp64 = 0; |
| <> | 144:ef7eb2e8f9f7 | 37 | |
| <> | 144:ef7eb2e8f9f7 | 38 | void us_ticker_interrupt(void) { |
| <> | 144:ef7eb2e8f9f7 | 39 | us_ticker_irq_handler(); |
| <> | 144:ef7eb2e8f9f7 | 40 | } |
| <> | 144:ef7eb2e8f9f7 | 41 | |
| <> | 144:ef7eb2e8f9f7 | 42 | void us_ticker_init(void) { |
| <> | 144:ef7eb2e8f9f7 | 43 | if (us_ticker_inited) return; |
| <> | 144:ef7eb2e8f9f7 | 44 | us_ticker_inited = 1; |
| <> | 144:ef7eb2e8f9f7 | 45 | |
| <> | 144:ef7eb2e8f9f7 | 46 | /* set Counter Clock(us) */ |
| <> | 144:ef7eb2e8f9f7 | 47 | if (false == RZ_A1_IsClockMode0()) { |
| <> | 144:ef7eb2e8f9f7 | 48 | count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); |
| <> | 144:ef7eb2e8f9f7 | 49 | } else { |
| <> | 144:ef7eb2e8f9f7 | 50 | count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); |
| <> | 144:ef7eb2e8f9f7 | 51 | } |
| <> | 144:ef7eb2e8f9f7 | 52 | |
| <> | 144:ef7eb2e8f9f7 | 53 | /* Power Control for Peripherals */ |
| <> | 144:ef7eb2e8f9f7 | 54 | CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */ |
| <> | 144:ef7eb2e8f9f7 | 55 | |
| <> | 144:ef7eb2e8f9f7 | 56 | // timer settings |
| <> | 144:ef7eb2e8f9f7 | 57 | OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */ |
| <> | 144:ef7eb2e8f9f7 | 58 | OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */ |
| <> | 144:ef7eb2e8f9f7 | 59 | |
| <> | 144:ef7eb2e8f9f7 | 60 | OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ |
| <> | 144:ef7eb2e8f9f7 | 61 | |
| <> | 144:ef7eb2e8f9f7 | 62 | // INTC settings |
| <> | 144:ef7eb2e8f9f7 | 63 | InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt); |
| <> | 144:ef7eb2e8f9f7 | 64 | GIC_SetPriority(US_TICKER_TIMER_IRQn, 5); |
| <> | 144:ef7eb2e8f9f7 | 65 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
| <> | 144:ef7eb2e8f9f7 | 66 | } |
| <> | 144:ef7eb2e8f9f7 | 67 | |
| <> | 144:ef7eb2e8f9f7 | 68 | static uint64_t ticker_read_counter64(void) { |
| <> | 144:ef7eb2e8f9f7 | 69 | uint32_t cnt_val; |
| <> | 144:ef7eb2e8f9f7 | 70 | uint64_t cnt_val64; |
| <> | 144:ef7eb2e8f9f7 | 71 | |
| <> | 144:ef7eb2e8f9f7 | 72 | if (!us_ticker_inited) |
| <> | 144:ef7eb2e8f9f7 | 73 | us_ticker_init(); |
| <> | 144:ef7eb2e8f9f7 | 74 | |
| <> | 144:ef7eb2e8f9f7 | 75 | /* read counter */ |
| <> | 144:ef7eb2e8f9f7 | 76 | cnt_val = OSTM1CNT; |
| <> | 144:ef7eb2e8f9f7 | 77 | if (last_read > cnt_val) { |
| <> | 144:ef7eb2e8f9f7 | 78 | wrap_arround++; |
| <> | 144:ef7eb2e8f9f7 | 79 | } |
| <> | 144:ef7eb2e8f9f7 | 80 | last_read = cnt_val; |
| <> | 144:ef7eb2e8f9f7 | 81 | cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val; |
| <> | 144:ef7eb2e8f9f7 | 82 | |
| <> | 144:ef7eb2e8f9f7 | 83 | return cnt_val64; |
| <> | 144:ef7eb2e8f9f7 | 84 | } |
| <> | 144:ef7eb2e8f9f7 | 85 | |
| <> | 151:5eaa88a5bcc7 | 86 | static void us_ticker_read_last(void) { |
| <> | 144:ef7eb2e8f9f7 | 87 | uint64_t cnt_val64; |
| <> | 151:5eaa88a5bcc7 | 88 | |
| <> | 151:5eaa88a5bcc7 | 89 | cnt_val64 = ticker_read_counter64(); |
| <> | 151:5eaa88a5bcc7 | 90 | |
| <> | 151:5eaa88a5bcc7 | 91 | ticker_us_last64 = (cnt_val64 / count_clock); |
| <> | 151:5eaa88a5bcc7 | 92 | } |
| <> | 151:5eaa88a5bcc7 | 93 | |
| <> | 151:5eaa88a5bcc7 | 94 | uint32_t us_ticker_read() { |
| <> | 144:ef7eb2e8f9f7 | 95 | int check_irq_masked; |
| <> | 144:ef7eb2e8f9f7 | 96 | |
| <> | 144:ef7eb2e8f9f7 | 97 | #if defined ( __ICCARM__) |
| <> | 144:ef7eb2e8f9f7 | 98 | check_irq_masked = __disable_irq_iar(); |
| <> | 144:ef7eb2e8f9f7 | 99 | #else |
| <> | 144:ef7eb2e8f9f7 | 100 | check_irq_masked = __disable_irq(); |
| <> | 144:ef7eb2e8f9f7 | 101 | #endif /* __ICCARM__ */ |
| <> | 144:ef7eb2e8f9f7 | 102 | |
| <> | 151:5eaa88a5bcc7 | 103 | __vfp_neon_push(); |
| <> | 151:5eaa88a5bcc7 | 104 | us_ticker_read_last(); |
| <> | 151:5eaa88a5bcc7 | 105 | __vfp_neon_pop(); |
| <> | 144:ef7eb2e8f9f7 | 106 | |
| <> | 144:ef7eb2e8f9f7 | 107 | if (!check_irq_masked) { |
| <> | 144:ef7eb2e8f9f7 | 108 | __enable_irq(); |
| <> | 144:ef7eb2e8f9f7 | 109 | } |
| <> | 144:ef7eb2e8f9f7 | 110 | |
| <> | 144:ef7eb2e8f9f7 | 111 | /* clock to us */ |
| <> | 151:5eaa88a5bcc7 | 112 | return (uint32_t)ticker_us_last64; |
| <> | 151:5eaa88a5bcc7 | 113 | } |
| <> | 151:5eaa88a5bcc7 | 114 | |
| <> | 151:5eaa88a5bcc7 | 115 | static void us_ticker_calc_compare_match(void) { |
| <> | 151:5eaa88a5bcc7 | 116 | set_cmp_val64 = timestamp64 * count_clock; |
| <> | 144:ef7eb2e8f9f7 | 117 | } |
| <> | 144:ef7eb2e8f9f7 | 118 | |
| <> | 144:ef7eb2e8f9f7 | 119 | void us_ticker_set_interrupt(timestamp_t timestamp) { |
| <> | 144:ef7eb2e8f9f7 | 120 | // set match value |
| <> | 144:ef7eb2e8f9f7 | 121 | volatile uint32_t set_cmp_val; |
| <> | 144:ef7eb2e8f9f7 | 122 | uint64_t count_val_64; |
| <> | 144:ef7eb2e8f9f7 | 123 | |
| <> | 144:ef7eb2e8f9f7 | 124 | /* calc compare mach timestamp */ |
| <> | 144:ef7eb2e8f9f7 | 125 | timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp; |
| <> | 144:ef7eb2e8f9f7 | 126 | if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) { |
| <> | 144:ef7eb2e8f9f7 | 127 | /* This event is wrap arround */ |
| <> | 144:ef7eb2e8f9f7 | 128 | timestamp64 += 0x100000000; |
| <> | 144:ef7eb2e8f9f7 | 129 | } |
| <> | 144:ef7eb2e8f9f7 | 130 | |
| <> | 144:ef7eb2e8f9f7 | 131 | /* calc compare mach timestamp */ |
| <> | 151:5eaa88a5bcc7 | 132 | __vfp_neon_push(); |
| <> | 151:5eaa88a5bcc7 | 133 | us_ticker_calc_compare_match(); |
| <> | 151:5eaa88a5bcc7 | 134 | __vfp_neon_pop(); |
| <> | 151:5eaa88a5bcc7 | 135 | |
| <> | 144:ef7eb2e8f9f7 | 136 | set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF); |
| <> | 144:ef7eb2e8f9f7 | 137 | count_val_64 = ticker_read_counter64(); |
| <> | 144:ef7eb2e8f9f7 | 138 | if (set_cmp_val64 <= (count_val_64 + 500)) { |
| <> | 144:ef7eb2e8f9f7 | 139 | GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); |
| <> | 144:ef7eb2e8f9f7 | 140 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
| <> | 144:ef7eb2e8f9f7 | 141 | return; |
| <> | 144:ef7eb2e8f9f7 | 142 | } |
| <> | 144:ef7eb2e8f9f7 | 143 | OSTM1CMP = set_cmp_val; |
| <> | 144:ef7eb2e8f9f7 | 144 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
| <> | 144:ef7eb2e8f9f7 | 145 | } |
| <> | 144:ef7eb2e8f9f7 | 146 | |
| AnnaBridge | 174:b96e65c34a4d | 147 | void us_ticker_fire_interrupt(void) { |
| AnnaBridge | 174:b96e65c34a4d | 148 | GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); |
| AnnaBridge | 174:b96e65c34a4d | 149 | } |
| AnnaBridge | 174:b96e65c34a4d | 150 | |
| <> | 144:ef7eb2e8f9f7 | 151 | void us_ticker_disable_interrupt(void) { |
| <> | 144:ef7eb2e8f9f7 | 152 | GIC_DisableIRQ(US_TICKER_TIMER_IRQn); |
| <> | 144:ef7eb2e8f9f7 | 153 | } |
| <> | 144:ef7eb2e8f9f7 | 154 | |
| <> | 144:ef7eb2e8f9f7 | 155 | void us_ticker_clear_interrupt(void) { |
| <> | 144:ef7eb2e8f9f7 | 156 | GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn); |
| <> | 144:ef7eb2e8f9f7 | 157 | } |
