Additional font macro
STM32F429I-Discovery/stm32f429i_discovery_sdram.c@1:a6fd0931a9e9, 2016-02-05 (annotated)
- Committer:
- SomeRandomBloke
- Date:
- Fri Feb 05 09:20:30 2016 +0000
- Revision:
- 1:a6fd0931a9e9
- Parent:
- 0:e1d164542663
Added additional font macro
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bcostm | 0:e1d164542663 | 1 | /** |
bcostm | 0:e1d164542663 | 2 | ****************************************************************************** |
bcostm | 0:e1d164542663 | 3 | * @file stm32f429i_discovery_sdram.c |
bcostm | 0:e1d164542663 | 4 | * @author MCD Application Team |
bcostm | 0:e1d164542663 | 5 | * @version V2.1.2 |
bcostm | 0:e1d164542663 | 6 | * @date 02-March-2015 |
bcostm | 0:e1d164542663 | 7 | * @brief This file provides a set of functions needed to drive the |
bcostm | 0:e1d164542663 | 8 | * IS42S16400J SDRAM memory mounted on STM32F429I-Discovery Kit. |
bcostm | 0:e1d164542663 | 9 | ****************************************************************************** |
bcostm | 0:e1d164542663 | 10 | * @attention |
bcostm | 0:e1d164542663 | 11 | * |
bcostm | 0:e1d164542663 | 12 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
bcostm | 0:e1d164542663 | 13 | * |
bcostm | 0:e1d164542663 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
bcostm | 0:e1d164542663 | 15 | * are permitted provided that the following conditions are met: |
bcostm | 0:e1d164542663 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
bcostm | 0:e1d164542663 | 17 | * this list of conditions and the following disclaimer. |
bcostm | 0:e1d164542663 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bcostm | 0:e1d164542663 | 19 | * this list of conditions and the following disclaimer in the documentation |
bcostm | 0:e1d164542663 | 20 | * and/or other materials provided with the distribution. |
bcostm | 0:e1d164542663 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bcostm | 0:e1d164542663 | 22 | * may be used to endorse or promote products derived from this software |
bcostm | 0:e1d164542663 | 23 | * without specific prior written permission. |
bcostm | 0:e1d164542663 | 24 | * |
bcostm | 0:e1d164542663 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bcostm | 0:e1d164542663 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bcostm | 0:e1d164542663 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bcostm | 0:e1d164542663 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bcostm | 0:e1d164542663 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bcostm | 0:e1d164542663 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bcostm | 0:e1d164542663 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bcostm | 0:e1d164542663 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bcostm | 0:e1d164542663 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bcostm | 0:e1d164542663 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bcostm | 0:e1d164542663 | 35 | * |
bcostm | 0:e1d164542663 | 36 | ****************************************************************************** |
bcostm | 0:e1d164542663 | 37 | */ |
bcostm | 0:e1d164542663 | 38 | |
bcostm | 0:e1d164542663 | 39 | /* Includes ------------------------------------------------------------------*/ |
bcostm | 0:e1d164542663 | 40 | #include "stm32f429i_discovery_sdram.h" |
bcostm | 0:e1d164542663 | 41 | |
bcostm | 0:e1d164542663 | 42 | // mbed |
bcostm | 0:e1d164542663 | 43 | void wait_ms(int ms); |
bcostm | 0:e1d164542663 | 44 | |
bcostm | 0:e1d164542663 | 45 | /** @addtogroup BSP |
bcostm | 0:e1d164542663 | 46 | * @{ |
bcostm | 0:e1d164542663 | 47 | */ |
bcostm | 0:e1d164542663 | 48 | |
bcostm | 0:e1d164542663 | 49 | /** @addtogroup STM32F429I_DISCOVERY |
bcostm | 0:e1d164542663 | 50 | * @{ |
bcostm | 0:e1d164542663 | 51 | */ |
bcostm | 0:e1d164542663 | 52 | |
bcostm | 0:e1d164542663 | 53 | /** @defgroup STM32F429I_DISCOVERY_SDRAM |
bcostm | 0:e1d164542663 | 54 | * @{ |
bcostm | 0:e1d164542663 | 55 | */ |
bcostm | 0:e1d164542663 | 56 | |
bcostm | 0:e1d164542663 | 57 | /** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Types_Definitions |
bcostm | 0:e1d164542663 | 58 | * @{ |
bcostm | 0:e1d164542663 | 59 | */ |
bcostm | 0:e1d164542663 | 60 | /** |
bcostm | 0:e1d164542663 | 61 | * @} |
bcostm | 0:e1d164542663 | 62 | */ |
bcostm | 0:e1d164542663 | 63 | |
bcostm | 0:e1d164542663 | 64 | /** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Defines |
bcostm | 0:e1d164542663 | 65 | * @{ |
bcostm | 0:e1d164542663 | 66 | */ |
bcostm | 0:e1d164542663 | 67 | /** |
bcostm | 0:e1d164542663 | 68 | * @} |
bcostm | 0:e1d164542663 | 69 | */ |
bcostm | 0:e1d164542663 | 70 | |
bcostm | 0:e1d164542663 | 71 | /** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Macros |
bcostm | 0:e1d164542663 | 72 | * @{ |
bcostm | 0:e1d164542663 | 73 | */ |
bcostm | 0:e1d164542663 | 74 | /** |
bcostm | 0:e1d164542663 | 75 | * @} |
bcostm | 0:e1d164542663 | 76 | */ |
bcostm | 0:e1d164542663 | 77 | |
bcostm | 0:e1d164542663 | 78 | /** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Variables |
bcostm | 0:e1d164542663 | 79 | * @{ |
bcostm | 0:e1d164542663 | 80 | */ |
bcostm | 0:e1d164542663 | 81 | static SDRAM_HandleTypeDef SdramHandle; |
bcostm | 0:e1d164542663 | 82 | static FMC_SDRAM_TimingTypeDef Timing; |
bcostm | 0:e1d164542663 | 83 | static FMC_SDRAM_CommandTypeDef Command; |
bcostm | 0:e1d164542663 | 84 | /** |
bcostm | 0:e1d164542663 | 85 | * @} |
bcostm | 0:e1d164542663 | 86 | */ |
bcostm | 0:e1d164542663 | 87 | |
bcostm | 0:e1d164542663 | 88 | /** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Function_Prototypes |
bcostm | 0:e1d164542663 | 89 | * @{ |
bcostm | 0:e1d164542663 | 90 | */ |
bcostm | 0:e1d164542663 | 91 | static void MspInit(void); |
bcostm | 0:e1d164542663 | 92 | /** |
bcostm | 0:e1d164542663 | 93 | * @} |
bcostm | 0:e1d164542663 | 94 | */ |
bcostm | 0:e1d164542663 | 95 | |
bcostm | 0:e1d164542663 | 96 | /** @defgroup STM32F429I_DISCOVERY_SDRAM_Private_Functions |
bcostm | 0:e1d164542663 | 97 | * @{ |
bcostm | 0:e1d164542663 | 98 | */ |
bcostm | 0:e1d164542663 | 99 | |
bcostm | 0:e1d164542663 | 100 | /** |
bcostm | 0:e1d164542663 | 101 | * @brief Initializes the SDRAM device. |
bcostm | 0:e1d164542663 | 102 | * @param None |
bcostm | 0:e1d164542663 | 103 | * @retval None |
bcostm | 0:e1d164542663 | 104 | */ |
bcostm | 0:e1d164542663 | 105 | void BSP_SDRAM_Init(void) |
bcostm | 0:e1d164542663 | 106 | { |
bcostm | 0:e1d164542663 | 107 | /* SDRAM device configuration */ |
bcostm | 0:e1d164542663 | 108 | SdramHandle.Instance = FMC_SDRAM_DEVICE; |
bcostm | 0:e1d164542663 | 109 | |
bcostm | 0:e1d164542663 | 110 | /* FMC Configuration -------------------------------------------------------*/ |
bcostm | 0:e1d164542663 | 111 | /* FMC SDRAM Bank configuration */ |
bcostm | 0:e1d164542663 | 112 | /* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */ |
bcostm | 0:e1d164542663 | 113 | /* TMRD: 2 Clock cycles */ |
bcostm | 0:e1d164542663 | 114 | Timing.LoadToActiveDelay = 2; |
bcostm | 0:e1d164542663 | 115 | /* TXSR: min=70ns (7x11.11ns) */ |
bcostm | 0:e1d164542663 | 116 | Timing.ExitSelfRefreshDelay = 7; |
bcostm | 0:e1d164542663 | 117 | /* TRAS: min=42ns (4x11.11ns) max=120k (ns) */ |
bcostm | 0:e1d164542663 | 118 | Timing.SelfRefreshTime = 4; |
bcostm | 0:e1d164542663 | 119 | /* TRC: min=70 (7x11.11ns) */ |
bcostm | 0:e1d164542663 | 120 | Timing.RowCycleDelay = 7; |
bcostm | 0:e1d164542663 | 121 | /* TWR: min=1+ 7ns (1+1x11.11ns) */ |
bcostm | 0:e1d164542663 | 122 | Timing.WriteRecoveryTime = 2; |
bcostm | 0:e1d164542663 | 123 | /* TRP: 20ns => 2x11.11ns*/ |
bcostm | 0:e1d164542663 | 124 | Timing.RPDelay = 2; |
bcostm | 0:e1d164542663 | 125 | /* TRCD: 20ns => 2x11.11ns */ |
bcostm | 0:e1d164542663 | 126 | Timing.RCDDelay = 2; |
bcostm | 0:e1d164542663 | 127 | |
bcostm | 0:e1d164542663 | 128 | /* FMC SDRAM control configuration */ |
bcostm | 0:e1d164542663 | 129 | SdramHandle.Init.SDBank = FMC_SDRAM_BANK2; |
bcostm | 0:e1d164542663 | 130 | /* Row addressing: [7:0] */ |
bcostm | 0:e1d164542663 | 131 | SdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; |
bcostm | 0:e1d164542663 | 132 | /* Column addressing: [11:0] */ |
bcostm | 0:e1d164542663 | 133 | SdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; |
bcostm | 0:e1d164542663 | 134 | SdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; |
bcostm | 0:e1d164542663 | 135 | SdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; |
bcostm | 0:e1d164542663 | 136 | SdramHandle.Init.CASLatency = SDRAM_CAS_LATENCY; |
bcostm | 0:e1d164542663 | 137 | SdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; |
bcostm | 0:e1d164542663 | 138 | SdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; |
bcostm | 0:e1d164542663 | 139 | SdramHandle.Init.ReadBurst = SDRAM_READBURST; |
bcostm | 0:e1d164542663 | 140 | SdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1; |
bcostm | 0:e1d164542663 | 141 | |
bcostm | 0:e1d164542663 | 142 | /* SDRAM controller initialization */ |
bcostm | 0:e1d164542663 | 143 | MspInit(); |
bcostm | 0:e1d164542663 | 144 | HAL_SDRAM_Init(&SdramHandle, &Timing); |
bcostm | 0:e1d164542663 | 145 | |
bcostm | 0:e1d164542663 | 146 | /* SDRAM initialization sequence */ |
bcostm | 0:e1d164542663 | 147 | BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); |
bcostm | 0:e1d164542663 | 148 | } |
bcostm | 0:e1d164542663 | 149 | |
bcostm | 0:e1d164542663 | 150 | /** |
bcostm | 0:e1d164542663 | 151 | * @brief Programs the SDRAM device. |
bcostm | 0:e1d164542663 | 152 | * @param RefreshCount: SDRAM refresh counter value |
bcostm | 0:e1d164542663 | 153 | * @retval None |
bcostm | 0:e1d164542663 | 154 | */ |
bcostm | 0:e1d164542663 | 155 | void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) |
bcostm | 0:e1d164542663 | 156 | { |
bcostm | 0:e1d164542663 | 157 | __IO uint32_t tmpmrd =0; |
bcostm | 0:e1d164542663 | 158 | |
bcostm | 0:e1d164542663 | 159 | /* Step 1: Configure a clock configuration enable command */ |
bcostm | 0:e1d164542663 | 160 | Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; |
bcostm | 0:e1d164542663 | 161 | Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; |
bcostm | 0:e1d164542663 | 162 | Command.AutoRefreshNumber = 1; |
bcostm | 0:e1d164542663 | 163 | Command.ModeRegisterDefinition = 0; |
bcostm | 0:e1d164542663 | 164 | |
bcostm | 0:e1d164542663 | 165 | /* Send the command */ |
bcostm | 0:e1d164542663 | 166 | HAL_SDRAM_SendCommand(&SdramHandle, &Command, SDRAM_TIMEOUT); |
bcostm | 0:e1d164542663 | 167 | |
bcostm | 0:e1d164542663 | 168 | /* Step 2: Insert 100 us minimum delay */ |
bcostm | 0:e1d164542663 | 169 | /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ |
bcostm | 0:e1d164542663 | 170 | //HAL_Delay(1); |
bcostm | 0:e1d164542663 | 171 | wait_ms(1); |
bcostm | 0:e1d164542663 | 172 | |
bcostm | 0:e1d164542663 | 173 | /* Step 3: Configure a PALL (precharge all) command */ |
bcostm | 0:e1d164542663 | 174 | Command.CommandMode = FMC_SDRAM_CMD_PALL; |
bcostm | 0:e1d164542663 | 175 | Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; |
bcostm | 0:e1d164542663 | 176 | Command.AutoRefreshNumber = 1; |
bcostm | 0:e1d164542663 | 177 | Command.ModeRegisterDefinition = 0; |
bcostm | 0:e1d164542663 | 178 | |
bcostm | 0:e1d164542663 | 179 | /* Send the command */ |
bcostm | 0:e1d164542663 | 180 | HAL_SDRAM_SendCommand(&SdramHandle, &Command, SDRAM_TIMEOUT); |
bcostm | 0:e1d164542663 | 181 | |
bcostm | 0:e1d164542663 | 182 | /* Step 4: Configure an Auto Refresh command */ |
bcostm | 0:e1d164542663 | 183 | Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; |
bcostm | 0:e1d164542663 | 184 | Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; |
bcostm | 0:e1d164542663 | 185 | Command.AutoRefreshNumber = 4; |
bcostm | 0:e1d164542663 | 186 | Command.ModeRegisterDefinition = 0; |
bcostm | 0:e1d164542663 | 187 | |
bcostm | 0:e1d164542663 | 188 | /* Send the command */ |
bcostm | 0:e1d164542663 | 189 | HAL_SDRAM_SendCommand(&SdramHandle, &Command, SDRAM_TIMEOUT); |
bcostm | 0:e1d164542663 | 190 | |
bcostm | 0:e1d164542663 | 191 | /* Step 5: Program the external memory mode register */ |
bcostm | 0:e1d164542663 | 192 | tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 | |
bcostm | 0:e1d164542663 | 193 | SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | |
bcostm | 0:e1d164542663 | 194 | SDRAM_MODEREG_CAS_LATENCY_3 | |
bcostm | 0:e1d164542663 | 195 | SDRAM_MODEREG_OPERATING_MODE_STANDARD | |
bcostm | 0:e1d164542663 | 196 | SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; |
bcostm | 0:e1d164542663 | 197 | |
bcostm | 0:e1d164542663 | 198 | Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; |
bcostm | 0:e1d164542663 | 199 | Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; |
bcostm | 0:e1d164542663 | 200 | Command.AutoRefreshNumber = 1; |
bcostm | 0:e1d164542663 | 201 | Command.ModeRegisterDefinition = tmpmrd; |
bcostm | 0:e1d164542663 | 202 | |
bcostm | 0:e1d164542663 | 203 | /* Send the command */ |
bcostm | 0:e1d164542663 | 204 | HAL_SDRAM_SendCommand(&SdramHandle, &Command, SDRAM_TIMEOUT); |
bcostm | 0:e1d164542663 | 205 | |
bcostm | 0:e1d164542663 | 206 | /* Step 6: Set the refresh rate counter */ |
bcostm | 0:e1d164542663 | 207 | /* Set the device refresh rate */ |
bcostm | 0:e1d164542663 | 208 | HAL_SDRAM_ProgramRefreshRate(&SdramHandle, RefreshCount); |
bcostm | 0:e1d164542663 | 209 | } |
bcostm | 0:e1d164542663 | 210 | |
bcostm | 0:e1d164542663 | 211 | /** |
bcostm | 0:e1d164542663 | 212 | * @brief Reads an mount of data from the SDRAM memory in polling mode. |
bcostm | 0:e1d164542663 | 213 | * @param uwStartAddress : Read start address |
bcostm | 0:e1d164542663 | 214 | * @param pData : Pointer to data to be read |
bcostm | 0:e1d164542663 | 215 | * @param uwDataSize: Size of read data from the memory |
bcostm | 0:e1d164542663 | 216 | * @retval None |
bcostm | 0:e1d164542663 | 217 | */ |
bcostm | 0:e1d164542663 | 218 | void BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) |
bcostm | 0:e1d164542663 | 219 | { |
bcostm | 0:e1d164542663 | 220 | HAL_SDRAM_Read_32b(&SdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize); |
bcostm | 0:e1d164542663 | 221 | } |
bcostm | 0:e1d164542663 | 222 | |
bcostm | 0:e1d164542663 | 223 | /** |
bcostm | 0:e1d164542663 | 224 | * @brief Reads an mount of data from the SDRAM memory in DMA mode. |
bcostm | 0:e1d164542663 | 225 | * @param uwStartAddress : Read start address |
bcostm | 0:e1d164542663 | 226 | * @param pData : Pointer to data to be read |
bcostm | 0:e1d164542663 | 227 | * @param uwDataSize: Size of read data from the memory |
bcostm | 0:e1d164542663 | 228 | * @retval None |
bcostm | 0:e1d164542663 | 229 | */ |
bcostm | 0:e1d164542663 | 230 | void BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) |
bcostm | 0:e1d164542663 | 231 | { |
bcostm | 0:e1d164542663 | 232 | HAL_SDRAM_Read_DMA(&SdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize); |
bcostm | 0:e1d164542663 | 233 | } |
bcostm | 0:e1d164542663 | 234 | |
bcostm | 0:e1d164542663 | 235 | /** |
bcostm | 0:e1d164542663 | 236 | * @brief Writes an mount of data to the SDRAM memory in polling mode. |
bcostm | 0:e1d164542663 | 237 | * @param uwStartAddress : Write start address |
bcostm | 0:e1d164542663 | 238 | * @param pData : Pointer to data to be written |
bcostm | 0:e1d164542663 | 239 | * @param uwDataSize: Size of written data from the memory |
bcostm | 0:e1d164542663 | 240 | * @retval None |
bcostm | 0:e1d164542663 | 241 | */ |
bcostm | 0:e1d164542663 | 242 | void BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) |
bcostm | 0:e1d164542663 | 243 | { |
bcostm | 0:e1d164542663 | 244 | /* Disable write protection */ |
bcostm | 0:e1d164542663 | 245 | HAL_SDRAM_WriteProtection_Disable(&SdramHandle); |
bcostm | 0:e1d164542663 | 246 | |
bcostm | 0:e1d164542663 | 247 | /*Write 32-bit data buffer to SDRAM memory*/ |
bcostm | 0:e1d164542663 | 248 | HAL_SDRAM_Write_32b(&SdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize); |
bcostm | 0:e1d164542663 | 249 | } |
bcostm | 0:e1d164542663 | 250 | |
bcostm | 0:e1d164542663 | 251 | /** |
bcostm | 0:e1d164542663 | 252 | * @brief Writes an mount of data to the SDRAM memory in DMA mode. |
bcostm | 0:e1d164542663 | 253 | * @param uwStartAddress : Write start address |
bcostm | 0:e1d164542663 | 254 | * @param pData : Pointer to data to be written |
bcostm | 0:e1d164542663 | 255 | * @param uwDataSize: Size of written data from the memory |
bcostm | 0:e1d164542663 | 256 | * @retval None |
bcostm | 0:e1d164542663 | 257 | */ |
bcostm | 0:e1d164542663 | 258 | void BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) |
bcostm | 0:e1d164542663 | 259 | { |
bcostm | 0:e1d164542663 | 260 | HAL_SDRAM_Write_DMA(&SdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize); |
bcostm | 0:e1d164542663 | 261 | } |
bcostm | 0:e1d164542663 | 262 | |
bcostm | 0:e1d164542663 | 263 | /** |
bcostm | 0:e1d164542663 | 264 | * @brief Sends command to the SDRAM bank. |
bcostm | 0:e1d164542663 | 265 | * @param SdramCmd: Pointer to SDRAM command structure |
bcostm | 0:e1d164542663 | 266 | * @retval HAL status |
bcostm | 0:e1d164542663 | 267 | */ |
bcostm | 0:e1d164542663 | 268 | HAL_StatusTypeDef BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) |
bcostm | 0:e1d164542663 | 269 | { |
bcostm | 0:e1d164542663 | 270 | return(HAL_SDRAM_SendCommand(&SdramHandle, SdramCmd, SDRAM_TIMEOUT)); |
bcostm | 0:e1d164542663 | 271 | } |
bcostm | 0:e1d164542663 | 272 | |
bcostm | 0:e1d164542663 | 273 | /** |
bcostm | 0:e1d164542663 | 274 | * @brief Handles SDRAM DMA transfer interrupt request. |
bcostm | 0:e1d164542663 | 275 | * @param None |
bcostm | 0:e1d164542663 | 276 | * @retval None |
bcostm | 0:e1d164542663 | 277 | */ |
bcostm | 0:e1d164542663 | 278 | void BSP_SDRAM_DMA_IRQHandler(void) |
bcostm | 0:e1d164542663 | 279 | { |
bcostm | 0:e1d164542663 | 280 | HAL_DMA_IRQHandler(SdramHandle.hdma); |
bcostm | 0:e1d164542663 | 281 | } |
bcostm | 0:e1d164542663 | 282 | |
bcostm | 0:e1d164542663 | 283 | /** |
bcostm | 0:e1d164542663 | 284 | * @brief Initializes SDRAM MSP. |
bcostm | 0:e1d164542663 | 285 | * @param None |
bcostm | 0:e1d164542663 | 286 | * @retval None |
bcostm | 0:e1d164542663 | 287 | */ |
bcostm | 0:e1d164542663 | 288 | static void MspInit(void) |
bcostm | 0:e1d164542663 | 289 | { |
bcostm | 0:e1d164542663 | 290 | static DMA_HandleTypeDef dmaHandle; |
bcostm | 0:e1d164542663 | 291 | GPIO_InitTypeDef GPIO_InitStructure; |
bcostm | 0:e1d164542663 | 292 | SDRAM_HandleTypeDef *hsdram = &SdramHandle; |
bcostm | 0:e1d164542663 | 293 | |
bcostm | 0:e1d164542663 | 294 | /* Enable FMC clock */ |
bcostm | 0:e1d164542663 | 295 | __FMC_CLK_ENABLE(); |
bcostm | 0:e1d164542663 | 296 | |
bcostm | 0:e1d164542663 | 297 | /* Enable chosen DMAx clock */ |
bcostm | 0:e1d164542663 | 298 | __DMAx_CLK_ENABLE(); |
bcostm | 0:e1d164542663 | 299 | |
bcostm | 0:e1d164542663 | 300 | /* Enable GPIOs clock */ |
bcostm | 0:e1d164542663 | 301 | __GPIOB_CLK_ENABLE(); |
bcostm | 0:e1d164542663 | 302 | __GPIOC_CLK_ENABLE(); |
bcostm | 0:e1d164542663 | 303 | __GPIOD_CLK_ENABLE(); |
bcostm | 0:e1d164542663 | 304 | __GPIOE_CLK_ENABLE(); |
bcostm | 0:e1d164542663 | 305 | __GPIOF_CLK_ENABLE(); |
bcostm | 0:e1d164542663 | 306 | __GPIOG_CLK_ENABLE(); |
bcostm | 0:e1d164542663 | 307 | |
bcostm | 0:e1d164542663 | 308 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
bcostm | 0:e1d164542663 | 309 | /* |
bcostm | 0:e1d164542663 | 310 | +-------------------+--------------------+--------------------+--------------------+ |
bcostm | 0:e1d164542663 | 311 | + SDRAM pins assignment + |
bcostm | 0:e1d164542663 | 312 | +-------------------+--------------------+--------------------+--------------------+ |
bcostm | 0:e1d164542663 | 313 | | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | |
bcostm | 0:e1d164542663 | 314 | | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | |
bcostm | 0:e1d164542663 | 315 | | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | |
bcostm | 0:e1d164542663 | 316 | | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | |
bcostm | 0:e1d164542663 | 317 | | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ |
bcostm | 0:e1d164542663 | 318 | | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | |
bcostm | 0:e1d164542663 | 319 | | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | |
bcostm | 0:e1d164542663 | 320 | +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | |
bcostm | 0:e1d164542663 | 321 | | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | |
bcostm | 0:e1d164542663 | 322 | | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | |
bcostm | 0:e1d164542663 | 323 | | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | |
bcostm | 0:e1d164542663 | 324 | +-------------------+--------------------+--------------------+ |
bcostm | 0:e1d164542663 | 325 | | PB5 <-> FMC_SDCKE1| |
bcostm | 0:e1d164542663 | 326 | | PB6 <-> FMC_SDNE1 | |
bcostm | 0:e1d164542663 | 327 | | PC0 <-> FMC_SDNWE | |
bcostm | 0:e1d164542663 | 328 | +-------------------+ |
bcostm | 0:e1d164542663 | 329 | |
bcostm | 0:e1d164542663 | 330 | */ |
bcostm | 0:e1d164542663 | 331 | |
bcostm | 0:e1d164542663 | 332 | /* Common GPIO configuration */ |
bcostm | 0:e1d164542663 | 333 | GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; |
bcostm | 0:e1d164542663 | 334 | GPIO_InitStructure.Speed = GPIO_SPEED_FAST; |
bcostm | 0:e1d164542663 | 335 | GPIO_InitStructure.Pull = GPIO_NOPULL; |
bcostm | 0:e1d164542663 | 336 | GPIO_InitStructure.Alternate = GPIO_AF12_FMC; |
bcostm | 0:e1d164542663 | 337 | |
bcostm | 0:e1d164542663 | 338 | /* GPIOB configuration */ |
bcostm | 0:e1d164542663 | 339 | GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_6; |
bcostm | 0:e1d164542663 | 340 | HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); |
bcostm | 0:e1d164542663 | 341 | |
bcostm | 0:e1d164542663 | 342 | /* GPIOC configuration */ |
bcostm | 0:e1d164542663 | 343 | GPIO_InitStructure.Pin = GPIO_PIN_0; |
bcostm | 0:e1d164542663 | 344 | HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); |
bcostm | 0:e1d164542663 | 345 | |
bcostm | 0:e1d164542663 | 346 | /* GPIOD configuration */ |
bcostm | 0:e1d164542663 | 347 | GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | |
bcostm | 0:e1d164542663 | 348 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_14 | |
bcostm | 0:e1d164542663 | 349 | GPIO_PIN_15; |
bcostm | 0:e1d164542663 | 350 | HAL_GPIO_Init(GPIOD, &GPIO_InitStructure); |
bcostm | 0:e1d164542663 | 351 | |
bcostm | 0:e1d164542663 | 352 | /* GPIOE configuration */ |
bcostm | 0:e1d164542663 | 353 | GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7 | |
bcostm | 0:e1d164542663 | 354 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | |
bcostm | 0:e1d164542663 | 355 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | |
bcostm | 0:e1d164542663 | 356 | GPIO_PIN_14 | GPIO_PIN_15; |
bcostm | 0:e1d164542663 | 357 | HAL_GPIO_Init(GPIOE, &GPIO_InitStructure); |
bcostm | 0:e1d164542663 | 358 | |
bcostm | 0:e1d164542663 | 359 | /* GPIOF configuration */ |
bcostm | 0:e1d164542663 | 360 | GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | |
bcostm | 0:e1d164542663 | 361 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | |
bcostm | 0:e1d164542663 | 362 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | |
bcostm | 0:e1d164542663 | 363 | GPIO_PIN_14 | GPIO_PIN_15; |
bcostm | 0:e1d164542663 | 364 | HAL_GPIO_Init(GPIOF, &GPIO_InitStructure); |
bcostm | 0:e1d164542663 | 365 | |
bcostm | 0:e1d164542663 | 366 | /* GPIOG configuration */ |
bcostm | 0:e1d164542663 | 367 | GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | |
bcostm | 0:e1d164542663 | 368 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_15; |
bcostm | 0:e1d164542663 | 369 | HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); |
bcostm | 0:e1d164542663 | 370 | |
bcostm | 0:e1d164542663 | 371 | /* Configure common DMA parameters */ |
bcostm | 0:e1d164542663 | 372 | dmaHandle.Init.Channel = SDRAM_DMAx_CHANNEL; |
bcostm | 0:e1d164542663 | 373 | dmaHandle.Init.Direction = DMA_MEMORY_TO_MEMORY; |
bcostm | 0:e1d164542663 | 374 | dmaHandle.Init.PeriphInc = DMA_PINC_ENABLE; |
bcostm | 0:e1d164542663 | 375 | dmaHandle.Init.MemInc = DMA_MINC_ENABLE; |
bcostm | 0:e1d164542663 | 376 | dmaHandle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; |
bcostm | 0:e1d164542663 | 377 | dmaHandle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; |
bcostm | 0:e1d164542663 | 378 | dmaHandle.Init.Mode = DMA_NORMAL; |
bcostm | 0:e1d164542663 | 379 | dmaHandle.Init.Priority = DMA_PRIORITY_HIGH; |
bcostm | 0:e1d164542663 | 380 | dmaHandle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; |
bcostm | 0:e1d164542663 | 381 | dmaHandle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; |
bcostm | 0:e1d164542663 | 382 | dmaHandle.Init.MemBurst = DMA_MBURST_SINGLE; |
bcostm | 0:e1d164542663 | 383 | dmaHandle.Init.PeriphBurst = DMA_PBURST_SINGLE; |
bcostm | 0:e1d164542663 | 384 | |
bcostm | 0:e1d164542663 | 385 | dmaHandle.Instance = SDRAM_DMAx_STREAM; |
bcostm | 0:e1d164542663 | 386 | |
bcostm | 0:e1d164542663 | 387 | /* Associate the DMA handle */ |
bcostm | 0:e1d164542663 | 388 | __HAL_LINKDMA(hsdram, hdma, dmaHandle); |
bcostm | 0:e1d164542663 | 389 | |
bcostm | 0:e1d164542663 | 390 | /* Deinitialize the stream for new transfer */ |
bcostm | 0:e1d164542663 | 391 | HAL_DMA_DeInit(&dmaHandle); |
bcostm | 0:e1d164542663 | 392 | |
bcostm | 0:e1d164542663 | 393 | /* Configure the DMA stream */ |
bcostm | 0:e1d164542663 | 394 | HAL_DMA_Init(&dmaHandle); |
bcostm | 0:e1d164542663 | 395 | |
bcostm | 0:e1d164542663 | 396 | /* NVIC configuration for DMA transfer complete interrupt */ |
bcostm | 0:e1d164542663 | 397 | HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 0, 0); |
bcostm | 0:e1d164542663 | 398 | HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); |
bcostm | 0:e1d164542663 | 399 | } |
bcostm | 0:e1d164542663 | 400 | |
bcostm | 0:e1d164542663 | 401 | /** |
bcostm | 0:e1d164542663 | 402 | * @} |
bcostm | 0:e1d164542663 | 403 | */ |
bcostm | 0:e1d164542663 | 404 | |
bcostm | 0:e1d164542663 | 405 | /** |
bcostm | 0:e1d164542663 | 406 | * @} |
bcostm | 0:e1d164542663 | 407 | */ |
bcostm | 0:e1d164542663 | 408 | |
bcostm | 0:e1d164542663 | 409 | /** |
bcostm | 0:e1d164542663 | 410 | * @} |
bcostm | 0:e1d164542663 | 411 | */ |
bcostm | 0:e1d164542663 | 412 | |
bcostm | 0:e1d164542663 | 413 | /** |
bcostm | 0:e1d164542663 | 414 | * @} |
bcostm | 0:e1d164542663 | 415 | */ |
bcostm | 0:e1d164542663 | 416 | |
bcostm | 0:e1d164542663 | 417 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |