rau cha / mbed-src-I2CWaitFix

fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088

Fork of mbed-src by mbed official

vendor/NXP/LPC812/hal/us_ticker.c@13:bd9ff402dd42, 2013-08-05 (annotated)

Committer:
Shikaneo
Date:
Mon Aug 05 02:27:27 2013 +0000
Revision:
13:bd9ff402dd42
Parent:
10:3bc89ef62ce7 
equipped timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include <stddef.h>
emilmont 10:3bc89ef62ce7 17 #include "us_ticker_api.h"
emilmont 10:3bc89ef62ce7 18 #include "PeripheralNames.h"
emilmont 10:3bc89ef62ce7 19
emilmont 10:3bc89ef62ce7 20 #define US_TICKER_TIMER_IRQn SCT_IRQn
emilmont 10:3bc89ef62ce7 21
emilmont 10:3bc89ef62ce7 22 int us_ticker_inited = 0;
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 void us_ticker_init(void) {
emilmont 10:3bc89ef62ce7 25 if (us_ticker_inited) return;
emilmont 10:3bc89ef62ce7 26 us_ticker_inited = 1;
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 // Enable the SCT clock
emilmont 10:3bc89ef62ce7 29 LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 // Clear peripheral reset the SCT:
emilmont 10:3bc89ef62ce7 32 LPC_SYSCON->PRESETCTRL |= (1 << 8);
emilmont 10:3bc89ef62ce7 33
emilmont 10:3bc89ef62ce7 34 // Unified counter (32 bits)
emilmont 10:3bc89ef62ce7 35 LPC_SCT->CONFIG |= 1;
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 // halt and clear the counter
emilmont 10:3bc89ef62ce7 38 LPC_SCT->CTRL_L |= (1 << 2) | (1 << 3);
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 // System Clock (12)MHz -> us_ticker (1)MHz
emilmont 10:3bc89ef62ce7 41 LPC_SCT->CTRL_L |= ((SystemCoreClock/1000000 - 1) << 5);
emilmont 10:3bc89ef62ce7 42
emilmont 10:3bc89ef62ce7 43 // unhalt the counter:
emilmont 10:3bc89ef62ce7 44 // - clearing bit 2 of the CTRL register
emilmont 10:3bc89ef62ce7 45 LPC_SCT->CTRL_L &= ~(1 << 2);
emilmont 10:3bc89ef62ce7 46
emilmont 10:3bc89ef62ce7 47 NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
emilmont 10:3bc89ef62ce7 48 NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
emilmont 10:3bc89ef62ce7 49 }
emilmont 10:3bc89ef62ce7 50
emilmont 10:3bc89ef62ce7 51 uint32_t us_ticker_read() {
emilmont 10:3bc89ef62ce7 52 if (!us_ticker_inited)
emilmont 10:3bc89ef62ce7 53 us_ticker_init();
emilmont 10:3bc89ef62ce7 54
emilmont 10:3bc89ef62ce7 55 return LPC_SCT->COUNT_U;
emilmont 10:3bc89ef62ce7 56 }
emilmont 10:3bc89ef62ce7 57
emilmont 10:3bc89ef62ce7 58 void us_ticker_set_interrupt(unsigned int timestamp) {
emilmont 10:3bc89ef62ce7 59 // halt the counter:
emilmont 10:3bc89ef62ce7 60 // - setting bit 2 of the CTRL register
emilmont 10:3bc89ef62ce7 61 LPC_SCT->CTRL_L |= (1 << 2);
emilmont 10:3bc89ef62ce7 62
emilmont 10:3bc89ef62ce7 63 // set timestamp in compare register
emilmont 10:3bc89ef62ce7 64 LPC_SCT->MATCH[0].U = timestamp;
emilmont 10:3bc89ef62ce7 65
emilmont 10:3bc89ef62ce7 66 // unhalt the counter:
emilmont 10:3bc89ef62ce7 67 // - clearing bit 2 of the CTRL register
emilmont 10:3bc89ef62ce7 68 LPC_SCT->CTRL_L &= ~(1 << 2);
emilmont 10:3bc89ef62ce7 69
emilmont 10:3bc89ef62ce7 70 // if events are not enabled, enable them
emilmont 10:3bc89ef62ce7 71 if (!(LPC_SCT->EVEN & 0x01)) {
emilmont 10:3bc89ef62ce7 72
emilmont 10:3bc89ef62ce7 73 // comb mode = match only
emilmont 10:3bc89ef62ce7 74 LPC_SCT->EVENT[0].CTRL = (1 << 12);
emilmont 10:3bc89ef62ce7 75
emilmont 10:3bc89ef62ce7 76 // ref manual:
emilmont 10:3bc89ef62ce7 77 // In simple applications that do not
emilmont 10:3bc89ef62ce7 78 // use states, write 0x01 to this
emilmont 10:3bc89ef62ce7 79 // register to enable an event
emilmont 10:3bc89ef62ce7 80 LPC_SCT->EVENT[0].STATE |= 0x1;
emilmont 10:3bc89ef62ce7 81
emilmont 10:3bc89ef62ce7 82 // enable events
emilmont 10:3bc89ef62ce7 83 LPC_SCT->EVEN |= 0x1;
emilmont 10:3bc89ef62ce7 84 }
emilmont 10:3bc89ef62ce7 85 }
emilmont 10:3bc89ef62ce7 86
emilmont 10:3bc89ef62ce7 87 void us_ticker_disable_interrupt(void) {
emilmont 10:3bc89ef62ce7 88 LPC_SCT->EVEN &= ~1;
emilmont 10:3bc89ef62ce7 89 }
emilmont 10:3bc89ef62ce7 90
emilmont 10:3bc89ef62ce7 91 void us_ticker_clear_interrupt(void) {
emilmont 10:3bc89ef62ce7 92 LPC_SCT->EVFLAG = 1;
emilmont 10:3bc89ef62ce7 93 }