rau cha / mbed-src-I2CWaitFix

fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088

Fork of mbed-src by mbed official

vendor/NXP/LPC11U24/cmsis/system_LPC11Uxx.c@13:bd9ff402dd42, 2013-08-05 (annotated)

Committer:
Shikaneo
Date:
Mon Aug 05 02:27:27 2013 +0000
Revision:
13:bd9ff402dd42
Parent:
10:3bc89ef62ce7 
equipped timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /******************************************************************************
emilmont 10:3bc89ef62ce7 2 * @file system_LPC11Uxx.c
emilmont 10:3bc89ef62ce7 3 * @purpose CMSIS Cortex-M3 Device Peripheral Access Layer Source File
emilmont 10:3bc89ef62ce7 4 * for the NXP LPC13xx Device Series
emilmont 10:3bc89ef62ce7 5 * @version V1.10
emilmont 10:3bc89ef62ce7 6 * @date 24. November 2010
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * @note
emilmont 10:3bc89ef62ce7 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 10 *
emilmont 10:3bc89ef62ce7 11 * @par
emilmont 10:3bc89ef62ce7 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 10:3bc89ef62ce7 13 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 14 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 15 *
emilmont 10:3bc89ef62ce7 16 * @par
emilmont 10:3bc89ef62ce7 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 22 *
emilmont 10:3bc89ef62ce7 23 ******************************************************************************/
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26 #include <stdint.h>
emilmont 10:3bc89ef62ce7 27 #include "LPC11Uxx.h"
emilmont 10:3bc89ef62ce7 28
emilmont 10:3bc89ef62ce7 29 /*
emilmont 10:3bc89ef62ce7 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
emilmont 10:3bc89ef62ce7 31 */
emilmont 10:3bc89ef62ce7 32
emilmont 10:3bc89ef62ce7 33 /*--------------------- Clock Configuration ----------------------------------
emilmont 10:3bc89ef62ce7 34 //
emilmont 10:3bc89ef62ce7 35 // <e> Clock Configuration
emilmont 10:3bc89ef62ce7 36 // <h> System Oscillator Control Register (SYSOSCCTRL)
emilmont 10:3bc89ef62ce7 37 // <o1.0> BYPASS: System Oscillator Bypass Enable
emilmont 10:3bc89ef62ce7 38 // <i> If enabled then PLL input (sys_osc_clk) is fed
emilmont 10:3bc89ef62ce7 39 // <i> directly from XTALIN and XTALOUT pins.
emilmont 10:3bc89ef62ce7 40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
emilmont 10:3bc89ef62ce7 41 // <i> Determines frequency range for Low-power oscillator.
emilmont 10:3bc89ef62ce7 42 // <0=> 1 - 20 MHz
emilmont 10:3bc89ef62ce7 43 // <1=> 15 - 25 MHz
emilmont 10:3bc89ef62ce7 44 // </h>
emilmont 10:3bc89ef62ce7 45 //
emilmont 10:3bc89ef62ce7 46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
emilmont 10:3bc89ef62ce7 47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
emilmont 10:3bc89ef62ce7 48 // <i> wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))
emilmont 10:3bc89ef62ce7 49 // <0-31>
emilmont 10:3bc89ef62ce7 50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
emilmont 10:3bc89ef62ce7 51 // <0=> Undefined
emilmont 10:3bc89ef62ce7 52 // <1=> 0.5 MHz
emilmont 10:3bc89ef62ce7 53 // <2=> 0.8 MHz
emilmont 10:3bc89ef62ce7 54 // <3=> 1.1 MHz
emilmont 10:3bc89ef62ce7 55 // <4=> 1.4 MHz
emilmont 10:3bc89ef62ce7 56 // <5=> 1.6 MHz
emilmont 10:3bc89ef62ce7 57 // <6=> 1.8 MHz
emilmont 10:3bc89ef62ce7 58 // <7=> 2.0 MHz
emilmont 10:3bc89ef62ce7 59 // <8=> 2.2 MHz
emilmont 10:3bc89ef62ce7 60 // <9=> 2.4 MHz
emilmont 10:3bc89ef62ce7 61 // <10=> 2.6 MHz
emilmont 10:3bc89ef62ce7 62 // <11=> 2.7 MHz
emilmont 10:3bc89ef62ce7 63 // <12=> 2.9 MHz
emilmont 10:3bc89ef62ce7 64 // <13=> 3.1 MHz
emilmont 10:3bc89ef62ce7 65 // <14=> 3.2 MHz
emilmont 10:3bc89ef62ce7 66 // <15=> 3.4 MHz
emilmont 10:3bc89ef62ce7 67 // </h>
emilmont 10:3bc89ef62ce7 68 //
emilmont 10:3bc89ef62ce7 69 // <h> System PLL Control Register (SYSPLLCTRL)
emilmont 10:3bc89ef62ce7 70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
emilmont 10:3bc89ef62ce7 71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
emilmont 10:3bc89ef62ce7 72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
emilmont 10:3bc89ef62ce7 73 // <o3.0..4> MSEL: Feedback Divider Selection
emilmont 10:3bc89ef62ce7 74 // <i> M = MSEL + 1
emilmont 10:3bc89ef62ce7 75 // <0-31>
emilmont 10:3bc89ef62ce7 76 // <o3.5..6> PSEL: Post Divider Selection
emilmont 10:3bc89ef62ce7 77 // <0=> P = 1
emilmont 10:3bc89ef62ce7 78 // <1=> P = 2
emilmont 10:3bc89ef62ce7 79 // <2=> P = 4
emilmont 10:3bc89ef62ce7 80 // <3=> P = 8
emilmont 10:3bc89ef62ce7 81 // </h>
emilmont 10:3bc89ef62ce7 82 //
emilmont 10:3bc89ef62ce7 83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
emilmont 10:3bc89ef62ce7 84 // <o4.0..1> SEL: System PLL Clock Source
emilmont 10:3bc89ef62ce7 85 // <0=> IRC Oscillator
emilmont 10:3bc89ef62ce7 86 // <1=> System Oscillator
emilmont 10:3bc89ef62ce7 87 // <2=> Reserved
emilmont 10:3bc89ef62ce7 88 // <3=> Reserved
emilmont 10:3bc89ef62ce7 89 // </h>
emilmont 10:3bc89ef62ce7 90 //
emilmont 10:3bc89ef62ce7 91 // <h> Main Clock Source Select Register (MAINCLKSEL)
emilmont 10:3bc89ef62ce7 92 // <o5.0..1> SEL: Clock Source for Main Clock
emilmont 10:3bc89ef62ce7 93 // <0=> IRC Oscillator
emilmont 10:3bc89ef62ce7 94 // <1=> Input Clock to System PLL
emilmont 10:3bc89ef62ce7 95 // <2=> WDT Oscillator
emilmont 10:3bc89ef62ce7 96 // <3=> System PLL Clock Out
emilmont 10:3bc89ef62ce7 97 // </h>
emilmont 10:3bc89ef62ce7 98 //
emilmont 10:3bc89ef62ce7 99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
emilmont 10:3bc89ef62ce7 100 // <o6.0..7> DIV: System AHB Clock Divider
emilmont 10:3bc89ef62ce7 101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
emilmont 10:3bc89ef62ce7 102 // <i> 0 = is disabled
emilmont 10:3bc89ef62ce7 103 // <0-255>
emilmont 10:3bc89ef62ce7 104 // </h>
emilmont 10:3bc89ef62ce7 105 //
emilmont 10:3bc89ef62ce7 106 // <h> USB PLL Control Register (USBPLLCTRL)
emilmont 10:3bc89ef62ce7 107 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
emilmont 10:3bc89ef62ce7 108 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
emilmont 10:3bc89ef62ce7 109 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
emilmont 10:3bc89ef62ce7 110 // <o7.0..4> MSEL: Feedback Divider Selection
emilmont 10:3bc89ef62ce7 111 // <i> M = MSEL + 1
emilmont 10:3bc89ef62ce7 112 // <0-31>
emilmont 10:3bc89ef62ce7 113 // <o7.5..6> PSEL: Post Divider Selection
emilmont 10:3bc89ef62ce7 114 // <0=> P = 1
emilmont 10:3bc89ef62ce7 115 // <1=> P = 2
emilmont 10:3bc89ef62ce7 116 // <2=> P = 4
emilmont 10:3bc89ef62ce7 117 // <3=> P = 8
emilmont 10:3bc89ef62ce7 118 // </h>
emilmont 10:3bc89ef62ce7 119 //
emilmont 10:3bc89ef62ce7 120 // <h> USB PLL Clock Source Select Register (USBPLLCLKSEL)
emilmont 10:3bc89ef62ce7 121 // <o8.0..1> SEL: USB PLL Clock Source
emilmont 10:3bc89ef62ce7 122 // <i> USB PLL clock source must be switched to System Oscillator for correct USB operation
emilmont 10:3bc89ef62ce7 123 // <0=> IRC Oscillator
emilmont 10:3bc89ef62ce7 124 // <1=> System Oscillator
emilmont 10:3bc89ef62ce7 125 // <2=> Reserved
emilmont 10:3bc89ef62ce7 126 // <3=> Reserved
emilmont 10:3bc89ef62ce7 127 // </h>
emilmont 10:3bc89ef62ce7 128 //
emilmont 10:3bc89ef62ce7 129 // <h> USB Clock Source Select Register (USBCLKSEL)
emilmont 10:3bc89ef62ce7 130 // <o9.0..1> SEL: System PLL Clock Source
emilmont 10:3bc89ef62ce7 131 // <0=> USB PLL out
emilmont 10:3bc89ef62ce7 132 // <1=> Main clock
emilmont 10:3bc89ef62ce7 133 // <2=> Reserved
emilmont 10:3bc89ef62ce7 134 // <3=> Reserved
emilmont 10:3bc89ef62ce7 135 // </h>
emilmont 10:3bc89ef62ce7 136 //
emilmont 10:3bc89ef62ce7 137 // <h> USB Clock Divider Register (USBCLKDIV)
emilmont 10:3bc89ef62ce7 138 // <o10.0..7> DIV: USB Clock Divider
emilmont 10:3bc89ef62ce7 139 // <i> Divides USB clock to 48 MHz.
emilmont 10:3bc89ef62ce7 140 // <i> 0 = is disabled
emilmont 10:3bc89ef62ce7 141 // <0-255>
emilmont 10:3bc89ef62ce7 142 // </h>
emilmont 10:3bc89ef62ce7 143 // </e>
emilmont 10:3bc89ef62ce7 144 */
emilmont 10:3bc89ef62ce7 145 #define CLOCK_SETUP 1
emilmont 10:3bc89ef62ce7 146 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
emilmont 10:3bc89ef62ce7 147 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
emilmont 10:3bc89ef62ce7 148 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
emilmont 10:3bc89ef62ce7 149 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
emilmont 10:3bc89ef62ce7 150 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
emilmont 10:3bc89ef62ce7 151 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
emilmont 10:3bc89ef62ce7 152 #define USBPLLCTRL_Val 0x00000023 // Reset: 0x000
emilmont 10:3bc89ef62ce7 153 #define USBPLLCLKSEL_Val 0x00000001 // Reset: 0x000
emilmont 10:3bc89ef62ce7 154 #define USBCLKSEL_Val 0x00000000 // Reset: 0x000
emilmont 10:3bc89ef62ce7 155 #define USBCLKDIV_Val 0x00000001 // Reset: 0x001
emilmont 10:3bc89ef62ce7 156
emilmont 10:3bc89ef62ce7 157 /*
emilmont 10:3bc89ef62ce7 158 //-------- <<< end of configuration section >>> ------------------------------
emilmont 10:3bc89ef62ce7 159 */
emilmont 10:3bc89ef62ce7 160
emilmont 10:3bc89ef62ce7 161 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 162 Check the register settings
emilmont 10:3bc89ef62ce7 163 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 164 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
emilmont 10:3bc89ef62ce7 165 #define CHECK_RSVD(val, mask) (val & mask)
emilmont 10:3bc89ef62ce7 166
emilmont 10:3bc89ef62ce7 167 /* Clock Configuration -------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 168 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
emilmont 10:3bc89ef62ce7 169 #error "SYSOSCCTRL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 170 #endif
emilmont 10:3bc89ef62ce7 171
emilmont 10:3bc89ef62ce7 172 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
emilmont 10:3bc89ef62ce7 173 #error "WDTOSCCTRL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 174 #endif
emilmont 10:3bc89ef62ce7 175
emilmont 10:3bc89ef62ce7 176 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
emilmont 10:3bc89ef62ce7 177 #error "SYSPLLCLKSEL: Value out of range!"
emilmont 10:3bc89ef62ce7 178 #endif
emilmont 10:3bc89ef62ce7 179
emilmont 10:3bc89ef62ce7 180 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
emilmont 10:3bc89ef62ce7 181 #error "SYSPLLCTRL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 182 #endif
emilmont 10:3bc89ef62ce7 183
emilmont 10:3bc89ef62ce7 184 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
emilmont 10:3bc89ef62ce7 185 #error "MAINCLKSEL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 186 #endif
emilmont 10:3bc89ef62ce7 187
emilmont 10:3bc89ef62ce7 188 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
emilmont 10:3bc89ef62ce7 189 #error "SYSAHBCLKDIV: Value out of range!"
emilmont 10:3bc89ef62ce7 190 #endif
emilmont 10:3bc89ef62ce7 191
emilmont 10:3bc89ef62ce7 192 #if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
emilmont 10:3bc89ef62ce7 193 #error "USBPLLCLKSEL: Value out of range!"
emilmont 10:3bc89ef62ce7 194 #endif
emilmont 10:3bc89ef62ce7 195
emilmont 10:3bc89ef62ce7 196 #if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
emilmont 10:3bc89ef62ce7 197 #error "USBPLLCTRL: Invalid values of reserved bits!"
emilmont 10:3bc89ef62ce7 198 #endif
emilmont 10:3bc89ef62ce7 199
emilmont 10:3bc89ef62ce7 200 #if (CHECK_RANGE((USBCLKSEL_Val), 0, 1))
emilmont 10:3bc89ef62ce7 201 #error "USBCLKSEL: Value out of range!"
emilmont 10:3bc89ef62ce7 202 #endif
emilmont 10:3bc89ef62ce7 203
emilmont 10:3bc89ef62ce7 204 #if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
emilmont 10:3bc89ef62ce7 205 #error "USBCLKDIV: Value out of range!"
emilmont 10:3bc89ef62ce7 206 #endif
emilmont 10:3bc89ef62ce7 207
emilmont 10:3bc89ef62ce7 208
emilmont 10:3bc89ef62ce7 209 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 210 DEFINES
emilmont 10:3bc89ef62ce7 211 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 212
emilmont 10:3bc89ef62ce7 213 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 214 Define clocks
emilmont 10:3bc89ef62ce7 215 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 216 #define __XTAL (12000000UL) /* Oscillator frequency */
emilmont 10:3bc89ef62ce7 217 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
emilmont 10:3bc89ef62ce7 218 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
emilmont 10:3bc89ef62ce7 219
emilmont 10:3bc89ef62ce7 220
emilmont 10:3bc89ef62ce7 221 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
emilmont 10:3bc89ef62ce7 222 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
emilmont 10:3bc89ef62ce7 223
emilmont 10:3bc89ef62ce7 224 #if (CLOCK_SETUP) /* Clock Setup */
emilmont 10:3bc89ef62ce7 225 #if (__FREQSEL == 0)
emilmont 10:3bc89ef62ce7 226 #define __WDT_OSC_CLK ( 0) /* undefined */
emilmont 10:3bc89ef62ce7 227 #elif (__FREQSEL == 1)
emilmont 10:3bc89ef62ce7 228 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 229 #elif (__FREQSEL == 2)
emilmont 10:3bc89ef62ce7 230 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 231 #elif (__FREQSEL == 3)
emilmont 10:3bc89ef62ce7 232 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 233 #elif (__FREQSEL == 4)
emilmont 10:3bc89ef62ce7 234 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 235 #elif (__FREQSEL == 5)
emilmont 10:3bc89ef62ce7 236 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 237 #elif (__FREQSEL == 6)
emilmont 10:3bc89ef62ce7 238 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 239 #elif (__FREQSEL == 7)
emilmont 10:3bc89ef62ce7 240 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 241 #elif (__FREQSEL == 8)
emilmont 10:3bc89ef62ce7 242 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 243 #elif (__FREQSEL == 9)
emilmont 10:3bc89ef62ce7 244 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 245 #elif (__FREQSEL == 10)
emilmont 10:3bc89ef62ce7 246 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 247 #elif (__FREQSEL == 11)
emilmont 10:3bc89ef62ce7 248 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 249 #elif (__FREQSEL == 12)
emilmont 10:3bc89ef62ce7 250 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 251 #elif (__FREQSEL == 13)
emilmont 10:3bc89ef62ce7 252 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 253 #elif (__FREQSEL == 14)
emilmont 10:3bc89ef62ce7 254 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 255 #else
emilmont 10:3bc89ef62ce7 256 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
emilmont 10:3bc89ef62ce7 257 #endif
emilmont 10:3bc89ef62ce7 258
emilmont 10:3bc89ef62ce7 259 /* sys_pllclkin calculation */
emilmont 10:3bc89ef62ce7 260 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
emilmont 10:3bc89ef62ce7 261 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
emilmont 10:3bc89ef62ce7 262 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 263 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
emilmont 10:3bc89ef62ce7 264 #else
emilmont 10:3bc89ef62ce7 265 #define __SYS_PLLCLKIN (0)
emilmont 10:3bc89ef62ce7 266 #endif
emilmont 10:3bc89ef62ce7 267
emilmont 10:3bc89ef62ce7 268 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
emilmont 10:3bc89ef62ce7 269
emilmont 10:3bc89ef62ce7 270 /* main clock calculation */
emilmont 10:3bc89ef62ce7 271 #if ((MAINCLKSEL_Val & 0x03) == 0)
emilmont 10:3bc89ef62ce7 272 #define __MAIN_CLOCK (__IRC_OSC_CLK)
emilmont 10:3bc89ef62ce7 273 #elif ((MAINCLKSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 274 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
emilmont 10:3bc89ef62ce7 275 #elif ((MAINCLKSEL_Val & 0x03) == 2)
emilmont 10:3bc89ef62ce7 276 #if (__FREQSEL == 0)
emilmont 10:3bc89ef62ce7 277 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
emilmont 10:3bc89ef62ce7 278 #else
emilmont 10:3bc89ef62ce7 279 #define __MAIN_CLOCK (__WDT_OSC_CLK)
emilmont 10:3bc89ef62ce7 280 #endif
emilmont 10:3bc89ef62ce7 281 #elif ((MAINCLKSEL_Val & 0x03) == 3)
emilmont 10:3bc89ef62ce7 282 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
emilmont 10:3bc89ef62ce7 283 #else
emilmont 10:3bc89ef62ce7 284 #define __MAIN_CLOCK (0)
emilmont 10:3bc89ef62ce7 285 #endif
emilmont 10:3bc89ef62ce7 286
emilmont 10:3bc89ef62ce7 287 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
emilmont 10:3bc89ef62ce7 288
emilmont 10:3bc89ef62ce7 289 #else
emilmont 10:3bc89ef62ce7 290 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
emilmont 10:3bc89ef62ce7 291 #endif // CLOCK_SETUP
emilmont 10:3bc89ef62ce7 292
emilmont 10:3bc89ef62ce7 293
emilmont 10:3bc89ef62ce7 294 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 295 Clock Variable definitions
emilmont 10:3bc89ef62ce7 296 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 297 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
emilmont 10:3bc89ef62ce7 298
emilmont 10:3bc89ef62ce7 299
emilmont 10:3bc89ef62ce7 300 /*----------------------------------------------------------------------------
emilmont 10:3bc89ef62ce7 301 Clock functions
emilmont 10:3bc89ef62ce7 302 *----------------------------------------------------------------------------*/
emilmont 10:3bc89ef62ce7 303 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
emilmont 10:3bc89ef62ce7 304 {
emilmont 10:3bc89ef62ce7 305 uint32_t wdt_osc = 0;
emilmont 10:3bc89ef62ce7 306
emilmont 10:3bc89ef62ce7 307 /* Determine clock frequency according to clock register values */
emilmont 10:3bc89ef62ce7 308 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
emilmont 10:3bc89ef62ce7 309 case 0: wdt_osc = 0; break;
emilmont 10:3bc89ef62ce7 310 case 1: wdt_osc = 500000; break;
emilmont 10:3bc89ef62ce7 311 case 2: wdt_osc = 800000; break;
emilmont 10:3bc89ef62ce7 312 case 3: wdt_osc = 1100000; break;
emilmont 10:3bc89ef62ce7 313 case 4: wdt_osc = 1400000; break;
emilmont 10:3bc89ef62ce7 314 case 5: wdt_osc = 1600000; break;
emilmont 10:3bc89ef62ce7 315 case 6: wdt_osc = 1800000; break;
emilmont 10:3bc89ef62ce7 316 case 7: wdt_osc = 2000000; break;
emilmont 10:3bc89ef62ce7 317 case 8: wdt_osc = 2200000; break;
emilmont 10:3bc89ef62ce7 318 case 9: wdt_osc = 2400000; break;
emilmont 10:3bc89ef62ce7 319 case 10: wdt_osc = 2600000; break;
emilmont 10:3bc89ef62ce7 320 case 11: wdt_osc = 2700000; break;
emilmont 10:3bc89ef62ce7 321 case 12: wdt_osc = 2900000; break;
emilmont 10:3bc89ef62ce7 322 case 13: wdt_osc = 3100000; break;
emilmont 10:3bc89ef62ce7 323 case 14: wdt_osc = 3200000; break;
emilmont 10:3bc89ef62ce7 324 case 15: wdt_osc = 3400000; break;
emilmont 10:3bc89ef62ce7 325 }
emilmont 10:3bc89ef62ce7 326 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
emilmont 10:3bc89ef62ce7 327
emilmont 10:3bc89ef62ce7 328 switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
emilmont 10:3bc89ef62ce7 329 case 0: /* Internal RC oscillator */
emilmont 10:3bc89ef62ce7 330 SystemCoreClock = __IRC_OSC_CLK;
emilmont 10:3bc89ef62ce7 331 break;
emilmont 10:3bc89ef62ce7 332 case 1: /* Input Clock to System PLL */
emilmont 10:3bc89ef62ce7 333 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
emilmont 10:3bc89ef62ce7 334 case 0: /* Internal RC oscillator */
emilmont 10:3bc89ef62ce7 335 SystemCoreClock = __IRC_OSC_CLK;
emilmont 10:3bc89ef62ce7 336 break;
emilmont 10:3bc89ef62ce7 337 case 1: /* System oscillator */
emilmont 10:3bc89ef62ce7 338 SystemCoreClock = __SYS_OSC_CLK;
emilmont 10:3bc89ef62ce7 339 break;
emilmont 10:3bc89ef62ce7 340 case 2: /* Reserved */
emilmont 10:3bc89ef62ce7 341 case 3: /* Reserved */
emilmont 10:3bc89ef62ce7 342 SystemCoreClock = 0;
emilmont 10:3bc89ef62ce7 343 break;
emilmont 10:3bc89ef62ce7 344 }
emilmont 10:3bc89ef62ce7 345 break;
emilmont 10:3bc89ef62ce7 346 case 2: /* WDT Oscillator */
emilmont 10:3bc89ef62ce7 347 SystemCoreClock = wdt_osc;
emilmont 10:3bc89ef62ce7 348 break;
emilmont 10:3bc89ef62ce7 349 case 3: /* System PLL Clock Out */
emilmont 10:3bc89ef62ce7 350 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
emilmont 10:3bc89ef62ce7 351 case 0: /* Internal RC oscillator */
emilmont 10:3bc89ef62ce7 352 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
emilmont 10:3bc89ef62ce7 353 SystemCoreClock = __IRC_OSC_CLK;
emilmont 10:3bc89ef62ce7 354 } else {
emilmont 10:3bc89ef62ce7 355 SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
emilmont 10:3bc89ef62ce7 356 }
emilmont 10:3bc89ef62ce7 357 break;
emilmont 10:3bc89ef62ce7 358 case 1: /* System oscillator */
emilmont 10:3bc89ef62ce7 359 if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
emilmont 10:3bc89ef62ce7 360 SystemCoreClock = __SYS_OSC_CLK;
emilmont 10:3bc89ef62ce7 361 } else {
emilmont 10:3bc89ef62ce7 362 SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
emilmont 10:3bc89ef62ce7 363 }
emilmont 10:3bc89ef62ce7 364 break;
emilmont 10:3bc89ef62ce7 365 case 2: /* Reserved */
emilmont 10:3bc89ef62ce7 366 case 3: /* Reserved */
emilmont 10:3bc89ef62ce7 367 SystemCoreClock = 0;
emilmont 10:3bc89ef62ce7 368 break;
emilmont 10:3bc89ef62ce7 369 }
emilmont 10:3bc89ef62ce7 370 break;
emilmont 10:3bc89ef62ce7 371 }
emilmont 10:3bc89ef62ce7 372
emilmont 10:3bc89ef62ce7 373 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
emilmont 10:3bc89ef62ce7 374
emilmont 10:3bc89ef62ce7 375 }
emilmont 10:3bc89ef62ce7 376
emilmont 10:3bc89ef62ce7 377 /**
emilmont 10:3bc89ef62ce7 378 * Initialize the system
emilmont 10:3bc89ef62ce7 379 *
emilmont 10:3bc89ef62ce7 380 * @param none
emilmont 10:3bc89ef62ce7 381 * @return none
emilmont 10:3bc89ef62ce7 382 *
emilmont 10:3bc89ef62ce7 383 * @brief Setup the microcontroller system.
emilmont 10:3bc89ef62ce7 384 * Initialize the System.
emilmont 10:3bc89ef62ce7 385 */
emilmont 10:3bc89ef62ce7 386 void SystemInit (void) {
emilmont 10:3bc89ef62ce7 387 volatile uint32_t i;
emilmont 10:3bc89ef62ce7 388
emilmont 10:3bc89ef62ce7 389 #if (CLOCK_SETUP) /* Clock Setup */
emilmont 10:3bc89ef62ce7 390
emilmont 10:3bc89ef62ce7 391 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
emilmont 10:3bc89ef62ce7 392 LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
emilmont 10:3bc89ef62ce7 393 LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
emilmont 10:3bc89ef62ce7 394 for (i = 0; i < 200; i++) __NOP();
emilmont 10:3bc89ef62ce7 395 #endif
emilmont 10:3bc89ef62ce7 396
emilmont 10:3bc89ef62ce7 397 LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
emilmont 10:3bc89ef62ce7 398 LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
emilmont 10:3bc89ef62ce7 399 LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
emilmont 10:3bc89ef62ce7 400 LPC_SYSCON->SYSPLLCLKUEN = 0x01;
emilmont 10:3bc89ef62ce7 401 while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
emilmont 10:3bc89ef62ce7 402 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
emilmont 10:3bc89ef62ce7 403 LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
emilmont 10:3bc89ef62ce7 404 LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
emilmont 10:3bc89ef62ce7 405 while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
emilmont 10:3bc89ef62ce7 406 #endif
emilmont 10:3bc89ef62ce7 407
emilmont 10:3bc89ef62ce7 408 #if (((MAINCLKSEL_Val & 0x03) == 2) )
emilmont 10:3bc89ef62ce7 409 LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
emilmont 10:3bc89ef62ce7 410 LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
emilmont 10:3bc89ef62ce7 411 for (i = 0; i < 200; i++) __NOP();
emilmont 10:3bc89ef62ce7 412 #endif
emilmont 10:3bc89ef62ce7 413
emilmont 10:3bc89ef62ce7 414 LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
emilmont 10:3bc89ef62ce7 415 LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
emilmont 10:3bc89ef62ce7 416 LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
emilmont 10:3bc89ef62ce7 417 LPC_SYSCON->MAINCLKUEN = 0x01;
emilmont 10:3bc89ef62ce7 418 while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
emilmont 10:3bc89ef62ce7 419
emilmont 10:3bc89ef62ce7 420 LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
emilmont 10:3bc89ef62ce7 421
emilmont 10:3bc89ef62ce7 422 #if ((USBCLKDIV_Val & 0x1FF) != 0) /* USB clock is used */
emilmont 10:3bc89ef62ce7 423 LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
emilmont 10:3bc89ef62ce7 424
emilmont 10:3bc89ef62ce7 425 #if ((USBCLKSEL_Val & 0x003) == 0) /* USB clock is USB PLL out */
emilmont 10:3bc89ef62ce7 426 LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
emilmont 10:3bc89ef62ce7 427 LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
emilmont 10:3bc89ef62ce7 428 LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
emilmont 10:3bc89ef62ce7 429 LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
emilmont 10:3bc89ef62ce7 430 LPC_SYSCON->USBPLLCLKUEN = 0x01;
emilmont 10:3bc89ef62ce7 431 while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
emilmont 10:3bc89ef62ce7 432 LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
emilmont 10:3bc89ef62ce7 433 while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
emilmont 10:3bc89ef62ce7 434 LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
emilmont 10:3bc89ef62ce7 435 #endif
emilmont 10:3bc89ef62ce7 436
emilmont 10:3bc89ef62ce7 437 LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
emilmont 10:3bc89ef62ce7 438 LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
emilmont 10:3bc89ef62ce7 439
emilmont 10:3bc89ef62ce7 440 #else /* USB clock is not used */
emilmont 10:3bc89ef62ce7 441 LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
emilmont 10:3bc89ef62ce7 442 LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
emilmont 10:3bc89ef62ce7 443 #endif
emilmont 10:3bc89ef62ce7 444
emilmont 10:3bc89ef62ce7 445 #endif
emilmont 10:3bc89ef62ce7 446
emilmont 10:3bc89ef62ce7 447 /* System clock to the IOCON needs to be enabled or
emilmont 10:3bc89ef62ce7 448 most of the I/O related peripherals won't work. */
emilmont 10:3bc89ef62ce7 449 LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16);
emilmont 10:3bc89ef62ce7 450 }