pmu_11xx.h

00001 /*
00002  * @brief LPC11xx PMU chip driver
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2012
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 #ifndef __PMU_11XX_H_
00033 #define __PMU_11XX_H_
00034 
00035 #ifdef __cplusplus
00036 extern "C" {
00037 #endif
00038 
00039 /** @defgroup PMU_11XX CHIP: LPC11xx Power Management Unit block driver
00040  * @ingroup CHIP_11XX_Drivers
00041  * This driver only applies to devices in the CHIP_LPC11AXX, CHIP_LPC11CXX,
00042  * CHIP_LPC11EXX, CHIP_LPC11UXX, and CHIP_LPC1125 families. Note different
00043  * families may have slightly different PMU support.
00044  * @{
00045  */
00046 
00047 #if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)
00048 #if defined(CHIP_LPC1125)
00049 #error "LPC1125 support for the PMU driver is not ready"
00050 #endif
00051  
00052 /**
00053  * @brief LPC11xx Power Management Unit register block structure
00054  */
00055 typedef struct {
00056     __IO uint32_t PCON ;     /*!< Offset: 0x000 Power control Register (R/W) */
00057     __IO uint32_t GPREG[4]; /*!< Offset: 0x004 General purpose Registers 0..3 (R/W) */
00058 } LPC_PMU_T;
00059 
00060 /**
00061  * @brief LPC11xx low power mode type definitions
00062  */
00063 typedef enum CHIP_PMU_MCUPOWER {
00064     PMU_MCU_SLEEP  = 0,          /*!< Sleep mode */
00065 #if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
00066     PMU_MCU_DEEP_SLEEP ,         /*!< Deep Sleep mode */
00067     PMU_MCU_POWER_DOWN ,         /*!< Power down mode */
00068     PMU_MCU_DEEP_PWRDOWN         /*!< Deep power down mode */
00069 #elif defined(CHIP_LPC11CXX)
00070     PMU_MCU_DEEP_PWRDOWN  = 3    /*!< Deep power down mode */
00071 #endif
00072 } CHIP_PMU_MCUPOWER_T;
00073 
00074 /**
00075  * PMU PCON register bit fields & masks
00076  */
00077 #define PMU_PCON_PM_SLEEP           (0x0)       /*!< ARM WFI enter sleep mode */
00078 #if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
00079 #define PMU_PCON_PM_DEEPSLEEP       (0x1)       /*!< ARM WFI enter Deep-sleep mode */
00080 #define PMU_PCON_PM_POWERDOWN       (0x2)       /*!< ARM WFI enter Power-down mode */
00081 #define PMU_PCON_PM_DEEPPOWERDOWN   (0x3)       /*!< ARM WFI enter Deep Power-down mode */
00082 #elif defined(CHIP_LPC11CXX)
00083 #define PMU_PCON_PM_DEEPPOWERDOWN   (0x2)
00084 #endif
00085 #define PMU_PCON_SLEEPFLAG          (1 << 8)    /*!< Sleep mode flag */
00086 #define PMU_PCON_DPDFLAG            (1 << 11)   /*!< Deep power-down flag */
00087 
00088 /**
00089  * @brief   Write a value to a GPREG register
00090  * @param   pPMU        : Pointer to PMU register block
00091  * @param   regIndex    : Register index to write to, must be 0..3
00092  * @param   value       : Value to write
00093  * @return  None
00094  */
00095 STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value)
00096 {
00097     pPMU->GPREG [regIndex] = value;
00098 }
00099 
00100 /**
00101  * @brief   Read a value to a GPREG register
00102  * @param   pPMU        : Pointer to PMU register block
00103  * @param   regIndex    : Register index to read from, must be 0..3
00104  * @return  Value read from the GPREG register
00105  */
00106 STATIC INLINE uint32_t Chip_PMU_ReadGPREG(LPC_PMU_T *pPMU, uint8_t regIndex)
00107 {
00108     return pPMU->GPREG [regIndex];
00109 }
00110 
00111 /**
00112  * @brief   Enter MCU Sleep mode
00113  * @param   pPMU    : Pointer to PMU register block
00114  * @return  None
00115  * @note    The sleep mode affects the ARM Cortex-M0+ core only. Peripherals
00116  * and memories are active. 
00117  */
00118 void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
00119 
00120 #if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
00121 /**
00122  * @brief   Enter MCU Deep Sleep mode
00123  * @param   pPMU    : Pointer to PMU register block
00124  * @return  None
00125  * @note    In Deep-sleep mode, the peripherals receive no internal clocks.
00126  * The flash is in stand-by mode. The SRAM memory and all peripheral registers
00127  * as well as the processor maintain their internal states. The WWDT, WKT,
00128  * and BOD can remain active to wake up the system on an interrupt.
00129  */
00130 void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU);
00131 
00132 /**
00133  * @brief   Enter MCU Power down mode
00134  * @param   pPMU    : Pointer to PMU register block
00135  * @return  None
00136  * @note    In Power-down mode, the peripherals receive no internal clocks.
00137  * The internal SRAM memory and all peripheral registers as well as the
00138  * processor maintain their internal states. The flash memory is powered
00139  * down. The WWDT, WKT, and BOD can remain active to wake up the system
00140  * on an interrupt.
00141  */
00142 void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU);
00143 #endif
00144 
00145 /**
00146  * @brief   Enter MCU Deep Power down mode
00147  * @param   pPMU    : Pointer to PMU register block
00148  * @return  None
00149  * @note    For maximal power savings, the entire system is shut down
00150  * except for the general purpose registers in the PMU and the self
00151  * wake-up timer. Only the general purpose registers in the PMU maintain
00152  * their internal states. The part can wake up on a pulse on the WAKEUP
00153  * pin or when the self wake-up timer times out. On wake-up, the part
00154  * reboots.
00155  */
00156 void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU);
00157 
00158 /**
00159  * @brief   Place the MCU in a low power state
00160  * @param   pPMU        : Pointer to PMU register block
00161  * @param   SleepMode   : Sleep mode
00162  * @return  None
00163  */
00164 void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
00165 
00166 /**
00167  * @brief   Returns sleep/power-down flags
00168  * @param   pPMU    : Pointer to PMU register block
00169  * @return  Or'ed values of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
00170  * @note    These indicate that the PMU is setup for entry into a low
00171  * power state on the next WFI() instruction.
00172  */
00173 STATIC INLINE uint32_t Chip_PMU_GetSleepFlags(LPC_PMU_T *pPMU)
00174 {
00175     return (pPMU->PCON  & (PMU_PCON_SLEEPFLAG | PMU_PCON_DPDFLAG));
00176 }
00177 
00178 /**
00179  * @brief   Clears sleep/power-down flags
00180  * @param   pPMU    : Pointer to PMU register block
00181  * @param   flags   : Or'ed value of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
00182  * @return  Nothing
00183  * @note    Use this function to clear a low power state prior to calling
00184  * WFI().
00185  */
00186 STATIC INLINE void Chip_PMU_ClearSleepFlags(LPC_PMU_T *pPMU, uint32_t flags)
00187 {
00188     pPMU->PCON  &= ~flags;
00189 }
00190 
00191 #endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || ... */
00192 
00193 /**
00194  * @}
00195  */
00196 
00197 #ifdef __cplusplus
00198 }
00199 #endif
00200 
00201 #endif /* __PMU_11XX_H_ */