Diff: rtx/TARGET_CORTEX_A/RTX_Conf_CA.c

Revision:

109:3b7dd22a5b25

Parent:

107:bdd541595fc5

Child:

119:6635230e06ba

--- a/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c	Tue Apr 26 17:15:29 2016 +0100
+++ b/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c	Fri Apr 29 01:15:35 2016 +0100
@@ -117,7 +117,7 @@
 //   <i> Defines the timer clock value.
 //   <i> Default: 12000000  (12MHz)
 #ifndef OS_CLOCK
-#  if defined(TARGET_RZ_A1H)
+#  if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
  #define OS_CLOCK       12000000
 #  else
 #    error "no target defined"
@@ -234,7 +234,7 @@
 #if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
 
 /*--------------------------- os_tick_init ----------------------------------*/
-#ifdef TARGET_RZ_A1H
+#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
 #define OSTM0   (0xFCFEC000uL) /* OSTM0 */
 #define OSTM1   (0xFCFEC400uL) /* OSTM1 */
 #define CPG     (0xFCFE0410uL) /* CPG */
@@ -275,7 +275,7 @@
 // Initialize alternative hardware timer as RTX kernel timer
 // Return: IRQ number of the alternative hardware timer
 int os_tick_init (void) {
-#ifdef TARGET_RZ_A1H
+#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H)
   CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); /* enable OSTM0 clock */
 
   OSTM0TT   = 0x1;    /* Stop the counter and clears the OSTM0TE bit.     */