Emilio Salomone / X_NUCLEO_IKS01A2

Dependencies:   ST_INTERFACES X_NUCLEO_COMMON

Fork of X_NUCLEO_IKS01A2 by ST

Committer:
davide.aliprandi@st.com
Date:
Tue Mar 14 15:39:53 2017 +0100
Revision:
10:7ced1e5f49dc
Parent:
9:038121268b07
Renamed status_t into mems_status_t to avoid conflicts with other expansion boards.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nikapov 0:cad5dab2b21d 1 /**
nikapov 0:cad5dab2b21d 2 ******************************************************************************
davide.aliprandi@st.com 6:671fd10a51b7 3 * @file LSM303AGR_mag_driver.h
nikapov 0:cad5dab2b21d 4 * @author MEMS Application Team
nikapov 0:cad5dab2b21d 5 * @version V1.1
nikapov 0:cad5dab2b21d 6 * @date 25-February-2016
nikapov 0:cad5dab2b21d 7 * @brief LSM303AGR Magnetometer header driver file
nikapov 0:cad5dab2b21d 8 ******************************************************************************
nikapov 0:cad5dab2b21d 9 * @attention
nikapov 0:cad5dab2b21d 10 *
nikapov 0:cad5dab2b21d 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
nikapov 0:cad5dab2b21d 12 *
nikapov 0:cad5dab2b21d 13 * Redistribution and use in source and binary forms, with or without modification,
nikapov 0:cad5dab2b21d 14 * are permitted provided that the following conditions are met:
nikapov 0:cad5dab2b21d 15 * 1. Redistributions of source code must retain the above copyright notice,
nikapov 0:cad5dab2b21d 16 * this list of conditions and the following disclaimer.
nikapov 0:cad5dab2b21d 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
nikapov 0:cad5dab2b21d 18 * this list of conditions and the following disclaimer in the documentation
nikapov 0:cad5dab2b21d 19 * and/or other materials provided with the distribution.
nikapov 0:cad5dab2b21d 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
nikapov 0:cad5dab2b21d 21 * may be used to endorse or promote products derived from this software
nikapov 0:cad5dab2b21d 22 * without specific prior written permission.
nikapov 0:cad5dab2b21d 23 *
nikapov 0:cad5dab2b21d 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
nikapov 0:cad5dab2b21d 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
nikapov 0:cad5dab2b21d 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
nikapov 0:cad5dab2b21d 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
nikapov 0:cad5dab2b21d 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
nikapov 0:cad5dab2b21d 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
nikapov 0:cad5dab2b21d 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
nikapov 0:cad5dab2b21d 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
nikapov 0:cad5dab2b21d 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
nikapov 0:cad5dab2b21d 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
nikapov 0:cad5dab2b21d 34 *
nikapov 0:cad5dab2b21d 35 ******************************************************************************
nikapov 0:cad5dab2b21d 36 */
nikapov 0:cad5dab2b21d 37
nikapov 0:cad5dab2b21d 38 /* Define to prevent recursive inclusion -------------------------------------*/
nikapov 0:cad5dab2b21d 39 #ifndef __LSM303AGR_MAG_DRIVER__H
nikapov 0:cad5dab2b21d 40 #define __LSM303AGR_MAG_DRIVER__H
nikapov 0:cad5dab2b21d 41
nikapov 0:cad5dab2b21d 42 /* Includes ------------------------------------------------------------------*/
nikapov 0:cad5dab2b21d 43 #include <stdint.h>
nikapov 0:cad5dab2b21d 44
nikapov 0:cad5dab2b21d 45 /* Exported types ------------------------------------------------------------*/
nikapov 0:cad5dab2b21d 46
nikapov 0:cad5dab2b21d 47 #ifdef __cplusplus
nikapov 0:cad5dab2b21d 48 extern "C" {
nikapov 0:cad5dab2b21d 49 #endif
nikapov 0:cad5dab2b21d 50
nikapov 0:cad5dab2b21d 51 //these could change accordingly with the architecture
nikapov 0:cad5dab2b21d 52
nikapov 0:cad5dab2b21d 53 #ifndef __ARCHDEP__TYPES
nikapov 0:cad5dab2b21d 54 #define __ARCHDEP__TYPES
nikapov 0:cad5dab2b21d 55
nikapov 0:cad5dab2b21d 56 typedef unsigned char u8_t;
nikapov 0:cad5dab2b21d 57 typedef unsigned short int u16_t;
nikapov 0:cad5dab2b21d 58 typedef unsigned int u32_t;
nikapov 0:cad5dab2b21d 59 typedef int i32_t;
nikapov 0:cad5dab2b21d 60 typedef short int i16_t;
nikapov 0:cad5dab2b21d 61 typedef signed char i8_t;
nikapov 0:cad5dab2b21d 62
nikapov 0:cad5dab2b21d 63 #endif /*__ARCHDEP__TYPES*/
nikapov 0:cad5dab2b21d 64
nikapov 0:cad5dab2b21d 65 /* Exported common structure --------------------------------------------------------*/
nikapov 0:cad5dab2b21d 66
nikapov 0:cad5dab2b21d 67 #ifndef __SHARED__TYPES
nikapov 0:cad5dab2b21d 68 #define __SHARED__TYPES
nikapov 0:cad5dab2b21d 69
nikapov 0:cad5dab2b21d 70 typedef union{
nikapov 0:cad5dab2b21d 71 i16_t i16bit[3];
nikapov 0:cad5dab2b21d 72 u8_t u8bit[6];
nikapov 0:cad5dab2b21d 73 } Type3Axis16bit_U;
nikapov 0:cad5dab2b21d 74
nikapov 0:cad5dab2b21d 75 typedef union{
nikapov 0:cad5dab2b21d 76 i16_t i16bit;
nikapov 0:cad5dab2b21d 77 u8_t u8bit[2];
nikapov 0:cad5dab2b21d 78 } Type1Axis16bit_U;
nikapov 0:cad5dab2b21d 79
nikapov 0:cad5dab2b21d 80 typedef union{
nikapov 0:cad5dab2b21d 81 i32_t i32bit;
nikapov 0:cad5dab2b21d 82 u8_t u8bit[4];
nikapov 0:cad5dab2b21d 83 } Type1Axis32bit_U;
nikapov 0:cad5dab2b21d 84
nikapov 0:cad5dab2b21d 85 typedef enum {
nikapov 0:cad5dab2b21d 86 MEMS_SUCCESS = 0x01,
nikapov 0:cad5dab2b21d 87 MEMS_ERROR = 0x00
davide.aliprandi@st.com 10:7ced1e5f49dc 88 } mems_status_t;
nikapov 0:cad5dab2b21d 89
nikapov 0:cad5dab2b21d 90 #endif /*__SHARED__TYPES*/
nikapov 0:cad5dab2b21d 91
nikapov 0:cad5dab2b21d 92 /* Exported macro ------------------------------------------------------------*/
nikapov 0:cad5dab2b21d 93
nikapov 0:cad5dab2b21d 94 /* Exported constants --------------------------------------------------------*/
nikapov 0:cad5dab2b21d 95
nikapov 0:cad5dab2b21d 96 /************** I2C Address *****************/
nikapov 0:cad5dab2b21d 97
nikapov 0:cad5dab2b21d 98 #define LSM303AGR_MAG_I2C_ADDRESS 0x3C
nikapov 0:cad5dab2b21d 99
nikapov 0:cad5dab2b21d 100 /************** Who am I *******************/
nikapov 0:cad5dab2b21d 101
nikapov 0:cad5dab2b21d 102 #define LSM303AGR_MAG_WHO_AM_I 0x40
nikapov 0:cad5dab2b21d 103
nikapov 0:cad5dab2b21d 104 /* Private Function Prototype -------------------------------------------------------*/
nikapov 0:cad5dab2b21d 105
nikapov 0:cad5dab2b21d 106 void LSM303AGR_MAG_SwapHighLowByte(u8_t *bufferToSwap, u8_t numberOfByte, u8_t dimension);
nikapov 0:cad5dab2b21d 107
nikapov 0:cad5dab2b21d 108 /* Public Function Prototypes -------------------------------------------------------*/
nikapov 0:cad5dab2b21d 109
davide.aliprandi@st.com 10:7ced1e5f49dc 110 mems_status_t LSM303AGR_MAG_read_reg( void *handle, u8_t Reg, u8_t* Data );
davide.aliprandi@st.com 10:7ced1e5f49dc 111 mems_status_t LSM303AGR_MAG_write_reg( void *handle, u8_t Reg, u8_t Data );
nikapov 0:cad5dab2b21d 112
nikapov 0:cad5dab2b21d 113
nikapov 0:cad5dab2b21d 114 /************** Device Register *******************/
nikapov 0:cad5dab2b21d 115 #define LSM303AGR_MAG_OFFSET_X_REG_L 0X45
nikapov 0:cad5dab2b21d 116 #define LSM303AGR_MAG_OFFSET_X_REG_H 0X46
nikapov 0:cad5dab2b21d 117 #define LSM303AGR_MAG_OFFSET_Y_REG_L 0X47
nikapov 0:cad5dab2b21d 118 #define LSM303AGR_MAG_OFFSET_Y_REG_H 0X48
nikapov 0:cad5dab2b21d 119 #define LSM303AGR_MAG_OFFSET_Z_REG_L 0X49
nikapov 0:cad5dab2b21d 120 #define LSM303AGR_MAG_OFFSET_Z_REG_H 0X4A
nikapov 0:cad5dab2b21d 121 #define LSM303AGR_MAG_WHO_AM_I_REG 0X4F
nikapov 0:cad5dab2b21d 122 #define LSM303AGR_MAG_CFG_REG_A 0X60
nikapov 0:cad5dab2b21d 123 #define LSM303AGR_MAG_CFG_REG_B 0X61
nikapov 0:cad5dab2b21d 124 #define LSM303AGR_MAG_CFG_REG_C 0X62
nikapov 0:cad5dab2b21d 125 #define LSM303AGR_MAG_INT_CTRL_REG 0X63
nikapov 0:cad5dab2b21d 126 #define LSM303AGR_MAG_INT_SOURCE_REG 0X64
nikapov 0:cad5dab2b21d 127 #define LSM303AGR_MAG_INT_THS_L_REG 0X65
nikapov 0:cad5dab2b21d 128 #define LSM303AGR_MAG_INT_THS_H_REG 0X66
nikapov 0:cad5dab2b21d 129 #define LSM303AGR_MAG_STATUS_REG 0X67
nikapov 0:cad5dab2b21d 130 #define LSM303AGR_MAG_OUTX_L_REG 0X68
nikapov 0:cad5dab2b21d 131 #define LSM303AGR_MAG_OUTX_H_REG 0X69
nikapov 0:cad5dab2b21d 132 #define LSM303AGR_MAG_OUTY_L_REG 0X6A
nikapov 0:cad5dab2b21d 133 #define LSM303AGR_MAG_OUTY_H_REG 0X6B
nikapov 0:cad5dab2b21d 134 #define LSM303AGR_MAG_OUTZ_L_REG 0X6C
nikapov 0:cad5dab2b21d 135 #define LSM303AGR_MAG_OUTZ_H_REG 0X6D
nikapov 0:cad5dab2b21d 136
nikapov 0:cad5dab2b21d 137 /*******************************************************************************
nikapov 0:cad5dab2b21d 138 * Register : OFFSET_X_REG_L
nikapov 0:cad5dab2b21d 139 * Address : 0X45
nikapov 0:cad5dab2b21d 140 * Bit Group Name: OFF_X_L
nikapov 0:cad5dab2b21d 141 * Permission : RW
nikapov 0:cad5dab2b21d 142 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 143 #define LSM303AGR_MAG_OFF_X_L_MASK 0xFF
davide.aliprandi@st.com 10:7ced1e5f49dc 144 #define LSM303AGR_MAG_OFF_X_L_POSITION 0
davide.aliprandi@st.com 10:7ced1e5f49dc 145 mems_status_t LSM303AGR_MAG_W_OFF_X_L(void *handle, u8_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 146 mems_status_t LSM303AGR_MAG_R_OFF_X_L(void *handle, u8_t *value);
nikapov 0:cad5dab2b21d 147
nikapov 0:cad5dab2b21d 148 /*******************************************************************************
nikapov 0:cad5dab2b21d 149 * Register : OFFSET_X_REG_H
nikapov 0:cad5dab2b21d 150 * Address : 0X46
nikapov 0:cad5dab2b21d 151 * Bit Group Name: OFF_X_H
nikapov 0:cad5dab2b21d 152 * Permission : RW
nikapov 0:cad5dab2b21d 153 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 154 #define LSM303AGR_MAG_OFF_X_H_MASK 0xFF
davide.aliprandi@st.com 10:7ced1e5f49dc 155 #define LSM303AGR_MAG_OFF_X_H_POSITION 0
davide.aliprandi@st.com 10:7ced1e5f49dc 156 mems_status_t LSM303AGR_MAG_W_OFF_X_H(void *handle, u8_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 157 mems_status_t LSM303AGR_MAG_R_OFF_X_H(void *handle, u8_t *value);
nikapov 0:cad5dab2b21d 158
nikapov 0:cad5dab2b21d 159 /*******************************************************************************
nikapov 0:cad5dab2b21d 160 * Register : OFFSET_Y_REG_L
nikapov 0:cad5dab2b21d 161 * Address : 0X47
nikapov 0:cad5dab2b21d 162 * Bit Group Name: OFF_Y_L
nikapov 0:cad5dab2b21d 163 * Permission : RW
nikapov 0:cad5dab2b21d 164 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 165 #define LSM303AGR_MAG_OFF_Y_L_MASK 0xFF
davide.aliprandi@st.com 10:7ced1e5f49dc 166 #define LSM303AGR_MAG_OFF_Y_L_POSITION 0
davide.aliprandi@st.com 10:7ced1e5f49dc 167 mems_status_t LSM303AGR_MAG_W_OFF_Y_L(void *handle, u8_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 168 mems_status_t LSM303AGR_MAG_R_OFF_Y_L(void *handle, u8_t *value);
nikapov 0:cad5dab2b21d 169
nikapov 0:cad5dab2b21d 170 /*******************************************************************************
nikapov 0:cad5dab2b21d 171 * Register : OFFSET_Y_REG_H
nikapov 0:cad5dab2b21d 172 * Address : 0X48
nikapov 0:cad5dab2b21d 173 * Bit Group Name: OFF_Y_H
nikapov 0:cad5dab2b21d 174 * Permission : RW
nikapov 0:cad5dab2b21d 175 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 176 #define LSM303AGR_MAG_OFF_Y_H_MASK 0xFF
davide.aliprandi@st.com 10:7ced1e5f49dc 177 #define LSM303AGR_MAG_OFF_Y_H_POSITION 0
davide.aliprandi@st.com 10:7ced1e5f49dc 178 mems_status_t LSM303AGR_MAG_W_OFF_Y_H(void *handle, u8_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 179 mems_status_t LSM303AGR_MAG_R_OFF_Y_H(void *handle, u8_t *value);
nikapov 0:cad5dab2b21d 180
nikapov 0:cad5dab2b21d 181 /*******************************************************************************
nikapov 0:cad5dab2b21d 182 * Register : OFFSET_Z_REG_L
nikapov 0:cad5dab2b21d 183 * Address : 0X49
nikapov 0:cad5dab2b21d 184 * Bit Group Name: OFF_Z_L
nikapov 0:cad5dab2b21d 185 * Permission : RW
nikapov 0:cad5dab2b21d 186 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 187 #define LSM303AGR_MAG_OFF_Z_L_MASK 0xFF
davide.aliprandi@st.com 10:7ced1e5f49dc 188 #define LSM303AGR_MAG_OFF_Z_L_POSITION 0
davide.aliprandi@st.com 10:7ced1e5f49dc 189 mems_status_t LSM303AGR_MAG_W_OFF_Z_L(void *handle, u8_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 190 mems_status_t LSM303AGR_MAG_R_OFF_Z_L(void *handle, u8_t *value);
nikapov 0:cad5dab2b21d 191
nikapov 0:cad5dab2b21d 192 /*******************************************************************************
nikapov 0:cad5dab2b21d 193 * Register : OFFSET_Z_REG_H
nikapov 0:cad5dab2b21d 194 * Address : 0X4A
nikapov 0:cad5dab2b21d 195 * Bit Group Name: OFF_Z_H
nikapov 0:cad5dab2b21d 196 * Permission : RW
nikapov 0:cad5dab2b21d 197 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 198 #define LSM303AGR_MAG_OFF_Z_H_MASK 0xFF
davide.aliprandi@st.com 10:7ced1e5f49dc 199 #define LSM303AGR_MAG_OFF_Z_H_POSITION 0
davide.aliprandi@st.com 10:7ced1e5f49dc 200 mems_status_t LSM303AGR_MAG_W_OFF_Z_H(void *handle, u8_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 201 mems_status_t LSM303AGR_MAG_R_OFF_Z_H(void *handle, u8_t *value);
nikapov 0:cad5dab2b21d 202
nikapov 0:cad5dab2b21d 203 /*******************************************************************************
nikapov 0:cad5dab2b21d 204 * Set/Get the Magnetic offsets
nikapov 0:cad5dab2b21d 205 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 206 mems_status_t LSM303AGR_MAG_Get_MagOff(void *handle, u16_t *magx_off, u16_t *magy_off, u16_t *magz_off);
davide.aliprandi@st.com 10:7ced1e5f49dc 207 mems_status_t LSM303AGR_MAG_Set_MagOff(void *handle, u16_t magx_off, u16_t magy_off, u16_t magz_off);
nikapov 0:cad5dab2b21d 208
nikapov 0:cad5dab2b21d 209 /*******************************************************************************
nikapov 0:cad5dab2b21d 210 * Register : WHO_AM_I_REG
nikapov 0:cad5dab2b21d 211 * Address : 0X4F
nikapov 0:cad5dab2b21d 212 * Bit Group Name: WHO_AM_I
nikapov 0:cad5dab2b21d 213 * Permission : RO
nikapov 0:cad5dab2b21d 214 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 215 #define LSM303AGR_MAG_WHO_AM_I_MASK 0xFF
davide.aliprandi@st.com 10:7ced1e5f49dc 216 #define LSM303AGR_MAG_WHO_AM_I_POSITION 0
davide.aliprandi@st.com 10:7ced1e5f49dc 217 mems_status_t LSM303AGR_MAG_R_WHO_AM_I(void *handle, u8_t *value);
nikapov 0:cad5dab2b21d 218
nikapov 0:cad5dab2b21d 219 /*******************************************************************************
nikapov 0:cad5dab2b21d 220 * Register : CFG_REG_A
nikapov 0:cad5dab2b21d 221 * Address : 0X60
nikapov 0:cad5dab2b21d 222 * Bit Group Name: MD
nikapov 0:cad5dab2b21d 223 * Permission : RW
nikapov 0:cad5dab2b21d 224 *******************************************************************************/
nikapov 0:cad5dab2b21d 225 typedef enum {
nikapov 0:cad5dab2b21d 226 LSM303AGR_MAG_MD_CONTINUOS_MODE =0x00,
nikapov 0:cad5dab2b21d 227 LSM303AGR_MAG_MD_SINGLE_MODE =0x01,
nikapov 0:cad5dab2b21d 228 LSM303AGR_MAG_MD_IDLE1_MODE =0x02,
nikapov 0:cad5dab2b21d 229 LSM303AGR_MAG_MD_IDLE2_MODE =0x03,
nikapov 0:cad5dab2b21d 230 } LSM303AGR_MAG_MD_t;
nikapov 0:cad5dab2b21d 231
davide.aliprandi@st.com 10:7ced1e5f49dc 232 #define LSM303AGR_MAG_MD_MASK 0x03
davide.aliprandi@st.com 10:7ced1e5f49dc 233 mems_status_t LSM303AGR_MAG_W_MD(void *handle, LSM303AGR_MAG_MD_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 234 mems_status_t LSM303AGR_MAG_R_MD(void *handle, LSM303AGR_MAG_MD_t *value);
nikapov 0:cad5dab2b21d 235
nikapov 0:cad5dab2b21d 236 /*******************************************************************************
nikapov 0:cad5dab2b21d 237 * Register : CFG_REG_A
nikapov 0:cad5dab2b21d 238 * Address : 0X60
nikapov 0:cad5dab2b21d 239 * Bit Group Name: ODR
nikapov 0:cad5dab2b21d 240 * Permission : RW
nikapov 0:cad5dab2b21d 241 *******************************************************************************/
nikapov 0:cad5dab2b21d 242 typedef enum {
nikapov 0:cad5dab2b21d 243 LSM303AGR_MAG_ODR_10Hz =0x00,
nikapov 0:cad5dab2b21d 244 LSM303AGR_MAG_ODR_20Hz =0x04,
nikapov 0:cad5dab2b21d 245 LSM303AGR_MAG_ODR_50Hz =0x08,
nikapov 0:cad5dab2b21d 246 LSM303AGR_MAG_ODR_100Hz =0x0C,
nikapov 0:cad5dab2b21d 247 } LSM303AGR_MAG_ODR_t;
nikapov 0:cad5dab2b21d 248
davide.aliprandi@st.com 10:7ced1e5f49dc 249 #define LSM303AGR_MAG_ODR_MASK 0x0C
davide.aliprandi@st.com 10:7ced1e5f49dc 250 mems_status_t LSM303AGR_MAG_W_ODR(void *handle, LSM303AGR_MAG_ODR_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 251 mems_status_t LSM303AGR_MAG_R_ODR(void *handle, LSM303AGR_MAG_ODR_t *value);
nikapov 0:cad5dab2b21d 252
nikapov 0:cad5dab2b21d 253 /*******************************************************************************
nikapov 0:cad5dab2b21d 254 * Register : CFG_REG_A
nikapov 0:cad5dab2b21d 255 * Address : 0X60
nikapov 0:cad5dab2b21d 256 * Bit Group Name: LP
nikapov 0:cad5dab2b21d 257 * Permission : RW
nikapov 0:cad5dab2b21d 258 *******************************************************************************/
nikapov 0:cad5dab2b21d 259 typedef enum {
nikapov 0:cad5dab2b21d 260 LSM303AGR_MAG_HR_MODE =0x00,
nikapov 0:cad5dab2b21d 261 LSM303AGR_MAG_LP_MODE =0x10,
nikapov 0:cad5dab2b21d 262 } LSM303AGR_MAG_LP_t;
nikapov 0:cad5dab2b21d 263
davide.aliprandi@st.com 10:7ced1e5f49dc 264 #define LSM303AGR_MAG_LP_MASK 0x10
davide.aliprandi@st.com 10:7ced1e5f49dc 265 mems_status_t LSM303AGR_MAG_W_LP(void *handle, LSM303AGR_MAG_LP_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 266 mems_status_t LSM303AGR_MAG_R_LP(void *handle, LSM303AGR_MAG_LP_t *value);
nikapov 0:cad5dab2b21d 267
nikapov 0:cad5dab2b21d 268 /*******************************************************************************
nikapov 0:cad5dab2b21d 269 * Register : CFG_REG_A
nikapov 0:cad5dab2b21d 270 * Address : 0X60
nikapov 0:cad5dab2b21d 271 * Bit Group Name: SOFT_RST
nikapov 0:cad5dab2b21d 272 * Permission : RW
nikapov 0:cad5dab2b21d 273 *******************************************************************************/
nikapov 0:cad5dab2b21d 274 typedef enum {
nikapov 0:cad5dab2b21d 275 LSM303AGR_MAG_SOFT_RST_DISABLED =0x00,
nikapov 0:cad5dab2b21d 276 LSM303AGR_MAG_SOFT_RST_ENABLED =0x20,
nikapov 0:cad5dab2b21d 277 } LSM303AGR_MAG_SOFT_RST_t;
nikapov 0:cad5dab2b21d 278
davide.aliprandi@st.com 10:7ced1e5f49dc 279 #define LSM303AGR_MAG_SOFT_RST_MASK 0x20
davide.aliprandi@st.com 10:7ced1e5f49dc 280 mems_status_t LSM303AGR_MAG_W_SOFT_RST(void *handle, LSM303AGR_MAG_SOFT_RST_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 281 mems_status_t LSM303AGR_MAG_R_SOFT_RST(void *handle, LSM303AGR_MAG_SOFT_RST_t *value);
nikapov 0:cad5dab2b21d 282
nikapov 0:cad5dab2b21d 283 /*******************************************************************************
nikapov 0:cad5dab2b21d 284 * Register : CFG_REG_B
nikapov 0:cad5dab2b21d 285 * Address : 0X61
nikapov 0:cad5dab2b21d 286 * Bit Group Name: LPF
nikapov 0:cad5dab2b21d 287 * Permission : RW
nikapov 0:cad5dab2b21d 288 *******************************************************************************/
nikapov 0:cad5dab2b21d 289 typedef enum {
nikapov 0:cad5dab2b21d 290 LSM303AGR_MAG_LPF_DISABLED =0x00,
nikapov 0:cad5dab2b21d 291 LSM303AGR_MAG_LPF_ENABLED =0x01,
nikapov 0:cad5dab2b21d 292 } LSM303AGR_MAG_LPF_t;
nikapov 0:cad5dab2b21d 293
davide.aliprandi@st.com 10:7ced1e5f49dc 294 #define LSM303AGR_MAG_LPF_MASK 0x01
davide.aliprandi@st.com 10:7ced1e5f49dc 295 mems_status_t LSM303AGR_MAG_W_LPF(void *handle, LSM303AGR_MAG_LPF_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 296 mems_status_t LSM303AGR_MAG_R_LPF(void *handle, LSM303AGR_MAG_LPF_t *value);
nikapov 0:cad5dab2b21d 297
nikapov 0:cad5dab2b21d 298 /*******************************************************************************
nikapov 0:cad5dab2b21d 299 * Register : CFG_REG_B
nikapov 0:cad5dab2b21d 300 * Address : 0X61
nikapov 0:cad5dab2b21d 301 * Bit Group Name: OFF_CANC
nikapov 0:cad5dab2b21d 302 * Permission : RW
nikapov 0:cad5dab2b21d 303 *******************************************************************************/
nikapov 0:cad5dab2b21d 304 typedef enum {
nikapov 0:cad5dab2b21d 305 LSM303AGR_MAG_OFF_CANC_DISABLED =0x00,
nikapov 0:cad5dab2b21d 306 LSM303AGR_MAG_OFF_CANC_ENABLED =0x02,
nikapov 0:cad5dab2b21d 307 } LSM303AGR_MAG_OFF_CANC_t;
nikapov 0:cad5dab2b21d 308
davide.aliprandi@st.com 10:7ced1e5f49dc 309 #define LSM303AGR_MAG_OFF_CANC_MASK 0x02
davide.aliprandi@st.com 10:7ced1e5f49dc 310 mems_status_t LSM303AGR_MAG_W_OFF_CANC(void *handle, LSM303AGR_MAG_OFF_CANC_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 311 mems_status_t LSM303AGR_MAG_R_OFF_CANC(void *handle, LSM303AGR_MAG_OFF_CANC_t *value);
nikapov 0:cad5dab2b21d 312
nikapov 0:cad5dab2b21d 313 /*******************************************************************************
nikapov 0:cad5dab2b21d 314 * Register : CFG_REG_B
nikapov 0:cad5dab2b21d 315 * Address : 0X61
nikapov 0:cad5dab2b21d 316 * Bit Group Name: SET_FREQ
nikapov 0:cad5dab2b21d 317 * Permission : RW
nikapov 0:cad5dab2b21d 318 *******************************************************************************/
nikapov 0:cad5dab2b21d 319 typedef enum {
nikapov 0:cad5dab2b21d 320 LSM303AGR_MAG_SET_FREQ_CONTINUOS =0x00,
nikapov 0:cad5dab2b21d 321 LSM303AGR_MAG_SET_FREQ_SINGLE =0x04,
nikapov 0:cad5dab2b21d 322 } LSM303AGR_MAG_SET_FREQ_t;
nikapov 0:cad5dab2b21d 323
davide.aliprandi@st.com 10:7ced1e5f49dc 324 #define LSM303AGR_MAG_SET_FREQ_MASK 0x04
davide.aliprandi@st.com 10:7ced1e5f49dc 325 mems_status_t LSM303AGR_MAG_W_SET_FREQ(void *handle, LSM303AGR_MAG_SET_FREQ_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 326 mems_status_t LSM303AGR_MAG_R_SET_FREQ(void *handle, LSM303AGR_MAG_SET_FREQ_t *value);
nikapov 0:cad5dab2b21d 327
nikapov 0:cad5dab2b21d 328 /*******************************************************************************
nikapov 0:cad5dab2b21d 329 * Register : CFG_REG_B
nikapov 0:cad5dab2b21d 330 * Address : 0X61
nikapov 0:cad5dab2b21d 331 * Bit Group Name: INT_ON_DATAOFF
nikapov 0:cad5dab2b21d 332 * Permission : RW
nikapov 0:cad5dab2b21d 333 *******************************************************************************/
nikapov 0:cad5dab2b21d 334 typedef enum {
nikapov 0:cad5dab2b21d 335 LSM303AGR_MAG_INT_ON_DATAOFF_DISABLED =0x00,
nikapov 0:cad5dab2b21d 336 LSM303AGR_MAG_INT_ON_DATAOFF_ENABLED =0x08,
nikapov 0:cad5dab2b21d 337 } LSM303AGR_MAG_INT_ON_DATAOFF_t;
nikapov 0:cad5dab2b21d 338
davide.aliprandi@st.com 10:7ced1e5f49dc 339 #define LSM303AGR_MAG_INT_ON_DATAOFF_MASK 0x08
davide.aliprandi@st.com 10:7ced1e5f49dc 340 mems_status_t LSM303AGR_MAG_W_INT_ON_DATAOFF(void *handle, LSM303AGR_MAG_INT_ON_DATAOFF_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 341 mems_status_t LSM303AGR_MAG_R_INT_ON_DATAOFF(void *handle, LSM303AGR_MAG_INT_ON_DATAOFF_t *value);
nikapov 0:cad5dab2b21d 342
nikapov 0:cad5dab2b21d 343 /*******************************************************************************
nikapov 0:cad5dab2b21d 344 * Register : CFG_REG_C
nikapov 0:cad5dab2b21d 345 * Address : 0X62
nikapov 0:cad5dab2b21d 346 * Bit Group Name: INT_MAG
nikapov 0:cad5dab2b21d 347 * Permission : RW
nikapov 0:cad5dab2b21d 348 *******************************************************************************/
nikapov 0:cad5dab2b21d 349 typedef enum {
nikapov 0:cad5dab2b21d 350 LSM303AGR_MAG_INT_MAG_DISABLED =0x00,
nikapov 0:cad5dab2b21d 351 LSM303AGR_MAG_INT_MAG_ENABLED =0x01,
nikapov 0:cad5dab2b21d 352 } LSM303AGR_MAG_INT_MAG_t;
nikapov 0:cad5dab2b21d 353
davide.aliprandi@st.com 10:7ced1e5f49dc 354 #define LSM303AGR_MAG_INT_MAG_MASK 0x01
davide.aliprandi@st.com 10:7ced1e5f49dc 355 mems_status_t LSM303AGR_MAG_W_INT_MAG(void *handle, LSM303AGR_MAG_INT_MAG_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 356 mems_status_t LSM303AGR_MAG_R_INT_MAG(void *handle, LSM303AGR_MAG_INT_MAG_t *value);
nikapov 0:cad5dab2b21d 357
nikapov 0:cad5dab2b21d 358 /*******************************************************************************
nikapov 0:cad5dab2b21d 359 * Register : CFG_REG_C
nikapov 0:cad5dab2b21d 360 * Address : 0X62
nikapov 0:cad5dab2b21d 361 * Bit Group Name: ST
nikapov 0:cad5dab2b21d 362 * Permission : RW
nikapov 0:cad5dab2b21d 363 *******************************************************************************/
nikapov 0:cad5dab2b21d 364 typedef enum {
nikapov 0:cad5dab2b21d 365 LSM303AGR_MAG_ST_DISABLED =0x00,
nikapov 0:cad5dab2b21d 366 LSM303AGR_MAG_ST_ENABLED =0x02,
nikapov 0:cad5dab2b21d 367 } LSM303AGR_MAG_ST_t;
nikapov 0:cad5dab2b21d 368
davide.aliprandi@st.com 10:7ced1e5f49dc 369 #define LSM303AGR_MAG_ST_MASK 0x02
davide.aliprandi@st.com 10:7ced1e5f49dc 370 mems_status_t LSM303AGR_MAG_W_ST(void *handle, LSM303AGR_MAG_ST_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 371 mems_status_t LSM303AGR_MAG_R_ST(void *handle, LSM303AGR_MAG_ST_t *value);
nikapov 0:cad5dab2b21d 372
nikapov 0:cad5dab2b21d 373 /*******************************************************************************
nikapov 0:cad5dab2b21d 374 * Register : CFG_REG_C
nikapov 0:cad5dab2b21d 375 * Address : 0X62
nikapov 0:cad5dab2b21d 376 * Bit Group Name: BLE
nikapov 0:cad5dab2b21d 377 * Permission : RW
nikapov 0:cad5dab2b21d 378 *******************************************************************************/
nikapov 0:cad5dab2b21d 379 typedef enum {
nikapov 0:cad5dab2b21d 380 LSM303AGR_MAG_BLE_DISABLED =0x00,
nikapov 0:cad5dab2b21d 381 LSM303AGR_MAG_BLE_ENABLED =0x08,
nikapov 0:cad5dab2b21d 382 } LSM303AGR_MAG_BLE_t;
nikapov 0:cad5dab2b21d 383
davide.aliprandi@st.com 10:7ced1e5f49dc 384 #define LSM303AGR_MAG_BLE_MASK 0x08
davide.aliprandi@st.com 10:7ced1e5f49dc 385 mems_status_t LSM303AGR_MAG_W_BLE(void *handle, LSM303AGR_MAG_BLE_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 386 mems_status_t LSM303AGR_MAG_R_BLE(void *handle, LSM303AGR_MAG_BLE_t *value);
nikapov 0:cad5dab2b21d 387
nikapov 0:cad5dab2b21d 388 /*******************************************************************************
nikapov 0:cad5dab2b21d 389 * Register : CFG_REG_C
nikapov 0:cad5dab2b21d 390 * Address : 0X62
nikapov 0:cad5dab2b21d 391 * Bit Group Name: BDU
nikapov 0:cad5dab2b21d 392 * Permission : RW
nikapov 0:cad5dab2b21d 393 *******************************************************************************/
nikapov 0:cad5dab2b21d 394 typedef enum {
nikapov 0:cad5dab2b21d 395 LSM303AGR_MAG_BDU_DISABLED =0x00,
nikapov 0:cad5dab2b21d 396 LSM303AGR_MAG_BDU_ENABLED =0x10,
nikapov 0:cad5dab2b21d 397 } LSM303AGR_MAG_BDU_t;
nikapov 0:cad5dab2b21d 398
davide.aliprandi@st.com 10:7ced1e5f49dc 399 #define LSM303AGR_MAG_BDU_MASK 0x10
davide.aliprandi@st.com 10:7ced1e5f49dc 400 mems_status_t LSM303AGR_MAG_W_BDU(void *handle, LSM303AGR_MAG_BDU_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 401 mems_status_t LSM303AGR_MAG_R_BDU(void *handle, LSM303AGR_MAG_BDU_t *value);
nikapov 0:cad5dab2b21d 402
nikapov 0:cad5dab2b21d 403 /*******************************************************************************
nikapov 0:cad5dab2b21d 404 * Register : CFG_REG_C
nikapov 0:cad5dab2b21d 405 * Address : 0X62
nikapov 0:cad5dab2b21d 406 * Bit Group Name: I2C_DIS
nikapov 0:cad5dab2b21d 407 * Permission : RW
nikapov 0:cad5dab2b21d 408 *******************************************************************************/
nikapov 0:cad5dab2b21d 409 typedef enum {
nikapov 0:cad5dab2b21d 410 LSM303AGR_MAG_I2C_ENABLED =0x00,
nikapov 0:cad5dab2b21d 411 LSM303AGR_MAG_I2C_DISABLED =0x20,
nikapov 0:cad5dab2b21d 412 } LSM303AGR_MAG_I2C_DIS_t;
nikapov 0:cad5dab2b21d 413
davide.aliprandi@st.com 10:7ced1e5f49dc 414 #define LSM303AGR_MAG_I2C_DIS_MASK 0x20
davide.aliprandi@st.com 10:7ced1e5f49dc 415 mems_status_t LSM303AGR_MAG_W_I2C_DIS(void *handle, LSM303AGR_MAG_I2C_DIS_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 416 mems_status_t LSM303AGR_MAG_R_I2C_DIS(void *handle, LSM303AGR_MAG_I2C_DIS_t *value);
nikapov 0:cad5dab2b21d 417
nikapov 0:cad5dab2b21d 418 /*******************************************************************************
nikapov 0:cad5dab2b21d 419 * Register : CFG_REG_C
nikapov 0:cad5dab2b21d 420 * Address : 0X62
nikapov 0:cad5dab2b21d 421 * Bit Group Name: INT_MAG_PIN
nikapov 0:cad5dab2b21d 422 * Permission : RW
nikapov 0:cad5dab2b21d 423 *******************************************************************************/
nikapov 0:cad5dab2b21d 424 typedef enum {
nikapov 0:cad5dab2b21d 425 LSM303AGR_MAG_INT_MAG_PIN_DISABLED =0x00,
nikapov 0:cad5dab2b21d 426 LSM303AGR_MAG_INT_MAG_PIN_ENABLED =0x40,
nikapov 0:cad5dab2b21d 427 } LSM303AGR_MAG_INT_MAG_PIN_t;
nikapov 0:cad5dab2b21d 428
davide.aliprandi@st.com 10:7ced1e5f49dc 429 #define LSM303AGR_MAG_INT_MAG_PIN_MASK 0x40
davide.aliprandi@st.com 10:7ced1e5f49dc 430 mems_status_t LSM303AGR_MAG_W_INT_MAG_PIN(void *handle, LSM303AGR_MAG_INT_MAG_PIN_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 431 mems_status_t LSM303AGR_MAG_R_INT_MAG_PIN(void *handle, LSM303AGR_MAG_INT_MAG_PIN_t *value);
nikapov 0:cad5dab2b21d 432
nikapov 0:cad5dab2b21d 433 /*******************************************************************************
nikapov 0:cad5dab2b21d 434 * Register : INT_CTRL_REG
nikapov 0:cad5dab2b21d 435 * Address : 0X63
nikapov 0:cad5dab2b21d 436 * Bit Group Name: IEN
nikapov 0:cad5dab2b21d 437 * Permission : RW
nikapov 0:cad5dab2b21d 438 *******************************************************************************/
nikapov 0:cad5dab2b21d 439 typedef enum {
nikapov 0:cad5dab2b21d 440 LSM303AGR_MAG_IEN_DISABLED =0x00,
nikapov 0:cad5dab2b21d 441 LSM303AGR_MAG_IEN_ENABLED =0x01,
nikapov 0:cad5dab2b21d 442 } LSM303AGR_MAG_IEN_t;
nikapov 0:cad5dab2b21d 443
davide.aliprandi@st.com 10:7ced1e5f49dc 444 #define LSM303AGR_MAG_IEN_MASK 0x01
davide.aliprandi@st.com 10:7ced1e5f49dc 445 mems_status_t LSM303AGR_MAG_W_IEN(void *handle, LSM303AGR_MAG_IEN_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 446 mems_status_t LSM303AGR_MAG_R_IEN(void *handle, LSM303AGR_MAG_IEN_t *value);
nikapov 0:cad5dab2b21d 447
nikapov 0:cad5dab2b21d 448 /*******************************************************************************
nikapov 0:cad5dab2b21d 449 * Register : INT_CTRL_REG
nikapov 0:cad5dab2b21d 450 * Address : 0X63
nikapov 0:cad5dab2b21d 451 * Bit Group Name: IEL
nikapov 0:cad5dab2b21d 452 * Permission : RW
nikapov 0:cad5dab2b21d 453 *******************************************************************************/
nikapov 0:cad5dab2b21d 454 typedef enum {
nikapov 0:cad5dab2b21d 455 LSM303AGR_MAG_IEL_PULSED =0x00,
nikapov 0:cad5dab2b21d 456 LSM303AGR_MAG_IEL_LATCHED =0x02,
nikapov 0:cad5dab2b21d 457 } LSM303AGR_MAG_IEL_t;
nikapov 0:cad5dab2b21d 458
davide.aliprandi@st.com 10:7ced1e5f49dc 459 #define LSM303AGR_MAG_IEL_MASK 0x02
davide.aliprandi@st.com 10:7ced1e5f49dc 460 mems_status_t LSM303AGR_MAG_W_IEL(void *handle, LSM303AGR_MAG_IEL_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 461 mems_status_t LSM303AGR_MAG_R_IEL(void *handle, LSM303AGR_MAG_IEL_t *value);
nikapov 0:cad5dab2b21d 462
nikapov 0:cad5dab2b21d 463 /*******************************************************************************
nikapov 0:cad5dab2b21d 464 * Register : INT_CTRL_REG
nikapov 0:cad5dab2b21d 465 * Address : 0X63
nikapov 0:cad5dab2b21d 466 * Bit Group Name: IEA
nikapov 0:cad5dab2b21d 467 * Permission : RW
nikapov 0:cad5dab2b21d 468 *******************************************************************************/
nikapov 0:cad5dab2b21d 469 typedef enum {
nikapov 0:cad5dab2b21d 470 LSM303AGR_MAG_IEA_ACTIVE_LO =0x00,
nikapov 0:cad5dab2b21d 471 LSM303AGR_MAG_IEA_ACTIVE_HI =0x04,
nikapov 0:cad5dab2b21d 472 } LSM303AGR_MAG_IEA_t;
nikapov 0:cad5dab2b21d 473
davide.aliprandi@st.com 10:7ced1e5f49dc 474 #define LSM303AGR_MAG_IEA_MASK 0x04
davide.aliprandi@st.com 10:7ced1e5f49dc 475 mems_status_t LSM303AGR_MAG_W_IEA(void *handle, LSM303AGR_MAG_IEA_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 476 mems_status_t LSM303AGR_MAG_R_IEA(void *handle, LSM303AGR_MAG_IEA_t *value);
nikapov 0:cad5dab2b21d 477
nikapov 0:cad5dab2b21d 478 /*******************************************************************************
nikapov 0:cad5dab2b21d 479 * Register : INT_CTRL_REG
nikapov 0:cad5dab2b21d 480 * Address : 0X63
nikapov 0:cad5dab2b21d 481 * Bit Group Name: ZIEN
nikapov 0:cad5dab2b21d 482 * Permission : RW
nikapov 0:cad5dab2b21d 483 *******************************************************************************/
nikapov 0:cad5dab2b21d 484 typedef enum {
nikapov 0:cad5dab2b21d 485 LSM303AGR_MAG_ZIEN_DISABLED =0x00,
nikapov 0:cad5dab2b21d 486 LSM303AGR_MAG_ZIEN_ENABLED =0x20,
nikapov 0:cad5dab2b21d 487 } LSM303AGR_MAG_ZIEN_t;
nikapov 0:cad5dab2b21d 488
davide.aliprandi@st.com 10:7ced1e5f49dc 489 #define LSM303AGR_MAG_ZIEN_MASK 0x20
davide.aliprandi@st.com 10:7ced1e5f49dc 490 mems_status_t LSM303AGR_MAG_W_ZIEN(void *handle, LSM303AGR_MAG_ZIEN_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 491 mems_status_t LSM303AGR_MAG_R_ZIEN(void *handle, LSM303AGR_MAG_ZIEN_t *value);
nikapov 0:cad5dab2b21d 492
nikapov 0:cad5dab2b21d 493 /*******************************************************************************
nikapov 0:cad5dab2b21d 494 * Register : INT_CTRL_REG
nikapov 0:cad5dab2b21d 495 * Address : 0X63
nikapov 0:cad5dab2b21d 496 * Bit Group Name: YIEN
nikapov 0:cad5dab2b21d 497 * Permission : RW
nikapov 0:cad5dab2b21d 498 *******************************************************************************/
nikapov 0:cad5dab2b21d 499 typedef enum {
nikapov 0:cad5dab2b21d 500 LSM303AGR_MAG_YIEN_DISABLED =0x00,
nikapov 0:cad5dab2b21d 501 LSM303AGR_MAG_YIEN_ENABLED =0x40,
nikapov 0:cad5dab2b21d 502 } LSM303AGR_MAG_YIEN_t;
nikapov 0:cad5dab2b21d 503
davide.aliprandi@st.com 10:7ced1e5f49dc 504 #define LSM303AGR_MAG_YIEN_MASK 0x40
davide.aliprandi@st.com 10:7ced1e5f49dc 505 mems_status_t LSM303AGR_MAG_W_YIEN(void *handle, LSM303AGR_MAG_YIEN_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 506 mems_status_t LSM303AGR_MAG_R_YIEN(void *handle, LSM303AGR_MAG_YIEN_t *value);
nikapov 0:cad5dab2b21d 507
nikapov 0:cad5dab2b21d 508 /*******************************************************************************
nikapov 0:cad5dab2b21d 509 * Register : INT_CTRL_REG
nikapov 0:cad5dab2b21d 510 * Address : 0X63
nikapov 0:cad5dab2b21d 511 * Bit Group Name: XIEN
nikapov 0:cad5dab2b21d 512 * Permission : RW
nikapov 0:cad5dab2b21d 513 *******************************************************************************/
nikapov 0:cad5dab2b21d 514 typedef enum {
nikapov 0:cad5dab2b21d 515 LSM303AGR_MAG_XIEN_DISABLED =0x00,
nikapov 0:cad5dab2b21d 516 LSM303AGR_MAG_XIEN_ENABLED =0x80,
nikapov 0:cad5dab2b21d 517 } LSM303AGR_MAG_XIEN_t;
nikapov 0:cad5dab2b21d 518
davide.aliprandi@st.com 10:7ced1e5f49dc 519 #define LSM303AGR_MAG_XIEN_MASK 0x80
davide.aliprandi@st.com 10:7ced1e5f49dc 520 mems_status_t LSM303AGR_MAG_W_XIEN(void *handle, LSM303AGR_MAG_XIEN_t newValue);
davide.aliprandi@st.com 10:7ced1e5f49dc 521 mems_status_t LSM303AGR_MAG_R_XIEN(void *handle, LSM303AGR_MAG_XIEN_t *value);
nikapov 0:cad5dab2b21d 522
nikapov 0:cad5dab2b21d 523 /*******************************************************************************
nikapov 0:cad5dab2b21d 524 * Register : INT_SOURCE_REG
nikapov 0:cad5dab2b21d 525 * Address : 0X64
nikapov 0:cad5dab2b21d 526 * Bit Group Name: INT
nikapov 0:cad5dab2b21d 527 * Permission : RO
nikapov 0:cad5dab2b21d 528 *******************************************************************************/
nikapov 0:cad5dab2b21d 529 typedef enum {
nikapov 0:cad5dab2b21d 530 LSM303AGR_MAG_INT_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 531 LSM303AGR_MAG_INT_EV_ON =0x01,
nikapov 0:cad5dab2b21d 532 } LSM303AGR_MAG_INT_t;
nikapov 0:cad5dab2b21d 533
davide.aliprandi@st.com 10:7ced1e5f49dc 534 #define LSM303AGR_MAG_INT_MASK 0x01
davide.aliprandi@st.com 10:7ced1e5f49dc 535 mems_status_t LSM303AGR_MAG_R_INT(void *handle, LSM303AGR_MAG_INT_t *value);
nikapov 0:cad5dab2b21d 536
nikapov 0:cad5dab2b21d 537 /*******************************************************************************
nikapov 0:cad5dab2b21d 538 * Register : INT_SOURCE_REG
nikapov 0:cad5dab2b21d 539 * Address : 0X64
nikapov 0:cad5dab2b21d 540 * Bit Group Name: MROI
nikapov 0:cad5dab2b21d 541 * Permission : RO
nikapov 0:cad5dab2b21d 542 *******************************************************************************/
nikapov 0:cad5dab2b21d 543 typedef enum {
nikapov 0:cad5dab2b21d 544 LSM303AGR_MAG_MROI_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 545 LSM303AGR_MAG_MROI_EV_ON =0x02,
nikapov 0:cad5dab2b21d 546 } LSM303AGR_MAG_MROI_t;
nikapov 0:cad5dab2b21d 547
davide.aliprandi@st.com 10:7ced1e5f49dc 548 #define LSM303AGR_MAG_MROI_MASK 0x02
davide.aliprandi@st.com 10:7ced1e5f49dc 549 mems_status_t LSM303AGR_MAG_R_MROI(void *handle, LSM303AGR_MAG_MROI_t *value);
nikapov 0:cad5dab2b21d 550
nikapov 0:cad5dab2b21d 551 /*******************************************************************************
nikapov 0:cad5dab2b21d 552 * Register : INT_SOURCE_REG
nikapov 0:cad5dab2b21d 553 * Address : 0X64
nikapov 0:cad5dab2b21d 554 * Bit Group Name: N_TH_S_Z
nikapov 0:cad5dab2b21d 555 * Permission : RO
nikapov 0:cad5dab2b21d 556 *******************************************************************************/
nikapov 0:cad5dab2b21d 557 typedef enum {
nikapov 0:cad5dab2b21d 558 LSM303AGR_MAG_N_TH_S_Z_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 559 LSM303AGR_MAG_N_TH_S_Z_EV_ON =0x04,
nikapov 0:cad5dab2b21d 560 } LSM303AGR_MAG_N_TH_S_Z_t;
nikapov 0:cad5dab2b21d 561
davide.aliprandi@st.com 10:7ced1e5f49dc 562 #define LSM303AGR_MAG_N_TH_S_Z_MASK 0x04
davide.aliprandi@st.com 10:7ced1e5f49dc 563 mems_status_t LSM303AGR_MAG_R_N_TH_S_Z(void *handle, LSM303AGR_MAG_N_TH_S_Z_t *value);
nikapov 0:cad5dab2b21d 564
nikapov 0:cad5dab2b21d 565 /*******************************************************************************
nikapov 0:cad5dab2b21d 566 * Register : INT_SOURCE_REG
nikapov 0:cad5dab2b21d 567 * Address : 0X64
nikapov 0:cad5dab2b21d 568 * Bit Group Name: N_TH_S_Y
nikapov 0:cad5dab2b21d 569 * Permission : RO
nikapov 0:cad5dab2b21d 570 *******************************************************************************/
nikapov 0:cad5dab2b21d 571 typedef enum {
nikapov 0:cad5dab2b21d 572 LSM303AGR_MAG_N_TH_S_Y_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 573 LSM303AGR_MAG_N_TH_S_Y_EV_ON =0x08,
nikapov 0:cad5dab2b21d 574 } LSM303AGR_MAG_N_TH_S_Y_t;
nikapov 0:cad5dab2b21d 575
davide.aliprandi@st.com 10:7ced1e5f49dc 576 #define LSM303AGR_MAG_N_TH_S_Y_MASK 0x08
davide.aliprandi@st.com 10:7ced1e5f49dc 577 mems_status_t LSM303AGR_MAG_R_N_TH_S_Y(void *handle, LSM303AGR_MAG_N_TH_S_Y_t *value);
nikapov 0:cad5dab2b21d 578
nikapov 0:cad5dab2b21d 579 /*******************************************************************************
nikapov 0:cad5dab2b21d 580 * Register : INT_SOURCE_REG
nikapov 0:cad5dab2b21d 581 * Address : 0X64
nikapov 0:cad5dab2b21d 582 * Bit Group Name: N_TH_S_X
nikapov 0:cad5dab2b21d 583 * Permission : RO
nikapov 0:cad5dab2b21d 584 *******************************************************************************/
nikapov 0:cad5dab2b21d 585 typedef enum {
nikapov 0:cad5dab2b21d 586 LSM303AGR_MAG_N_TH_S_X_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 587 LSM303AGR_MAG_N_TH_S_X_EV_ON =0x10,
nikapov 0:cad5dab2b21d 588 } LSM303AGR_MAG_N_TH_S_X_t;
nikapov 0:cad5dab2b21d 589
davide.aliprandi@st.com 10:7ced1e5f49dc 590 #define LSM303AGR_MAG_N_TH_S_X_MASK 0x10
davide.aliprandi@st.com 10:7ced1e5f49dc 591 mems_status_t LSM303AGR_MAG_R_N_TH_S_X(void *handle, LSM303AGR_MAG_N_TH_S_X_t *value);
nikapov 0:cad5dab2b21d 592
nikapov 0:cad5dab2b21d 593 /*******************************************************************************
nikapov 0:cad5dab2b21d 594 * Register : INT_SOURCE_REG
nikapov 0:cad5dab2b21d 595 * Address : 0X64
nikapov 0:cad5dab2b21d 596 * Bit Group Name: P_TH_S_Z
nikapov 0:cad5dab2b21d 597 * Permission : RO
nikapov 0:cad5dab2b21d 598 *******************************************************************************/
nikapov 0:cad5dab2b21d 599 typedef enum {
nikapov 0:cad5dab2b21d 600 LSM303AGR_MAG_P_TH_S_Z_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 601 LSM303AGR_MAG_P_TH_S_Z_EV_ON =0x20,
nikapov 0:cad5dab2b21d 602 } LSM303AGR_MAG_P_TH_S_Z_t;
nikapov 0:cad5dab2b21d 603
davide.aliprandi@st.com 10:7ced1e5f49dc 604 #define LSM303AGR_MAG_P_TH_S_Z_MASK 0x20
davide.aliprandi@st.com 10:7ced1e5f49dc 605 mems_status_t LSM303AGR_MAG_R_P_TH_S_Z(void *handle, LSM303AGR_MAG_P_TH_S_Z_t *value);
nikapov 0:cad5dab2b21d 606
nikapov 0:cad5dab2b21d 607 /*******************************************************************************
nikapov 0:cad5dab2b21d 608 * Register : INT_SOURCE_REG
nikapov 0:cad5dab2b21d 609 * Address : 0X64
nikapov 0:cad5dab2b21d 610 * Bit Group Name: P_TH_S_Y
nikapov 0:cad5dab2b21d 611 * Permission : RO
nikapov 0:cad5dab2b21d 612 *******************************************************************************/
nikapov 0:cad5dab2b21d 613 typedef enum {
nikapov 0:cad5dab2b21d 614 LSM303AGR_MAG_P_TH_S_Y_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 615 LSM303AGR_MAG_P_TH_S_Y_EV_ON =0x40,
nikapov 0:cad5dab2b21d 616 } LSM303AGR_MAG_P_TH_S_Y_t;
nikapov 0:cad5dab2b21d 617
davide.aliprandi@st.com 10:7ced1e5f49dc 618 #define LSM303AGR_MAG_P_TH_S_Y_MASK 0x40
davide.aliprandi@st.com 10:7ced1e5f49dc 619 mems_status_t LSM303AGR_MAG_R_P_TH_S_Y(void *handle, LSM303AGR_MAG_P_TH_S_Y_t *value);
nikapov 0:cad5dab2b21d 620
nikapov 0:cad5dab2b21d 621 /*******************************************************************************
nikapov 0:cad5dab2b21d 622 * Register : INT_SOURCE_REG
nikapov 0:cad5dab2b21d 623 * Address : 0X64
nikapov 0:cad5dab2b21d 624 * Bit Group Name: P_TH_S_X
nikapov 0:cad5dab2b21d 625 * Permission : RO
nikapov 0:cad5dab2b21d 626 *******************************************************************************/
nikapov 0:cad5dab2b21d 627 typedef enum {
nikapov 0:cad5dab2b21d 628 LSM303AGR_MAG_P_TH_S_X_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 629 LSM303AGR_MAG_P_TH_S_X_EV_ON =0x80,
nikapov 0:cad5dab2b21d 630 } LSM303AGR_MAG_P_TH_S_X_t;
nikapov 0:cad5dab2b21d 631
davide.aliprandi@st.com 10:7ced1e5f49dc 632 #define LSM303AGR_MAG_P_TH_S_X_MASK 0x80
davide.aliprandi@st.com 10:7ced1e5f49dc 633 mems_status_t LSM303AGR_MAG_R_P_TH_S_X(void *handle, LSM303AGR_MAG_P_TH_S_X_t *value);
nikapov 0:cad5dab2b21d 634
nikapov 0:cad5dab2b21d 635 /*******************************************************************************
nikapov 0:cad5dab2b21d 636 * Register : STATUS_REG
nikapov 0:cad5dab2b21d 637 * Address : 0X67
nikapov 0:cad5dab2b21d 638 * Bit Group Name: XDA
nikapov 0:cad5dab2b21d 639 * Permission : RO
nikapov 0:cad5dab2b21d 640 *******************************************************************************/
nikapov 0:cad5dab2b21d 641 typedef enum {
nikapov 0:cad5dab2b21d 642 LSM303AGR_MAG_XDA_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 643 LSM303AGR_MAG_XDA_EV_ON =0x01,
nikapov 0:cad5dab2b21d 644 } LSM303AGR_MAG_XDA_t;
nikapov 0:cad5dab2b21d 645
davide.aliprandi@st.com 10:7ced1e5f49dc 646 #define LSM303AGR_MAG_XDA_MASK 0x01
davide.aliprandi@st.com 10:7ced1e5f49dc 647 mems_status_t LSM303AGR_MAG_R_XDA(void *handle, LSM303AGR_MAG_XDA_t *value);
nikapov 0:cad5dab2b21d 648
nikapov 0:cad5dab2b21d 649 /*******************************************************************************
nikapov 0:cad5dab2b21d 650 * Register : STATUS_REG
nikapov 0:cad5dab2b21d 651 * Address : 0X67
nikapov 0:cad5dab2b21d 652 * Bit Group Name: YDA
nikapov 0:cad5dab2b21d 653 * Permission : RO
nikapov 0:cad5dab2b21d 654 *******************************************************************************/
nikapov 0:cad5dab2b21d 655 typedef enum {
nikapov 0:cad5dab2b21d 656 LSM303AGR_MAG_YDA_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 657 LSM303AGR_MAG_YDA_EV_ON =0x02,
nikapov 0:cad5dab2b21d 658 } LSM303AGR_MAG_YDA_t;
nikapov 0:cad5dab2b21d 659
davide.aliprandi@st.com 10:7ced1e5f49dc 660 #define LSM303AGR_MAG_YDA_MASK 0x02
davide.aliprandi@st.com 10:7ced1e5f49dc 661 mems_status_t LSM303AGR_MAG_R_YDA(void *handle, LSM303AGR_MAG_YDA_t *value);
nikapov 0:cad5dab2b21d 662
nikapov 0:cad5dab2b21d 663 /*******************************************************************************
nikapov 0:cad5dab2b21d 664 * Register : STATUS_REG
nikapov 0:cad5dab2b21d 665 * Address : 0X67
nikapov 0:cad5dab2b21d 666 * Bit Group Name: ZDA
nikapov 0:cad5dab2b21d 667 * Permission : RO
nikapov 0:cad5dab2b21d 668 *******************************************************************************/
nikapov 0:cad5dab2b21d 669 typedef enum {
nikapov 0:cad5dab2b21d 670 LSM303AGR_MAG_ZDA_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 671 LSM303AGR_MAG_ZDA_EV_ON =0x04,
nikapov 0:cad5dab2b21d 672 } LSM303AGR_MAG_ZDA_t;
nikapov 0:cad5dab2b21d 673
davide.aliprandi@st.com 10:7ced1e5f49dc 674 #define LSM303AGR_MAG_ZDA_MASK 0x04
davide.aliprandi@st.com 10:7ced1e5f49dc 675 mems_status_t LSM303AGR_MAG_R_ZDA(void *handle, LSM303AGR_MAG_ZDA_t *value);
nikapov 0:cad5dab2b21d 676
nikapov 0:cad5dab2b21d 677 /*******************************************************************************
nikapov 0:cad5dab2b21d 678 * Register : STATUS_REG
nikapov 0:cad5dab2b21d 679 * Address : 0X67
nikapov 0:cad5dab2b21d 680 * Bit Group Name: ZYXDA
nikapov 0:cad5dab2b21d 681 * Permission : RO
nikapov 0:cad5dab2b21d 682 *******************************************************************************/
nikapov 0:cad5dab2b21d 683 typedef enum {
nikapov 0:cad5dab2b21d 684 LSM303AGR_MAG_ZYXDA_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 685 LSM303AGR_MAG_ZYXDA_EV_ON =0x08,
nikapov 0:cad5dab2b21d 686 } LSM303AGR_MAG_ZYXDA_t;
nikapov 0:cad5dab2b21d 687
davide.aliprandi@st.com 10:7ced1e5f49dc 688 #define LSM303AGR_MAG_ZYXDA_MASK 0x08
davide.aliprandi@st.com 10:7ced1e5f49dc 689 mems_status_t LSM303AGR_MAG_R_ZYXDA(void *handle, LSM303AGR_MAG_ZYXDA_t *value);
nikapov 0:cad5dab2b21d 690
nikapov 0:cad5dab2b21d 691 /*******************************************************************************
nikapov 0:cad5dab2b21d 692 * Register : STATUS_REG
nikapov 0:cad5dab2b21d 693 * Address : 0X67
nikapov 0:cad5dab2b21d 694 * Bit Group Name: XOR
nikapov 0:cad5dab2b21d 695 * Permission : RO
nikapov 0:cad5dab2b21d 696 *******************************************************************************/
nikapov 0:cad5dab2b21d 697 typedef enum {
nikapov 0:cad5dab2b21d 698 LSM303AGR_MAG_XOR_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 699 LSM303AGR_MAG_XOR_EV_ON =0x10,
nikapov 0:cad5dab2b21d 700 } LSM303AGR_MAG_XOR_t;
nikapov 0:cad5dab2b21d 701
davide.aliprandi@st.com 10:7ced1e5f49dc 702 #define LSM303AGR_MAG_XOR_MASK 0x10
davide.aliprandi@st.com 10:7ced1e5f49dc 703 mems_status_t LSM303AGR_MAG_R_XOR(void *handle, LSM303AGR_MAG_XOR_t *value);
nikapov 0:cad5dab2b21d 704
nikapov 0:cad5dab2b21d 705 /*******************************************************************************
nikapov 0:cad5dab2b21d 706 * Register : STATUS_REG
nikapov 0:cad5dab2b21d 707 * Address : 0X67
nikapov 0:cad5dab2b21d 708 * Bit Group Name: YOR
nikapov 0:cad5dab2b21d 709 * Permission : RO
nikapov 0:cad5dab2b21d 710 *******************************************************************************/
nikapov 0:cad5dab2b21d 711 typedef enum {
nikapov 0:cad5dab2b21d 712 LSM303AGR_MAG_YOR_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 713 LSM303AGR_MAG_YOR_EV_ON =0x20,
nikapov 0:cad5dab2b21d 714 } LSM303AGR_MAG_YOR_t;
nikapov 0:cad5dab2b21d 715
davide.aliprandi@st.com 10:7ced1e5f49dc 716 #define LSM303AGR_MAG_YOR_MASK 0x20
davide.aliprandi@st.com 10:7ced1e5f49dc 717 mems_status_t LSM303AGR_MAG_R_YOR(void *handle, LSM303AGR_MAG_YOR_t *value);
nikapov 0:cad5dab2b21d 718
nikapov 0:cad5dab2b21d 719 /*******************************************************************************
nikapov 0:cad5dab2b21d 720 * Register : STATUS_REG
nikapov 0:cad5dab2b21d 721 * Address : 0X67
nikapov 0:cad5dab2b21d 722 * Bit Group Name: ZOR
nikapov 0:cad5dab2b21d 723 * Permission : RO
nikapov 0:cad5dab2b21d 724 *******************************************************************************/
nikapov 0:cad5dab2b21d 725 typedef enum {
nikapov 0:cad5dab2b21d 726 LSM303AGR_MAG_ZOR_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 727 LSM303AGR_MAG_ZOR_EV_ON =0x40,
nikapov 0:cad5dab2b21d 728 } LSM303AGR_MAG_ZOR_t;
nikapov 0:cad5dab2b21d 729
davide.aliprandi@st.com 10:7ced1e5f49dc 730 #define LSM303AGR_MAG_ZOR_MASK 0x40
davide.aliprandi@st.com 10:7ced1e5f49dc 731 mems_status_t LSM303AGR_MAG_R_ZOR(void *handle, LSM303AGR_MAG_ZOR_t *value);
nikapov 0:cad5dab2b21d 732
nikapov 0:cad5dab2b21d 733 /*******************************************************************************
nikapov 0:cad5dab2b21d 734 * Register : STATUS_REG
nikapov 0:cad5dab2b21d 735 * Address : 0X67
nikapov 0:cad5dab2b21d 736 * Bit Group Name: ZYXOR
nikapov 0:cad5dab2b21d 737 * Permission : RO
nikapov 0:cad5dab2b21d 738 *******************************************************************************/
nikapov 0:cad5dab2b21d 739 typedef enum {
nikapov 0:cad5dab2b21d 740 LSM303AGR_MAG_ZYXOR_EV_OFF =0x00,
nikapov 0:cad5dab2b21d 741 LSM303AGR_MAG_ZYXOR_EV_ON =0x80,
nikapov 0:cad5dab2b21d 742 } LSM303AGR_MAG_ZYXOR_t;
nikapov 0:cad5dab2b21d 743
davide.aliprandi@st.com 10:7ced1e5f49dc 744 #define LSM303AGR_MAG_ZYXOR_MASK 0x80
davide.aliprandi@st.com 10:7ced1e5f49dc 745 mems_status_t LSM303AGR_MAG_R_ZYXOR(void *handle, LSM303AGR_MAG_ZYXOR_t *value);
nikapov 0:cad5dab2b21d 746 /*******************************************************************************
nikapov 0:cad5dab2b21d 747 * Register : <REGISTER_L> - <REGISTER_H>
nikapov 0:cad5dab2b21d 748 * Output Type : Magnetic
nikapov 0:cad5dab2b21d 749 * Permission : ro
nikapov 0:cad5dab2b21d 750 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 751 mems_status_t LSM303AGR_MAG_Get_Raw_Magnetic(void *handle, u8_t *buff);
davide.aliprandi@st.com 10:7ced1e5f49dc 752 mems_status_t LSM303AGR_MAG_Get_Magnetic(void *handle, int *buff);
nikapov 0:cad5dab2b21d 753
nikapov 0:cad5dab2b21d 754 /*******************************************************************************
nikapov 0:cad5dab2b21d 755 * Register : <REGISTER_L> - <REGISTER_H>
nikapov 0:cad5dab2b21d 756 * Output Type : IntThreshld
nikapov 0:cad5dab2b21d 757 * Permission : rw
nikapov 0:cad5dab2b21d 758 *******************************************************************************/
davide.aliprandi@st.com 10:7ced1e5f49dc 759 mems_status_t LSM303AGR_MAG_Get_IntThreshld(void *handle, u8_t *buff);
davide.aliprandi@st.com 10:7ced1e5f49dc 760 mems_status_t LSM303AGR_MAG_Set_IntThreshld(void *handle, u8_t *buff);
nikapov 0:cad5dab2b21d 761
nikapov 0:cad5dab2b21d 762 #ifdef __cplusplus
nikapov 0:cad5dab2b21d 763 }
nikapov 0:cad5dab2b21d 764 #endif
nikapov 0:cad5dab2b21d 765
nikapov 0:cad5dab2b21d 766 #endif