Jonne Valola
PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)
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core_cm3.h
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00001 /**************************************************************************//** 00002 * @file core_cm3.h 00003 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File 00004 * @version V3.20 00005 * @date 25. February 2013 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2013 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 #ifndef __CORE_CM3_H_GENERIC 00047 #define __CORE_CM3_H_GENERIC 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex_M3 00067 @{ 00068 */ 00069 00070 /* CMSIS CM3 definitions */ 00071 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x03) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __ICCARM__ ) 00085 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00086 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __TMS470__ ) 00090 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00091 #define __STATIC_INLINE static inline 00092 00093 #elif defined ( __GNUC__ ) 00094 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00095 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #endif 00104 00105 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all 00106 */ 00107 #define __FPU_USED 0 00108 00109 #if defined ( __CC_ARM ) 00110 #if defined __TARGET_FPU_VFP 00111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00112 #endif 00113 00114 #elif defined ( __ICCARM__ ) 00115 #if defined __ARMVFP__ 00116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00117 #endif 00118 00119 #elif defined ( __TMS470__ ) 00120 #if defined __TI__VFP_SUPPORT____ 00121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00122 #endif 00123 00124 #elif defined ( __GNUC__ ) 00125 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00127 #endif 00128 00129 #elif defined ( __TASKING__ ) 00130 #if defined __FPU_VFP__ 00131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00132 #endif 00133 #endif 00134 00135 #include <stdint.h> /* standard types definitions */ 00136 #include <core_cmInstr.h> /* Core Instruction Access */ 00137 #include <core_cmFunc.h> /* Core Function Access */ 00138 00139 #endif /* __CORE_CM3_H_GENERIC */ 00140 00141 #ifndef __CMSIS_GENERIC 00142 00143 #ifndef __CORE_CM3_H_DEPENDANT 00144 #define __CORE_CM3_H_DEPENDANT 00145 00146 /* check device defines and use defaults */ 00147 #if defined __CHECK_DEVICE_DEFINES 00148 #ifndef __CM3_REV 00149 #define __CM3_REV 0x0200 00150 #warning "__CM3_REV not defined in device header file; using default!" 00151 #endif 00152 00153 #ifndef __MPU_PRESENT 00154 #define __MPU_PRESENT 0 00155 #warning "__MPU_PRESENT not defined in device header file; using default!" 00156 #endif 00157 00158 #ifndef __NVIC_PRIO_BITS 00159 #define __NVIC_PRIO_BITS 4 00160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00161 #endif 00162 00163 #ifndef __Vendor_SysTickConfig 00164 #define __Vendor_SysTickConfig 0 00165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00166 #endif 00167 #endif 00168 00169 /* IO definitions (access restrictions to peripheral registers) */ 00170 /** 00171 \defgroup CMSIS_glob_defs CMSIS Global Defines 00172 00173 <strong>IO Type Qualifiers</strong> are used 00174 \li to specify the access to peripheral variables. 00175 \li for automatic generation of peripheral register debug information. 00176 */ 00177 #ifdef __cplusplus 00178 #define __I volatile /*!< Defines 'read only' permissions */ 00179 #else 00180 #define __I volatile const /*!< Defines 'read only' permissions */ 00181 #endif 00182 #define __O volatile /*!< Defines 'write only' permissions */ 00183 #define __IO volatile /*!< Defines 'read / write' permissions */ 00184 00185 /*@} end of group Cortex_M3 */ 00186 00187 00188 00189 /******************************************************************************* 00190 * Register Abstraction 00191 Core Register contain: 00192 - Core Register 00193 - Core NVIC Register 00194 - Core SCB Register 00195 - Core SysTick Register 00196 - Core Debug Register 00197 - Core MPU Register 00198 ******************************************************************************/ 00199 /** \defgroup CMSIS_core_register Defines and Type Definitions 00200 \brief Type definitions and defines for Cortex-M processor based devices. 00201 */ 00202 00203 /** \ingroup CMSIS_core_register 00204 \defgroup CMSIS_CORE Status and Control Registers 00205 \brief Core Register type definitions. 00206 @{ 00207 */ 00208 00209 /** \brief Union type to access the Application Program Status Register (APSR). 00210 */ 00211 typedef union 00212 { 00213 struct 00214 { 00215 #if (__CORTEX_M != 0x04) 00216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00217 #else 00218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00221 #endif 00222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00227 } b; /*!< Structure used for bit access */ 00228 uint32_t w; /*!< Type used for word access */ 00229 } APSR_Type; 00230 00231 00232 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00233 */ 00234 typedef union 00235 { 00236 struct 00237 { 00238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00240 } b; /*!< Structure used for bit access */ 00241 uint32_t w; /*!< Type used for word access */ 00242 } IPSR_Type; 00243 00244 00245 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00246 */ 00247 typedef union 00248 { 00249 struct 00250 { 00251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00252 #if (__CORTEX_M != 0x04) 00253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00254 #else 00255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00258 #endif 00259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00266 } b; /*!< Structure used for bit access */ 00267 uint32_t w; /*!< Type used for word access */ 00268 } xPSR_Type; 00269 00270 00271 /** \brief Union type to access the Control Registers (CONTROL). 00272 */ 00273 typedef union 00274 { 00275 struct 00276 { 00277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00281 } b; /*!< Structure used for bit access */ 00282 uint32_t w; /*!< Type used for word access */ 00283 } CONTROL_Type; 00284 00285 /*@} end of group CMSIS_CORE */ 00286 00287 00288 /** \ingroup CMSIS_core_register 00289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00290 \brief Type definitions for the NVIC Registers 00291 @{ 00292 */ 00293 00294 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00295 */ 00296 typedef struct 00297 { 00298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00299 uint32_t RESERVED0[24]; 00300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00301 uint32_t RSERVED1[24]; 00302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00303 uint32_t RESERVED2[24]; 00304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00305 uint32_t RESERVED3[24]; 00306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00307 uint32_t RESERVED4[56]; 00308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00309 uint32_t RESERVED5[644]; 00310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00311 } NVIC_Type; 00312 00313 /* Software Triggered Interrupt Register Definitions */ 00314 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ 00315 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ 00316 00317 /*@} end of group CMSIS_NVIC */ 00318 00319 00320 /** \ingroup CMSIS_core_register 00321 \defgroup CMSIS_SCB System Control Block (SCB) 00322 \brief Type definitions for the System Control Block Registers 00323 @{ 00324 */ 00325 00326 /** \brief Structure type to access the System Control Block (SCB). 00327 */ 00328 typedef struct 00329 { 00330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00349 uint32_t RESERVED0[5]; 00350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00351 } SCB_Type; 00352 00353 /* SCB CPUID Register Definitions */ 00354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00356 00357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00359 00360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00362 00363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00365 00366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00368 00369 /* SCB Interrupt Control State Register Definitions */ 00370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00372 00373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00375 00376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00378 00379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00381 00382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00384 00385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00387 00388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00390 00391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00393 00394 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 00395 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00396 00397 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00398 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00399 00400 /* SCB Vector Table Offset Register Definitions */ 00401 #if (__CM3_REV < 0x0201) /* core r2p1 */ 00402 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ 00403 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ 00404 00405 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00406 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00407 #else 00408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00410 #endif 00411 00412 /* SCB Application Interrupt and Reset Control Register Definitions */ 00413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00415 00416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00418 00419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00421 00422 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 00423 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00424 00425 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00427 00428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00430 00431 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 00432 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ 00433 00434 /* SCB System Control Register Definitions */ 00435 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00436 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00437 00438 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00439 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00440 00441 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00442 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00443 00444 /* SCB Configuration Control Register Definitions */ 00445 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00446 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00447 00448 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 00449 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00450 00451 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 00452 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00453 00454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00456 00457 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 00458 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00459 00460 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 00461 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ 00462 00463 /* SCB System Handler Control and State Register Definitions */ 00464 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 00465 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00466 00467 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 00468 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00469 00470 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 00471 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00472 00473 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00474 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00475 00476 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00477 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00478 00479 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00480 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00481 00482 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 00483 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00484 00485 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 00486 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00487 00488 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 00489 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00490 00491 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 00492 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00493 00494 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 00495 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00496 00497 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 00498 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00499 00500 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 00501 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00502 00503 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 00504 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00505 00506 /* SCB Configurable Fault Status Registers Definitions */ 00507 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 00508 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00509 00510 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 00511 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00512 00513 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00514 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00515 00516 /* SCB Hard Fault Status Registers Definitions */ 00517 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 00518 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00519 00520 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 00521 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00522 00523 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 00524 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00525 00526 /* SCB Debug Fault Status Register Definitions */ 00527 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 00528 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00529 00530 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 00531 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00532 00533 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 00534 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00535 00536 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 00537 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00538 00539 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 00540 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ 00541 00542 /*@} end of group CMSIS_SCB */ 00543 00544 00545 /** \ingroup CMSIS_core_register 00546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00547 \brief Type definitions for the System Control and ID Register not in the SCB 00548 @{ 00549 */ 00550 00551 /** \brief Structure type to access the System Control and ID Register not in the SCB. 00552 */ 00553 typedef struct 00554 { 00555 uint32_t RESERVED0[1]; 00556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00557 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) 00558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00559 #else 00560 uint32_t RESERVED1[1]; 00561 #endif 00562 } SCnSCB_Type; 00563 00564 /* Interrupt Controller Type Register Definitions */ 00565 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ 00566 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ 00567 00568 /* Auxiliary Control Register Definitions */ 00569 00570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ 00571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00572 00573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ 00574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 00575 00576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 00577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 00578 00579 /*@} end of group CMSIS_SCnotSCB */ 00580 00581 00582 /** \ingroup CMSIS_core_register 00583 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00584 \brief Type definitions for the System Timer Registers. 00585 @{ 00586 */ 00587 00588 /** \brief Structure type to access the System Timer (SysTick). 00589 */ 00590 typedef struct 00591 { 00592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00596 } SysTick_Type; 00597 00598 /* SysTick Control / Status Register Definitions */ 00599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00601 00602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00604 00605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00607 00608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00610 00611 /* SysTick Reload Register Definitions */ 00612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00614 00615 /* SysTick Current Register Definitions */ 00616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00618 00619 /* SysTick Calibration Register Definitions */ 00620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00622 00623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00625 00626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ 00628 00629 /*@} end of group CMSIS_SysTick */ 00630 00631 00632 /** \ingroup CMSIS_core_register 00633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00635 @{ 00636 */ 00637 00638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00639 */ 00640 typedef struct 00641 { 00642 __O union 00643 { 00644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00648 uint32_t RESERVED0[864]; 00649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00650 uint32_t RESERVED1[15]; 00651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00652 uint32_t RESERVED2[15]; 00653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00654 uint32_t RESERVED3[29]; 00655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 00656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 00657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 00658 uint32_t RESERVED4[43]; 00659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00661 uint32_t RESERVED5[6]; 00662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00674 } ITM_Type; 00675 00676 /* ITM Trace Privilege Register Definitions */ 00677 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 00678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ 00679 00680 /* ITM Trace Control Register Definitions */ 00681 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 00682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00683 00684 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ 00685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00686 00687 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ 00688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00689 00690 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 00691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00692 00693 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 00694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00695 00696 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ 00697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 00698 00699 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 00700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 00701 00702 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 00703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 00704 00705 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 00706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ 00707 00708 /* ITM Integration Write Register Definitions */ 00709 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ 00710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ 00711 00712 /* ITM Integration Read Register Definitions */ 00713 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ 00714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ 00715 00716 /* ITM Integration Mode Control Register Definitions */ 00717 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ 00718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ 00719 00720 /* ITM Lock Status Register Definitions */ 00721 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ 00722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 00723 00724 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ 00725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 00726 00727 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ 00728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ 00729 00730 /*@}*/ /* end of group CMSIS_ITM */ 00731 00732 00733 /** \ingroup CMSIS_core_register 00734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00735 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00736 @{ 00737 */ 00738 00739 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00740 */ 00741 typedef struct 00742 { 00743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 00745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 00746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 00747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 00748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 00749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 00750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 00753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00754 uint32_t RESERVED0[1]; 00755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 00757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00758 uint32_t RESERVED1[1]; 00759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 00761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00762 uint32_t RESERVED2[1]; 00763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 00765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00766 } DWT_Type; 00767 00768 /* DWT Control Register Definitions */ 00769 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ 00770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00771 00772 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ 00773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00774 00775 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ 00776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00777 00778 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ 00779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00780 00781 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ 00782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00783 00784 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ 00785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 00786 00787 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ 00788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 00789 00790 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ 00791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 00792 00793 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ 00794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 00795 00796 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ 00797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 00798 00799 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ 00800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 00801 00802 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ 00803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 00804 00805 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ 00806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 00807 00808 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ 00809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 00810 00811 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ 00812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 00813 00814 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ 00815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 00816 00817 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ 00818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 00819 00820 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ 00821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ 00822 00823 /* DWT CPI Count Register Definitions */ 00824 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ 00825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ 00826 00827 /* DWT Exception Overhead Count Register Definitions */ 00828 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ 00829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ 00830 00831 /* DWT Sleep Count Register Definitions */ 00832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ 00833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 00834 00835 /* DWT LSU Count Register Definitions */ 00836 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ 00837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ 00838 00839 /* DWT Folded-instruction Count Register Definitions */ 00840 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ 00841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ 00842 00843 /* DWT Comparator Mask Register Definitions */ 00844 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ 00845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ 00846 00847 /* DWT Comparator Function Register Definitions */ 00848 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ 00849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00850 00851 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ 00852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 00853 00854 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ 00855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 00856 00857 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ 00858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00859 00860 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ 00861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 00862 00863 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ 00864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 00865 00866 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ 00867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 00868 00869 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ 00870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 00871 00872 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ 00873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ 00874 00875 /*@}*/ /* end of group CMSIS_DWT */ 00876 00877 00878 /** \ingroup CMSIS_core_register 00879 \defgroup CMSIS_TPI Trace Port Interface (TPI) 00880 \brief Type definitions for the Trace Port Interface (TPI) 00881 @{ 00882 */ 00883 00884 /** \brief Structure type to access the Trace Port Interface Register (TPI). 00885 */ 00886 typedef struct 00887 { 00888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 00889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 00890 uint32_t RESERVED0[2]; 00891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 00892 uint32_t RESERVED1[55]; 00893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 00894 uint32_t RESERVED2[131]; 00895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 00896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 00897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 00898 uint32_t RESERVED3[759]; 00899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 00900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 00901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 00902 uint32_t RESERVED4[1]; 00903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 00904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 00905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 00906 uint32_t RESERVED5[39]; 00907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 00908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 00909 uint32_t RESERVED7[8]; 00910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 00911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 00912 } TPI_Type; 00913 00914 /* TPI Asynchronous Clock Prescaler Register Definitions */ 00915 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ 00916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ 00917 00918 /* TPI Selected Pin Protocol Register Definitions */ 00919 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ 00920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ 00921 00922 /* TPI Formatter and Flush Status Register Definitions */ 00923 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ 00924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 00925 00926 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ 00927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 00928 00929 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ 00930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 00931 00932 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ 00933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ 00934 00935 /* TPI Formatter and Flush Control Register Definitions */ 00936 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ 00937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 00938 00939 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ 00940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 00941 00942 /* TPI TRIGGER Register Definitions */ 00943 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ 00944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ 00945 00946 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 00947 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ 00948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 00949 00950 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ 00951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 00952 00953 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ 00954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 00955 00956 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ 00957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 00958 00959 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ 00960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 00961 00962 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ 00963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 00964 00965 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ 00966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ 00967 00968 /* TPI ITATBCTR2 Register Definitions */ 00969 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ 00970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ 00971 00972 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 00973 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ 00974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 00975 00976 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ 00977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 00978 00979 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ 00980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 00981 00982 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ 00983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 00984 00985 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ 00986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 00987 00988 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ 00989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 00990 00991 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ 00992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ 00993 00994 /* TPI ITATBCTR0 Register Definitions */ 00995 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ 00996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ 00997 00998 /* TPI Integration Mode Control Register Definitions */ 00999 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ 01000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ 01001 01002 /* TPI DEVID Register Definitions */ 01003 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ 01004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01005 01006 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ 01007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01008 01009 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ 01010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01011 01012 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ 01013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01014 01015 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ 01016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01017 01018 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ 01019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ 01020 01021 /* TPI DEVTYPE Register Definitions */ 01022 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ 01023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ 01024 01025 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ 01026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01027 01028 /*@}*/ /* end of group CMSIS_TPI */ 01029 01030 01031 #if (__MPU_PRESENT == 1) 01032 /** \ingroup CMSIS_core_register 01033 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01034 \brief Type definitions for the Memory Protection Unit (MPU) 01035 @{ 01036 */ 01037 01038 /** \brief Structure type to access the Memory Protection Unit (MPU). 01039 */ 01040 typedef struct 01041 { 01042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01053 } MPU_Type; 01054 01055 /* MPU Type Register */ 01056 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 01057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01058 01059 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 01060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01061 01062 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 01063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 01064 01065 /* MPU Control Register */ 01066 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 01067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01068 01069 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 01070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01071 01072 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 01073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 01074 01075 /* MPU Region Number Register */ 01076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 01077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 01078 01079 /* MPU Region Base Address Register */ 01080 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 01081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01082 01083 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 01084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01085 01086 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 01087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 01088 01089 /* MPU Region Attribute and Size Register */ 01090 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 01091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01092 01093 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 01094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01095 01096 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 01097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01098 01099 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 01100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01101 01102 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 01103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01104 01105 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 01106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01107 01108 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 01109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01110 01111 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 01112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01113 01114 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 01115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01116 01117 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 01118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 01119 01120 /*@} end of group CMSIS_MPU */ 01121 #endif 01122 01123 01124 /** \ingroup CMSIS_core_register 01125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01126 \brief Type definitions for the Core Debug Registers 01127 @{ 01128 */ 01129 01130 /** \brief Structure type to access the Core Debug Register (CoreDebug). 01131 */ 01132 typedef struct 01133 { 01134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01138 } CoreDebug_Type; 01139 01140 /* Debug Halting Control and Status Register */ 01141 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 01142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01143 01144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01146 01147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01149 01150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01152 01153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 01154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01155 01156 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 01157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01158 01159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 01160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01161 01162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01164 01165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01167 01168 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 01169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01170 01171 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 01172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01173 01174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01176 01177 /* Debug Core Register Selector Register */ 01178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 01179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01180 01181 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 01182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ 01183 01184 /* Debug Exception and Monitor Control Register */ 01185 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 01186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01187 01188 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 01189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01190 01191 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 01192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01193 01194 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 01195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01196 01197 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 01198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01199 01200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01202 01203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 01204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01205 01206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01208 01209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 01210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01211 01212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01214 01215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01217 01218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 01219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01220 01221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01223 01224 /*@} end of group CMSIS_CoreDebug */ 01225 01226 01227 /** \ingroup CMSIS_core_register 01228 \defgroup CMSIS_core_base Core Definitions 01229 \brief Definitions for base addresses, unions, and structures. 01230 @{ 01231 */ 01232 01233 /* Memory mapping of Cortex-M3 Hardware */ 01234 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01235 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01236 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01237 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01238 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01239 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01240 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01241 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01242 01243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01245 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01247 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01248 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01249 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01251 01252 #if (__MPU_PRESENT == 1) 01253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01255 #endif 01256 01257 /*@} */ 01258 01259 01260 01261 /******************************************************************************* 01262 * Hardware Abstraction Layer 01263 Core Function Interface contains: 01264 - Core NVIC Functions 01265 - Core SysTick Functions 01266 - Core Debug Functions 01267 - Core Register Access Functions 01268 ******************************************************************************/ 01269 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01270 */ 01271 01272 01273 01274 /* ########################## NVIC functions #################################### */ 01275 /** \ingroup CMSIS_Core_FunctionInterface 01276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01277 \brief Functions that manage interrupts and exceptions via the NVIC. 01278 @{ 01279 */ 01280 01281 /** \brief Set Priority Grouping 01282 01283 The function sets the priority grouping field using the required unlock sequence. 01284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01285 Only values from 0..7 are used. 01286 In case of a conflict between priority grouping and available 01287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01288 01289 \param [in] PriorityGroup Priority grouping field. 01290 */ 01291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01292 { 01293 uint32_t reg_value; 01294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ 01295 01296 reg_value = SCB->AIRCR; /* read old register configuration */ 01297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 01298 reg_value = (reg_value | 01299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 01301 SCB->AIRCR = reg_value; 01302 } 01303 01304 01305 /** \brief Get Priority Grouping 01306 01307 The function reads the priority grouping field from the NVIC Interrupt Controller. 01308 01309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01310 */ 01311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 01312 { 01313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 01314 } 01315 01316 01317 /** \brief Enable External Interrupt 01318 01319 The function enables a device-specific interrupt in the NVIC interrupt controller. 01320 01321 \param [in] IRQn External interrupt number. Value cannot be negative. 01322 */ 01323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 01324 { 01325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ 01326 } 01327 01328 01329 /** \brief Disable External Interrupt 01330 01331 The function disables a device-specific interrupt in the NVIC interrupt controller. 01332 01333 \param [in] IRQn External interrupt number. Value cannot be negative. 01334 */ 01335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 01336 { 01337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 01338 } 01339 01340 01341 /** \brief Get Pending Interrupt 01342 01343 The function reads the pending register in the NVIC and returns the pending bit 01344 for the specified interrupt. 01345 01346 \param [in] IRQn Interrupt number. 01347 01348 \return 0 Interrupt status is not pending. 01349 \return 1 Interrupt status is pending. 01350 */ 01351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 01352 { 01353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 01354 } 01355 01356 01357 /** \brief Set Pending Interrupt 01358 01359 The function sets the pending bit of an external interrupt. 01360 01361 \param [in] IRQn Interrupt number. Value cannot be negative. 01362 */ 01363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 01364 { 01365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 01366 } 01367 01368 01369 /** \brief Clear Pending Interrupt 01370 01371 The function clears the pending bit of an external interrupt. 01372 01373 \param [in] IRQn External interrupt number. Value cannot be negative. 01374 */ 01375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01376 { 01377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 01378 } 01379 01380 01381 /** \brief Get Active Interrupt 01382 01383 The function reads the active register in NVIC and returns the active bit. 01384 01385 \param [in] IRQn Interrupt number. 01386 01387 \return 0 Interrupt status is not active. 01388 \return 1 Interrupt status is active. 01389 */ 01390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 01391 { 01392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 01393 } 01394 01395 01396 /** \brief Set Interrupt Priority 01397 01398 The function sets the priority of an interrupt. 01399 01400 \note The priority cannot be set for every core interrupt. 01401 01402 \param [in] IRQn Interrupt number. 01403 \param [in] priority Priority to set. 01404 */ 01405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01406 { 01407 if(IRQn < 0) { 01408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 01409 else { 01410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 01411 } 01412 01413 01414 /** \brief Get Interrupt Priority 01415 01416 The function reads the priority of an interrupt. The interrupt 01417 number can be positive to specify an external (device specific) 01418 interrupt, or negative to specify an internal (core) interrupt. 01419 01420 01421 \param [in] IRQn Interrupt number. 01422 \return Interrupt Priority. Value is aligned automatically to the implemented 01423 priority bits of the microcontroller. 01424 */ 01425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 01426 { 01427 01428 if(IRQn < 0) { 01429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ 01430 else { 01431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 01432 } 01433 01434 01435 /** \brief Encode Priority 01436 01437 The function encodes the priority for an interrupt with the given priority group, 01438 preemptive priority value, and subpriority value. 01439 In case of a conflict between priority grouping and available 01440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. 01441 01442 \param [in] PriorityGroup Used priority group. 01443 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01444 \param [in] SubPriority Subpriority value (starting from 0). 01445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01446 */ 01447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01448 { 01449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01450 uint32_t PreemptPriorityBits; 01451 uint32_t SubPriorityBits; 01452 01453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01455 01456 return ( 01457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 01458 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 01459 ); 01460 } 01461 01462 01463 /** \brief Decode Priority 01464 01465 The function decodes an interrupt priority value with a given priority group to 01466 preemptive priority value and subpriority value. 01467 In case of a conflict between priority grouping and available 01468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. 01469 01470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01471 \param [in] PriorityGroup Used priority group. 01472 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01473 \param [out] pSubPriority Subpriority value (starting from 0). 01474 */ 01475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 01476 { 01477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01478 uint32_t PreemptPriorityBits; 01479 uint32_t SubPriorityBits; 01480 01481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01483 01484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 01485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 01486 } 01487 01488 01489 /** \brief System Reset 01490 01491 The function initiates a system reset request to reset the MCU. 01492 */ 01493 __STATIC_INLINE void NVIC_SystemReset(void) 01494 { 01495 __DSB(); /* Ensure all outstanding memory accesses included 01496 buffered write are completed before reset */ 01497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 01500 __DSB(); /* Ensure completion of memory access */ 01501 while(1); /* wait until reset */ 01502 } 01503 01504 /*@} end of CMSIS_Core_NVICFunctions */ 01505 01506 01507 01508 /* ################################## SysTick function ############################################ */ 01509 /** \ingroup CMSIS_Core_FunctionInterface 01510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01511 \brief Functions that configure the System. 01512 @{ 01513 */ 01514 01515 #if (__Vendor_SysTickConfig == 0) 01516 01517 /** \brief System Tick Configuration 01518 01519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 01520 Counter is in free running mode to generate periodic interrupts. 01521 01522 \param [in] ticks Number of ticks between two interrupts. 01523 01524 \return 0 Function succeeded. 01525 \return 1 Function failed. 01526 01527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01529 must contain a vendor-specific implementation of this function. 01530 01531 */ 01532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01533 { 01534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 01535 01536 SysTick->LOAD = ticks - 1; /* set reload register */ 01537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 01538 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 01539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01540 SysTick_CTRL_TICKINT_Msk | 01541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01542 return (0); /* Function successful */ 01543 } 01544 01545 #endif 01546 01547 /*@} end of CMSIS_Core_SysTickFunctions */ 01548 01549 01550 01551 /* ##################################### Debug In/Output function ########################################### */ 01552 /** \ingroup CMSIS_Core_FunctionInterface 01553 \defgroup CMSIS_core_DebugFunctions ITM Functions 01554 \brief Functions that access the ITM debug interface. 01555 @{ 01556 */ 01557 01558 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 01559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 01560 01561 01562 /** \brief ITM Send Character 01563 01564 The function transmits a character via the ITM channel 0, and 01565 \li Just returns when no debugger is connected that has booked the output. 01566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 01567 01568 \param [in] ch Character to transmit. 01569 01570 \returns Character to transmit. 01571 */ 01572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 01573 { 01574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 01575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ 01576 { 01577 while (ITM->PORT[0].u32 == 0); 01578 ITM->PORT[0].u8 = (uint8_t) ch; 01579 } 01580 return (ch); 01581 } 01582 01583 01584 /** \brief ITM Receive Character 01585 01586 The function inputs a character via the external variable \ref ITM_RxBuffer. 01587 01588 \return Received character. 01589 \return -1 No character pending. 01590 */ 01591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 01592 int32_t ch = -1; /* no character available */ 01593 01594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 01595 ch = ITM_RxBuffer; 01596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 01597 } 01598 01599 return (ch); 01600 } 01601 01602 01603 /** \brief ITM Check Character 01604 01605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 01606 01607 \return 0 No character available. 01608 \return 1 Character available. 01609 */ 01610 __STATIC_INLINE int32_t ITM_CheckChar (void) { 01611 01612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 01613 return (0); /* no character available */ 01614 } else { 01615 return (1); /* character available */ 01616 } 01617 } 01618 01619 /*@} end of CMSIS_core_DebugFunctions */ 01620 01621 #endif /* __CORE_CM3_H_DEPENDANT */ 01622 01623 #endif /* __CMSIS_GENERIC */ 01624 01625 #ifdef __cplusplus 01626 } 01627 #endif
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