clock_11u6x.h

00001 /*
00002  * @brief LPC11U6X Clock control functions
00003  *
00004  * @note
00005  * Copyright(C) NXP Semiconductors, 2013
00006  * All rights reserved.
00007  *
00008  * @par
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * LPC products.  This software is supplied "AS IS" without any warranties of
00012  * any kind, and NXP Semiconductors and its licensor disclaim any and
00013  * all warranties, express or implied, including all implied warranties of
00014  * merchantability, fitness for a particular purpose and non-infringement of
00015  * intellectual property rights.  NXP Semiconductors assumes no responsibility
00016  * or liability for the use of the software, conveys no license or rights under any
00017  * patent, copyright, mask work right, or any other intellectual property rights in
00018  * or to any products. NXP Semiconductors reserves the right to make changes
00019  * in the software without notification. NXP Semiconductors also makes no
00020  * representation or warranty that such application will be suitable for the
00021  * specified use without further testing or modification.
00022  *
00023  * @par
00024  * Permission to use, copy, modify, and distribute this software and its
00025  * documentation is hereby granted, under NXP Semiconductors' and its
00026  * licensor's relevant copyrights in the software, without fee, provided that it
00027  * is used in conjunction with NXP Semiconductors microcontrollers.  This
00028  * copyright, permission, and disclaimer notice must appear in all copies of
00029  * this code.
00030  */
00031 
00032 #ifndef __CLOCK_11U6X_H_
00033 #define __CLOCK_11U6X_H_
00034 
00035 #include "lpc_defs.h"
00036 #define STATIC static
00037 #undef INLINE
00038 #undef bool
00039 #define INLINE inline
00040 #define bool unsigned char
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /** @defgroup CLOCK_11U6X CHIP: LPC11u6x Clock Control block driver
00047  * @ingroup CHIP_11U6X_Drivers
00048  * @{
00049  */
00050 
00051 /** Internal oscillator frequency */
00052 #define SYSCTL_IRC_FREQ (12000000)
00053 
00054 /**
00055  * @brief   Set System PLL divider values
00056  * @param   msel    : PLL feedback divider value. M = msel + 1.
00057  * @param   psel    : PLL post divider value. P =  (1<<psel).
00058  * @return  Nothing
00059  * @note    See the user manual for how to setup the PLL.
00060  */
00061 STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
00062 {
00063     LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
00064 }
00065 
00066 /**
00067  * @brief   Read System PLL lock status
00068  * @return  true of the PLL is locked. false if not locked
00069  */
00070 STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
00071 {
00072     return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
00073 }
00074 
00075 /**
00076  * Clock sources for system PLL
00077  */
00078 typedef enum CHIP_SYSCTL_PLLCLKSRC {
00079     SYSCTL_PLLCLKSRC_IRC  = 0,       /*!< Internal oscillator in */
00080     SYSCTL_PLLCLKSRC_MAINOSC ,       /*!< Crystal (main) oscillator in */
00081     SYSCTL_PLLCLKSRC_SYSOSC = SYSCTL_PLLCLKSRC_MAINOSC ,
00082     SYSCTL_PLLCLKSRC_RESERVED1 ,     /*!< Reserved */
00083     SYSCTL_PLLCLKSRC_RTC32K ,        /*!< RTC 32KHz clock */
00084 } CHIP_SYSCTL_PLLCLKSRC_T;
00085 
00086 /**
00087  * @brief   Set System PLL clock source
00088  * @param   src : Clock source for system PLL
00089  * @return  Nothing
00090  * @note    This function will also toggle the clock source update register
00091  * to update the clock source.
00092  */
00093 void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
00094 
00095 /**
00096  * @brief   Set USB PLL divider values
00097  * @param   msel    : PLL feedback divider value. M = msel + 1.
00098  * @param   psel    : PLL post divider value. P = (1<<psel).
00099  * @return  Nothing
00100  * @note    See the user manual for how to setup the PLL.
00101  */
00102 STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
00103 {
00104     LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
00105 }
00106 
00107 /**
00108  * @brief   Read USB PLL lock status
00109  * @return  true of the PLL is locked. false if not locked
00110  */
00111 STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
00112 {
00113     return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
00114 }
00115 
00116 /**
00117  * Clock sources for USB PLL
00118  */
00119 typedef enum CHIP_SYSCTL_USBPLLCLKSRC {
00120     SYSCTL_USBPLLCLKSRC_IRC  = 0,        /*!< Internal oscillator in */
00121     SYSCTL_USBPLLCLKSRC_MAINOSC ,        /*!< Crystal (main) oscillator in */
00122     SYSCTL_USBPLLCLKSRC_SYSOSC = SYSCTL_USBPLLCLKSRC_MAINOSC ,
00123     SYSCTL_USBPLLCLKSRC_RESERVED1 ,      /*!< Reserved */
00124     SYSCTL_USBPLLCLKSRC_RESERVED2 ,      /*!< Reserved */
00125 } CHIP_SYSCTL_USBPLLCLKSRC_T;
00126 
00127 /**
00128  * @brief   Set USB PLL clock source
00129  * @param   src : Clock source for USB PLL
00130  * @return  Nothing
00131  * @note    This function will also toggle the clock source update register
00132  * to update the clock source.
00133  */
00134 void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_USBPLLCLKSRC_T src);
00135 
00136 /**
00137  * @brief   Bypass System Oscillator and set oscillator frequency range
00138  * @param   bypass  : Flag to bypass oscillator
00139  * @param   highfr  : Flag to set oscillator range from 15-25 MHz
00140  * @return  Nothing
00141  * @note    Sets the PLL input to bypass the oscillator. This would be
00142  * used if an external clock that is not an oscillator is attached
00143  * to the XTALIN pin.
00144  */
00145 void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
00146 
00147 /**
00148  * @brief   Enable the RTC 32KHz output
00149  * @return  Nothing
00150  * @note    This clock can be used for the main clock directly, but
00151  *          do not use this clock with the system PLL.
00152  */
00153 STATIC INLINE void Chip_Clock_EnableRTCOsc(void)
00154 {
00155     LPC_SYSCTL->RTCOSCCTRL  = 1;
00156 }
00157 
00158 /**
00159  * @brief   Disable the RTC 32KHz output
00160  * @return  Nothing
00161  */
00162 STATIC INLINE void Chip_Clock_DisableRTCOsc(void)
00163 {
00164     LPC_SYSCTL->RTCOSCCTRL  = 0;
00165 }
00166 
00167 /**
00168  * Watchdog and low frequency oscillator frequencies plus or minus 40%
00169  */
00170 typedef enum CHIP_WDTLFO_OSC {
00171     WDTLFO_OSC_ILLEGAL,
00172     WDTLFO_OSC_0_60 ,    /*!< 0.6 MHz watchdog/LFO rate */
00173     WDTLFO_OSC_1_05 ,    /*!< 1.05 MHz watchdog/LFO rate */
00174     WDTLFO_OSC_1_40 ,    /*!< 1.4 MHz watchdog/LFO rate */
00175     WDTLFO_OSC_1_75 ,    /*!< 1.75 MHz watchdog/LFO rate */
00176     WDTLFO_OSC_2_10 ,    /*!< 2.1 MHz watchdog/LFO rate */
00177     WDTLFO_OSC_2_40 ,    /*!< 2.4 MHz watchdog/LFO rate */
00178     WDTLFO_OSC_2_70 ,    /*!< 2.7 MHz watchdog/LFO rate */
00179     WDTLFO_OSC_3_00 ,    /*!< 3.0 MHz watchdog/LFO rate */
00180     WDTLFO_OSC_3_25 ,    /*!< 3.25 MHz watchdog/LFO rate */
00181     WDTLFO_OSC_3_50 ,    /*!< 3.5 MHz watchdog/LFO rate */
00182     WDTLFO_OSC_3_75 ,    /*!< 3.75 MHz watchdog/LFO rate */
00183     WDTLFO_OSC_4_00 ,    /*!< 4.0 MHz watchdog/LFO rate */
00184     WDTLFO_OSC_4_20 ,    /*!< 4.2 MHz watchdog/LFO rate */
00185     WDTLFO_OSC_4_40 ,    /*!< 4.4 MHz watchdog/LFO rate */
00186     WDTLFO_OSC_4_60      /*!< 4.6 MHz watchdog/LFO rate */
00187 } CHIP_WDTLFO_OSC_T;
00188 
00189 /**
00190  * @brief   Setup Watchdog oscillator rate and divider
00191  * @param   wdtclk  : Selected watchdog clock rate
00192  * @param   div     : Watchdog divider value, even value between 2 and 64
00193  * @return  Nothing
00194  * @note    Watchdog rate = selected rate divided by divider rate
00195  */
00196 STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
00197 {
00198     LPC_SYSCTL->WDTOSCCTRL  = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
00199 }
00200 
00201 /**
00202  * Clock sources for main system clock
00203  */
00204 typedef enum CHIP_SYSCTL_MAINCLKSRC {
00205     SYSCTL_MAINCLKSRC_IRC  = 0,      /*!< Internal oscillator */
00206     SYSCTL_MAINCLKSRC_PLLIN ,        /*!< System PLL input */
00207     SYSCTL_MAINCLKSRC_WDTOSC ,       /*!< Watchdog oscillator rate */
00208     SYSCTL_MAINCLKSRC_PLLOUT ,       /*!< System PLL output */
00209 } CHIP_SYSCTL_MAINCLKSRC_T;
00210 
00211 /**
00212  * @brief   Set main system clock source
00213  * @param   src : Clock source for main system
00214  * @return  Nothing
00215  * @note    This function will also toggle the clock source update register
00216  * to update the clock source.
00217  */
00218 void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
00219 
00220 /**
00221  * @brief   Returns the main clock source
00222  * @return  Which clock is used for the core clock source?
00223  */
00224 STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
00225 {
00226     return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
00227 }
00228 
00229 /**
00230  * @brief   Set system clock divider
00231  * @param   div : divider for system clock
00232  * @return  Nothing
00233  * @note    Use 0 to disable, or a divider value of 1 to 255. The system clock
00234  * rate is the main system clock divided by this value.
00235  */
00236 STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
00237 {
00238     LPC_SYSCTL->SYSAHBCLKDIV  = div;
00239 }
00240 
00241 /**
00242  * System and peripheral clocks
00243  */
00244 typedef enum CHIP_SYSCTL_CLOCK {
00245     SYSCTL_CLOCK_SYS  = 0,               /*!< 0: System clock */
00246     SYSCTL_CLOCK_ROM ,                   /*!< 1:  ROM clock */
00247     SYSCTL_CLOCK_RAM0 ,                  /*!< 2: RAM0 clock */
00248     SYSCTL_CLOCK_FLASHREG ,              /*!< 3: FLASH register interface clock */
00249     SYSCTL_CLOCK_FLASHARRAY ,            /*!< 4: FLASH array access clock */
00250     SYSCTL_CLOCK_I2C0 ,                  /*!< 5: I2C0 clock */
00251     SYSCTL_CLOCK_GPIO ,                  /*!< 6: GPIO clock */
00252     SYSCTL_CLOCK_CT16B0 ,                /*!< 7: 16-bit Counter/timer 0 clock */
00253     SYSCTL_CLOCK_CT16B1 ,                /*!< 8: 16-bit Counter/timer 1 clock */
00254     SYSCTL_CLOCK_CT32B0 ,                /*!< 9: 32-bit Counter/timer 0 clock */
00255     SYSCTL_CLOCK_CT32B1 ,                /*!< 10: 32-bit Counter/timer 1 clock */
00256     SYSCTL_CLOCK_SSP0 ,                  /*!< 11: SSP0 clock */
00257     SYSCTL_CLOCK_UART0 ,                 /*!< 12: UART0 clock */
00258     SYSCTL_CLOCK_ADC ,                   /*!< 13: ADC clock */
00259     SYSCTL_CLOCK_USB ,                   /*!< 14: USB clock */
00260     SYSCTL_CLOCK_WDT ,                   /*!< 15: Watchdog timer clock */
00261     SYSCTL_CLOCK_IOCON ,                 /*!< 16: IOCON block clock */
00262     SYSCTL_CLOCK_RESERVED17 ,            /*!< 17: Reserved */
00263     SYSCTL_CLOCK_SSP1 ,                  /*!< 18: SSP1 clock */
00264     SYSCTL_CLOCK_PINT ,                  /*!< 19: GPIO Pin int register interface clock */
00265     SYSCTL_CLOCK_USART1 ,                /*!< 20: USART1 clock */
00266     SYSCTL_CLOCK_USART2 ,                /*!< 21: USART2 clock */
00267     SYSCTL_CLOCK_USART3_4 ,              /*!< 22: USART3_4 clock */
00268     SYSCTL_CLOCK_P0INT ,                 /*!< 23: GPIO GROUP1 interrupt register clock */
00269     SYSCTL_CLOCK_GROUP0INT  = SYSCTL_CLOCK_P0INT ,/*!< 23: GPIO GROUP0 interrupt register interface clock */
00270     SYSCTL_CLOCK_P1INT ,                 /*!< 24: GPIO GROUP1 interrupt register clock */
00271     SYSCTL_CLOCK_GROUP1INT  = SYSCTL_CLOCK_P1INT ,/*!< 24: GPIO GROUP1 interrupt register interface clock */
00272     SYSCTL_CLOCK_I2C1 ,                  /*!< 25: I2C1 clock */
00273     SYSCTL_CLOCK_RAM1 ,                  /*!< 26: SRAM block clock */
00274     SYSCTL_CLOCK_USBRAM ,                /*!< 27: USB SRAM block clock */
00275     SYSCTL_CLOCK_CRC ,                   /*!< 25: CRC clock */
00276     SYSCTL_CLOCK_DMA ,                   /*!< 25: DMA clock */
00277     SYSCTL_CLOCK_RTC ,                   /*!< 25: RTC clock */
00278     SYSCTL_CLOCK_SCT0_1 ,                /*!< 25: SCT 0/1 clock */
00279 } CHIP_SYSCTL_CLOCK_T;
00280 
00281 /**
00282  * @brief   Enable a system or peripheral clock
00283  * @param   clk : Clock to enable
00284  * @return  Nothing
00285  */
00286 STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
00287 {
00288     LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
00289 }
00290 
00291 /**
00292  * @brief   Disable a system or peripheral clock
00293  * @param   clk : Clock to disable
00294  * @return  Nothing
00295  */
00296 STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
00297 {
00298     LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
00299 }
00300 
00301 /**
00302  * @brief   Set SSP0 divider
00303  * @param   div : divider for SSP0 clock
00304  * @return  Nothing
00305  * @note    Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock
00306  * rate is the main system clock divided by this value.
00307  */
00308 STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
00309 {
00310     LPC_SYSCTL->SSP0CLKDIV  = div;
00311 }
00312 
00313 /**
00314  * @brief   Return SSP0 divider
00315  * @return  divider for SSP0 clock
00316  * @note    A value of 0 means the clock is disabled.
00317  */
00318 STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
00319 {
00320     return LPC_SYSCTL->SSP0CLKDIV;
00321 }
00322 
00323 /**
00324  * @brief   Set USART0 divider clock
00325  * @param   div : divider for UART clock
00326  * @return  Nothing
00327  * @note    Use 0 to disable, or a divider value of 1 to 255. The UART clock
00328  * rate is the main system clock divided by this value.
00329  */
00330 STATIC INLINE void Chip_Clock_SetUSART0ClockDiv(uint32_t div)
00331 {
00332     LPC_SYSCTL->USART0CLKDIV  = div;
00333 }
00334 
00335 /**
00336  * @brief   Return USART0 divider
00337  * @return  divider for UART clock
00338  * @note    A value of 0 means the clock is disabled.
00339  */
00340 STATIC INLINE uint32_t Chip_Clock_GetUASRT0ClockDiv(void)
00341 {
00342     return LPC_SYSCTL->USART0CLKDIV;
00343 }
00344 
00345 /**
00346  * @brief   Set SSP1 divider clock
00347  * @param   div : divider for SSP1 clock
00348  * @return  Nothing
00349  * @note    Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock
00350  * rate is the main system clock divided by this value.
00351  */
00352 STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
00353 {
00354     LPC_SYSCTL->SSP1CLKDIV  = div;
00355 }
00356 
00357 /**
00358  * @brief   Return SSP1 divider
00359  * @return  divider for SSP1 clock
00360  * @note    A value of 0 means the clock is disabled.
00361  */
00362 STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
00363 {
00364     return LPC_SYSCTL->SSP1CLKDIV;
00365 }
00366 
00367 /**
00368  * @brief   Set USART 1/2/3/4 UART base rate (up to main clock rate)
00369  * @param   rate    : Desired rate for fractional divider/multipler output
00370  * @param   fEnable : true to use fractional clocking, false for integer clocking
00371  * @return  Actual rate generated
00372  * @note    USARTs 1 - 4 use the same base clock for their baud rate
00373  *          basis. This function is used to generate that clock, while the
00374  *          UART driver's SetBaud functions will attempt to get the closest
00375  *          baud rate from this base clock without altering it. This needs
00376  *          to be setup prior to individual UART setup.<br>
00377  *          UARTs need a base clock 16x faster than the baud rate, so if you
00378  *          need a 115.2Kbps baud rate, you will need a clock rate of at
00379  *          least (115.2K * 16). The UART base clock is generated from the
00380  *          main system clock, so fractional clocking may be the only
00381  *          possible choice when using a low main system clock frequency.
00382  *          Do not alter the FRGCLKDIV register after this call.
00383  */
00384 uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable);
00385 
00386 /**
00387  * @brief   Get USART 1/2/3/4 UART base rate
00388  * @return  USART 1/2/3/4 UART base rate
00389  */
00390 uint32_t Chip_Clock_GetUSARTNBaseClockRate(void);
00391 
00392 /**
00393  * @brief   Set USART 1/2/3/4 fractional baud rate divider clock
00394  * @param   div : divider for USART 1/2/3/4 fractional baud rate clock
00395  * @return  Nothing
00396  * @note    Use 0 to disable, or a divider value of 1 to 255.
00397  * This does not affect USART0.
00398  */
00399 STATIC INLINE void Chip_Clock_SetUSARTNBaseClockDiv(uint8_t div)
00400 {
00401     LPC_SYSCTL->FRGCLKDIV = (uint32_t) div;
00402 }
00403 
00404 /**
00405  * @brief   Return USART 1/2/3/4 fractional baud rate divider
00406  * @return  divider for USART 1/2/3/4 fractional baud rate clock
00407  * @note    A value of 0 means the clock is disabled.
00408  * This does not affect USART0.
00409  */
00410 STATIC INLINE uint32_t Chip_Clock_GetUSARTNBaseClockDiv(void)
00411 {
00412     return LPC_SYSCTL->FRGCLKDIV;
00413 }
00414 
00415 /**
00416  * @brief   Set The USART Fractional Generator Divider
00417  * @param   div  :  Fractional Generator Divider value, should be 0xFF
00418  * @return  Nothing
00419  */
00420 STATIC INLINE void Chip_Clock_SetUSARTNFRGDivider(uint8_t div)
00421 {
00422     LPC_SYSCTL->UARTFRGDIV = (uint32_t) div;
00423 }
00424 
00425 /**
00426  * @brief   Set The USART Fractional Generator Divider
00427  * @return  Value of USART Fractional Generator Divider
00428  */
00429 STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGDivider(void)
00430 {
00431     return LPC_SYSCTL->UARTFRGDIV;
00432 }
00433 
00434 /**
00435  * @brief   Set The USART Fractional Generator Multiplier
00436  * @param   mult  :  An 8-bit value (0-255) U_PCLK = UARTCLKDIV/(1 + MULT/256)
00437  * @return  Nothing
00438  */
00439 STATIC INLINE void Chip_Clock_SetUSARTNFRGMultiplier(uint8_t mult)
00440 {
00441     LPC_SYSCTL->UARTFRGMULT = (uint32_t) mult;
00442 }
00443 
00444 /**
00445  * @brief   Get The USART Fractional Generator Multiplier
00446  * @return  Value of USART Fractional Generator Multiplier
00447  */
00448 STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGMultiplier(void)
00449 {
00450     return LPC_SYSCTL->UARTFRGMULT;
00451 }
00452 
00453 /**
00454  * Clock sources for USB
00455  */
00456 typedef enum CHIP_SYSCTL_USBCLKSRC {
00457     SYSCTL_USBCLKSRC_PLLOUT  = 0,    /*!< USB PLL out */
00458     SYSCTL_USBCLKSRC_MAINSYSCLK ,    /*!< Main system clock */
00459 } CHIP_SYSCTL_USBCLKSRC_T;
00460 
00461 /**
00462  * @brief   Set USB clock source and divider
00463  * @param   src : Clock source for USB
00464  * @param   div : divider for USB clock
00465  * @return  Nothing
00466  * @note    Use 0 to disable, or a divider value of 1 to 255. The USB clock
00467  * rate is either the main system clock or USB PLL output clock divided
00468  * by this value. This function will also toggle the clock source
00469  * update register to update the clock source.
00470  */
00471 void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
00472 
00473 /**
00474  * Clock sources for CLKOUT
00475  */
00476 typedef enum CHIP_SYSCTL_CLKOUTSRC {
00477     SYSCTL_CLKOUTSRC_IRC  = 0,       /*!< Internal oscillator for CLKOUT */
00478     SYSCTL_CLKOUTSRC_MAINOSC ,       /*!< Main oscillator for CLKOUT */
00479     SYSCTL_CLKOUTSRC_SYSOSC = SYSCTL_CLKOUTSRC_MAINOSC ,
00480     SYSCTL_CLKOUTSRC_WDTOSC ,        /*!< Watchdog oscillator for CLKOUT */
00481     SYSCTL_CLKOUTSRC_MAINSYSCLK ,    /*!< Main system clock for CLKOUT */
00482 } CHIP_SYSCTL_CLKOUTSRC_T;
00483 
00484 /**
00485  * @brief   Set CLKOUT clock source and divider
00486  * @param   src : Clock source for CLKOUT
00487  * @param   div : divider for CLKOUT clock
00488  * @return  Nothing
00489  * @note    Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
00490  * rate is the clock source divided by the divider. This function will
00491  * also toggle the clock source update register to update the clock
00492  * source.
00493  */
00494 void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
00495 
00496 /**
00497  * @brief   Set IOCON glitch filter clock divider value
00498  * @param   index   : IOCON divider index (0 - 6) to set
00499  * @param   div     : value for IOCON filter divider value
00500  * @return  Nothing
00501  * @note    Use 0 to disable, or a divider value of 1 to 255.
00502  */
00503 STATIC INLINE void Chip_Clock_SetIOCONFiltClockDiv(int index, uint32_t div)
00504 {
00505     LPC_SYSCTL->IOCONCLKDIV[6 - index]  = div;
00506 }
00507 
00508 /**
00509  * @brief   Return IOCON glitch filter clock divider value
00510  * @param   index   : IOCON divider index (0 - 6) to get
00511  * @return  IOCON glitch filter clock divider value
00512  */
00513 STATIC INLINE uint32_t Chip_Clock_GetIOCONFiltClockDiv(int index)
00514 {
00515     return LPC_SYSCTL->IOCONCLKDIV[6 - index];
00516 }
00517 
00518 /**
00519  * @brief   Returns the main oscillator clock rate
00520  * @return  main oscillator clock rate in Hz
00521  */
00522 STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
00523 {
00524     return 12000000; //OscRateIn;
00525 }
00526 
00527 /**
00528  * @brief   Returns the internal oscillator (IRC) clock rate
00529  * @return  internal oscillator (IRC) clock rate in Hz
00530  */
00531 STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
00532 {
00533     return SYSCTL_IRC_FREQ;
00534 }
00535 
00536 /**
00537  * @brief   Returns the RTC clock rate
00538  * @return  RTC oscillator clock rate in Hz
00539  */
00540 STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate(void)
00541 {
00542     return 32768;//RTCOscRateIn;
00543 }
00544 
00545 /**
00546  * @brief   Return estimated watchdog oscillator rate
00547  * @return  Estimated watchdog oscillator rate
00548  * @note    This rate is accurate to plus or minus 40%.
00549  */
00550 uint32_t Chip_Clock_GetWDTOSCRate(void);
00551 
00552 /**
00553  * @brief   Return System PLL input clock rate
00554  * @return  System PLL input clock rate
00555  */
00556 uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
00557 
00558 /**
00559  * @brief   Return System PLL output clock rate
00560  * @return  System PLL output clock rate
00561  */
00562 uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
00563 
00564 /**
00565  * @brief   Return USB PLL input clock rate
00566  * @return  USB PLL input clock rate
00567  */
00568 uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
00569 
00570 /**
00571  * @brief   Return USB PLL output clock rate
00572  * @return  USB PLL output clock rate
00573  */
00574 uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
00575 
00576 /**
00577  * @brief   Return main clock rate
00578  * @return  main clock rate
00579  */
00580 uint32_t Chip_Clock_GetMainClockRate(void);
00581 
00582 /**
00583  * @brief   Return system clock rate
00584  * @return  system clock rate
00585  */
00586 uint32_t Chip_Clock_GetSystemClockRate(void);
00587 
00588 /**
00589  * @}
00590  */
00591 
00592 #ifdef __cplusplus
00593 }
00594 #endif
00595 
00596 #endif /* __CLOCK_11U6X_H_ */
00597