AD9249.h

00001 #ifndef AD9249_H
00002 #define AD9249_H
00003 /*  interface for controlling the AD9249 ADC ,  16 channel ADC  Analog Devices
00004 
00005 -only one CSB line , so assumes the pins CSB1 and CSB2 are connected together . 
00006 -only MSB mode is supported,  so configuration register MSB is set at the start. 
00007 
00008 
00009 W. Beaumont 
00010 (C) Universiteit Antwerpen  27 August 2014 
00011 
00012 */ 
00013 
00014 #define AD9249_HDR_VER  "1.22" 
00015 #include "getVersion.h"
00016 
00017 class SWSPI_BI;
00018 //class DigitalIn; 
00019 
00020 class AD9249: public getVersion {
00021     typedef  unsigned char u8;
00022     typedef  unsigned int u32;
00023     typedef  unsigned short u16;
00024 // address defs     
00025     static const u16 configreg =            0x0;
00026     static const u16 chip_id_reg =          0x1;
00027     static const u16 chip_grade_reg =       0x2;
00028    // static const u16 unused_reg= { 0x3, 0x07, 0xA, 0xE, 0xF ,0x11, 0x12,0x13, 0x17, 0x1D, 0x1E, 0x1F,0x20 };
00029     static const u16 dev_index2_reg =       0x4;
00030     static const u16 dev_index1_reg =       0x4;
00031     static const u16 transfer_reg =         0xFF;
00032     static const u16 power_mode_reg =       0x8;
00033     static const u16 clock_gobal_reg =      0x9;
00034     static const u16 clock_divide_reg =     0xB;
00035     static const u16 enhancement_ctr_reg =  0xC;
00036     static const u16 test_mode_reg =        0xD;
00037     static const u16 offset_adj_reg =       0x10;
00038     static const u16 output_mode_reg =      0x14;
00039     static const u16 output_adj_reg =       0x15;
00040     static const u16 output_phase_reg =     0x16;
00041     static const u16 vref_reg =             0x18;
00042     static const u16 usserpatt1_LSB_reg =   0x19;
00043     static const u16 usserpatt1_MSB_reg =   0x1A;
00044     static const u16 usserpatt2_LSB_reg =   0x1B;
00045     static const u16 usserpatt2_MSB_reg =   0x1C;
00046     static const u16 serial_out_cntr_reg =  0x21;
00047     static const u16 serial_status_reg =    0x22;
00048     static const u16 sample_rate_reg =      0x100;
00049     static const u16 user_io_ctr2_reg =     0x101;
00050     static const u16 user_io_ctr3_reg =     0x102;
00051     static const u16 sync_reg =             0x109;
00052    
00053     u32 spi_cycle(u16 reg, bool rw, u16 nrbytes, u32 data);
00054     SWSPI_BI * spi;
00055     DigitalOut * csb;    
00056     public:
00057         AD9249(SWSPI_BI * spi_dev, DigitalOut * csb_dev);
00058         bool getDevInfo(u8& chipid, u8& grade, u16& rb);
00059         bool getDevId(u8& chipid);
00060         bool getGrade(u8& grade); 
00061         bool setPattern1(u16 pattern);
00062         bool setPattern2(u16 pattern);
00063         bool readPattern1(u16& pattern);
00064         bool readPattern2(u16& pattern);
00065         //general read write 
00066         bool setReg16(u16 regaddr, u16 data);
00067         bool setReg8(u16 regaddr, u8 data);
00068         bool readReg16(u16 regaddr, u16& data);
00069         bool readReg8(u16 regaddr, u8& data);   
00070         void init1();
00071         void init2();
00072 };
00073 
00074 #endif