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targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Update mbed sources to revision 64

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 13:0645d8841f51 1
bogdanm 13:0645d8841f51 2 /****************************************************************************************************//**
bogdanm 13:0645d8841f51 3 * @file LPC13Uxx.h
bogdanm 13:0645d8841f51 4 *
bogdanm 13:0645d8841f51 5 *
bogdanm 13:0645d8841f51 6 *
bogdanm 13:0645d8841f51 7 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
bogdanm 13:0645d8841f51 8 * default LPC13Uxx Device Series
bogdanm 13:0645d8841f51 9 *
bogdanm 13:0645d8841f51 10 * @version V0.1
bogdanm 13:0645d8841f51 11 * @date 18. Jan 2012
bogdanm 13:0645d8841f51 12 *
bogdanm 13:0645d8841f51 13 * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
bogdanm 13:0645d8841f51 14 *
bogdanm 13:0645d8841f51 15 * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
bogdanm 13:0645d8841f51 16 * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
bogdanm 13:0645d8841f51 17 *
bogdanm 13:0645d8841f51 18 *******************************************************************************************************/
bogdanm 13:0645d8841f51 19
bogdanm 13:0645d8841f51 20 /** @addtogroup NXP
bogdanm 13:0645d8841f51 21 * @{
bogdanm 13:0645d8841f51 22 */
bogdanm 13:0645d8841f51 23
bogdanm 13:0645d8841f51 24 /** @addtogroup LPC13Uxx
bogdanm 13:0645d8841f51 25 * @{
bogdanm 13:0645d8841f51 26 */
bogdanm 13:0645d8841f51 27
bogdanm 13:0645d8841f51 28 #ifndef __LPC13UXX_H__
bogdanm 13:0645d8841f51 29 #define __LPC13UXX_H__
bogdanm 13:0645d8841f51 30
bogdanm 13:0645d8841f51 31 #ifdef __cplusplus
bogdanm 13:0645d8841f51 32 extern "C" {
bogdanm 13:0645d8841f51 33 #endif
bogdanm 13:0645d8841f51 34
bogdanm 13:0645d8841f51 35
bogdanm 13:0645d8841f51 36 #if defined ( __CC_ARM )
bogdanm 13:0645d8841f51 37 #pragma anon_unions
bogdanm 13:0645d8841f51 38 #endif
bogdanm 13:0645d8841f51 39
bogdanm 13:0645d8841f51 40 /* Interrupt Number Definition */
bogdanm 13:0645d8841f51 41
bogdanm 13:0645d8841f51 42 typedef enum {
bogdanm 13:0645d8841f51 43 // ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
bogdanm 13:0645d8841f51 44 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 13:0645d8841f51 45 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 13:0645d8841f51 46 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 13:0645d8841f51 47 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
bogdanm 13:0645d8841f51 48 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
bogdanm 13:0645d8841f51 49 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
bogdanm 13:0645d8841f51 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
bogdanm 13:0645d8841f51 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
bogdanm 13:0645d8841f51 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
bogdanm 13:0645d8841f51 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
bogdanm 13:0645d8841f51 54 // ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
bogdanm 13:0645d8841f51 55 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
bogdanm 13:0645d8841f51 56 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
bogdanm 13:0645d8841f51 57 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
bogdanm 13:0645d8841f51 58 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
bogdanm 13:0645d8841f51 59 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
bogdanm 13:0645d8841f51 60 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
bogdanm 13:0645d8841f51 61 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
bogdanm 13:0645d8841f51 62 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
bogdanm 13:0645d8841f51 63 GINT0_IRQn = 8, /*!< 8 GINT0 */
bogdanm 13:0645d8841f51 64 GINT1_IRQn = 9, /*!< 9 GINT1 */
bogdanm 13:0645d8841f51 65 Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
bogdanm 13:0645d8841f51 66 Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
bogdanm 13:0645d8841f51 67 RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
bogdanm 13:0645d8841f51 68 Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
bogdanm 13:0645d8841f51 69 SSP1_IRQn = 14, /*!< 14 SSP1 */
bogdanm 13:0645d8841f51 70 I2C_IRQn = 15, /*!< 15 I2C */
bogdanm 13:0645d8841f51 71 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
bogdanm 13:0645d8841f51 72 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
bogdanm 13:0645d8841f51 73 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
bogdanm 13:0645d8841f51 74 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
bogdanm 13:0645d8841f51 75 SSP0_IRQn = 20, /*!< 20 SSP0 */
bogdanm 13:0645d8841f51 76 USART_IRQn = 21, /*!< 21 USART */
bogdanm 13:0645d8841f51 77 USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
bogdanm 13:0645d8841f51 78 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
bogdanm 13:0645d8841f51 79 ADC_IRQn = 24, /*!< 24 ADC */
bogdanm 13:0645d8841f51 80 WDT_IRQn = 25, /*!< 25 WDT */
bogdanm 13:0645d8841f51 81 BOD_IRQn = 26, /*!< 26 BOD */
bogdanm 13:0645d8841f51 82 FMC_IRQn = 27, /*!< 27 FMC */
bogdanm 13:0645d8841f51 83 Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
bogdanm 13:0645d8841f51 84 Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
bogdanm 13:0645d8841f51 85 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
bogdanm 13:0645d8841f51 86 Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
bogdanm 13:0645d8841f51 87 } IRQn_Type;
bogdanm 13:0645d8841f51 88
bogdanm 13:0645d8841f51 89
bogdanm 13:0645d8841f51 90 /** @addtogroup Configuration_of_CMSIS
bogdanm 13:0645d8841f51 91 * @{
bogdanm 13:0645d8841f51 92 */
bogdanm 13:0645d8841f51 93
bogdanm 13:0645d8841f51 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
bogdanm 13:0645d8841f51 95
bogdanm 13:0645d8841f51 96 #define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
bogdanm 13:0645d8841f51 97 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 13:0645d8841f51 98 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
bogdanm 13:0645d8841f51 99 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 13:0645d8841f51 100 /** @} */ /* End of group Configuration_of_CMSIS */
bogdanm 13:0645d8841f51 101
bogdanm 13:0645d8841f51 102 #include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
bogdanm 13:0645d8841f51 103 #include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
bogdanm 13:0645d8841f51 104
bogdanm 13:0645d8841f51 105 /** @addtogroup Device_Peripheral_Registers
bogdanm 13:0645d8841f51 106 * @{
bogdanm 13:0645d8841f51 107 */
bogdanm 13:0645d8841f51 108
bogdanm 13:0645d8841f51 109
bogdanm 13:0645d8841f51 110 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 111 // ----- I2C -----
bogdanm 13:0645d8841f51 112 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 113
bogdanm 13:0645d8841f51 114
bogdanm 13:0645d8841f51 115
bogdanm 13:0645d8841f51 116 typedef struct { /*!< (@ 0x40000000) I2C Structure */
bogdanm 13:0645d8841f51 117 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
bogdanm 13:0645d8841f51 118 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
bogdanm 13:0645d8841f51 119 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
bogdanm 13:0645d8841f51 120 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
bogdanm 13:0645d8841f51 121 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
bogdanm 13:0645d8841f51 122 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
bogdanm 13:0645d8841f51 123 __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
bogdanm 13:0645d8841f51 124 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
bogdanm 13:0645d8841f51 125 union{
bogdanm 13:0645d8841f51 126 __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
bogdanm 13:0645d8841f51 127 struct{
bogdanm 13:0645d8841f51 128 __IO uint32_t ADR1;
bogdanm 13:0645d8841f51 129 __IO uint32_t ADR2;
bogdanm 13:0645d8841f51 130 __IO uint32_t ADR3;
bogdanm 13:0645d8841f51 131 };
bogdanm 13:0645d8841f51 132 };
bogdanm 13:0645d8841f51 133 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
bogdanm 13:0645d8841f51 134 union{
bogdanm 13:0645d8841f51 135 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
bogdanm 13:0645d8841f51 136 struct{
bogdanm 13:0645d8841f51 137 __IO uint32_t MASK0;
bogdanm 13:0645d8841f51 138 __IO uint32_t MASK1;
bogdanm 13:0645d8841f51 139 __IO uint32_t MASK2;
bogdanm 13:0645d8841f51 140 __IO uint32_t MASK3;
bogdanm 13:0645d8841f51 141 };
bogdanm 13:0645d8841f51 142 };
bogdanm 13:0645d8841f51 143 } LPC_I2C_Type;
bogdanm 13:0645d8841f51 144
bogdanm 13:0645d8841f51 145
bogdanm 13:0645d8841f51 146 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 147 // ----- WWDT -----
bogdanm 13:0645d8841f51 148 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 149
bogdanm 13:0645d8841f51 150
bogdanm 13:0645d8841f51 151 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
bogdanm 13:0645d8841f51 152 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
bogdanm 13:0645d8841f51 153 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
bogdanm 13:0645d8841f51 154 __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
bogdanm 13:0645d8841f51 155 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
bogdanm 13:0645d8841f51 156 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
bogdanm 13:0645d8841f51 157 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
bogdanm 13:0645d8841f51 158 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
bogdanm 13:0645d8841f51 159 } LPC_WWDT_Type;
bogdanm 13:0645d8841f51 160
bogdanm 13:0645d8841f51 161
bogdanm 13:0645d8841f51 162 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 163 // ----- USART -----
bogdanm 13:0645d8841f51 164 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 165
bogdanm 13:0645d8841f51 166
bogdanm 13:0645d8841f51 167 typedef struct { /*!< (@ 0x40008000) USART Structure */
bogdanm 13:0645d8841f51 168
bogdanm 13:0645d8841f51 169 union {
bogdanm 13:0645d8841f51 170 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
bogdanm 13:0645d8841f51 171 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
bogdanm 13:0645d8841f51 172 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
bogdanm 13:0645d8841f51 173 };
bogdanm 13:0645d8841f51 174
bogdanm 13:0645d8841f51 175 union {
bogdanm 13:0645d8841f51 176 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
bogdanm 13:0645d8841f51 177 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
bogdanm 13:0645d8841f51 178 };
bogdanm 13:0645d8841f51 179
bogdanm 13:0645d8841f51 180 union {
bogdanm 13:0645d8841f51 181 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
bogdanm 13:0645d8841f51 182 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
bogdanm 13:0645d8841f51 183 };
bogdanm 13:0645d8841f51 184 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
bogdanm 13:0645d8841f51 185 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
bogdanm 13:0645d8841f51 186 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
bogdanm 13:0645d8841f51 187 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
bogdanm 13:0645d8841f51 188 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
bogdanm 13:0645d8841f51 189 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
bogdanm 13:0645d8841f51 190 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
bogdanm 13:0645d8841f51 191 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
bogdanm 13:0645d8841f51 192 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
bogdanm 13:0645d8841f51 193 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
bogdanm 13:0645d8841f51 194 __I uint32_t RESERVED0[3];
bogdanm 13:0645d8841f51 195 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
bogdanm 13:0645d8841f51 196 __I uint32_t RESERVED1;
bogdanm 13:0645d8841f51 197 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
bogdanm 13:0645d8841f51 198 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
bogdanm 13:0645d8841f51 199 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
bogdanm 13:0645d8841f51 200 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
bogdanm 13:0645d8841f51 201 __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
bogdanm 13:0645d8841f51 202 } LPC_USART_Type;
bogdanm 13:0645d8841f51 203
bogdanm 13:0645d8841f51 204
bogdanm 13:0645d8841f51 205 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 206 // ----- CT16B0 -----
bogdanm 13:0645d8841f51 207 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 208
bogdanm 13:0645d8841f51 209 typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
bogdanm 13:0645d8841f51 210 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
bogdanm 13:0645d8841f51 211 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
bogdanm 13:0645d8841f51 212 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
bogdanm 13:0645d8841f51 213 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
bogdanm 13:0645d8841f51 214 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
bogdanm 13:0645d8841f51 215 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
bogdanm 13:0645d8841f51 216 union {
bogdanm 13:0645d8841f51 217 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
bogdanm 13:0645d8841f51 218 struct{
bogdanm 13:0645d8841f51 219 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
bogdanm 13:0645d8841f51 220 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
bogdanm 13:0645d8841f51 221 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
bogdanm 13:0645d8841f51 222 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
bogdanm 13:0645d8841f51 223 };
bogdanm 13:0645d8841f51 224 };
bogdanm 13:0645d8841f51 225 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
bogdanm 13:0645d8841f51 226 union{
bogdanm 13:0645d8841f51 227 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
bogdanm 13:0645d8841f51 228 struct{
bogdanm 13:0645d8841f51 229 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
bogdanm 13:0645d8841f51 230 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
bogdanm 13:0645d8841f51 231 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
bogdanm 13:0645d8841f51 232 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
bogdanm 13:0645d8841f51 233 };
bogdanm 13:0645d8841f51 234 };
bogdanm 13:0645d8841f51 235 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
bogdanm 13:0645d8841f51 236 __I uint32_t RESERVED0[12];
bogdanm 13:0645d8841f51 237 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
bogdanm 13:0645d8841f51 238 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
bogdanm 13:0645d8841f51 239 } LPC_CTxxBx_Type;
bogdanm 13:0645d8841f51 240
bogdanm 13:0645d8841f51 241 typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
bogdanm 13:0645d8841f51 242 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
bogdanm 13:0645d8841f51 243 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
bogdanm 13:0645d8841f51 244 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
bogdanm 13:0645d8841f51 245 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
bogdanm 13:0645d8841f51 246 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
bogdanm 13:0645d8841f51 247 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
bogdanm 13:0645d8841f51 248 union {
bogdanm 13:0645d8841f51 249 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
bogdanm 13:0645d8841f51 250 struct{
bogdanm 13:0645d8841f51 251 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
bogdanm 13:0645d8841f51 252 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
bogdanm 13:0645d8841f51 253 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
bogdanm 13:0645d8841f51 254 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
bogdanm 13:0645d8841f51 255 };
bogdanm 13:0645d8841f51 256 };
bogdanm 13:0645d8841f51 257 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
bogdanm 13:0645d8841f51 258 union{
bogdanm 13:0645d8841f51 259 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
bogdanm 13:0645d8841f51 260 struct{
bogdanm 13:0645d8841f51 261 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
bogdanm 13:0645d8841f51 262 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
bogdanm 13:0645d8841f51 263 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
bogdanm 13:0645d8841f51 264 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
bogdanm 13:0645d8841f51 265 };
bogdanm 13:0645d8841f51 266 };
bogdanm 13:0645d8841f51 267 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
bogdanm 13:0645d8841f51 268 __I uint32_t RESERVED0[12];
bogdanm 13:0645d8841f51 269 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
bogdanm 13:0645d8841f51 270 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
bogdanm 13:0645d8841f51 271 } LPC_CT16B0_Type;
bogdanm 13:0645d8841f51 272
bogdanm 13:0645d8841f51 273
bogdanm 13:0645d8841f51 274 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 275 // ----- CT16B1 -----
bogdanm 13:0645d8841f51 276 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 277
bogdanm 13:0645d8841f51 278 typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
bogdanm 13:0645d8841f51 279 __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
bogdanm 13:0645d8841f51 280 __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
bogdanm 13:0645d8841f51 281 __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
bogdanm 13:0645d8841f51 282 __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
bogdanm 13:0645d8841f51 283 __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
bogdanm 13:0645d8841f51 284 __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
bogdanm 13:0645d8841f51 285 union {
bogdanm 13:0645d8841f51 286 __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
bogdanm 13:0645d8841f51 287 struct{
bogdanm 13:0645d8841f51 288 __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
bogdanm 13:0645d8841f51 289 __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
bogdanm 13:0645d8841f51 290 __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
bogdanm 13:0645d8841f51 291 __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
bogdanm 13:0645d8841f51 292 };
bogdanm 13:0645d8841f51 293 };
bogdanm 13:0645d8841f51 294 __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
bogdanm 13:0645d8841f51 295 union{
bogdanm 13:0645d8841f51 296 __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
bogdanm 13:0645d8841f51 297 struct{
bogdanm 13:0645d8841f51 298 __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
bogdanm 13:0645d8841f51 299 __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
bogdanm 13:0645d8841f51 300 __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
bogdanm 13:0645d8841f51 301 __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
bogdanm 13:0645d8841f51 302 };
bogdanm 13:0645d8841f51 303 };
bogdanm 13:0645d8841f51 304 __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
bogdanm 13:0645d8841f51 305 __I uint32_t RESERVED0[12];
bogdanm 13:0645d8841f51 306 __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
bogdanm 13:0645d8841f51 307 __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
bogdanm 13:0645d8841f51 308 } LPC_CT16B1_Type;
bogdanm 13:0645d8841f51 309
bogdanm 13:0645d8841f51 310
bogdanm 13:0645d8841f51 311 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 312 // ----- CT32B0 -----
bogdanm 13:0645d8841f51 313 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 314 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
bogdanm 13:0645d8841f51 315 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
bogdanm 13:0645d8841f51 316 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
bogdanm 13:0645d8841f51 317 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
bogdanm 13:0645d8841f51 318 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
bogdanm 13:0645d8841f51 319 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
bogdanm 13:0645d8841f51 320 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
bogdanm 13:0645d8841f51 321 union {
bogdanm 13:0645d8841f51 322 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
bogdanm 13:0645d8841f51 323 struct{
bogdanm 13:0645d8841f51 324 __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
bogdanm 13:0645d8841f51 325 __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
bogdanm 13:0645d8841f51 326 __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
bogdanm 13:0645d8841f51 327 __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
bogdanm 13:0645d8841f51 328 };
bogdanm 13:0645d8841f51 329 };
bogdanm 13:0645d8841f51 330 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
bogdanm 13:0645d8841f51 331 union{
bogdanm 13:0645d8841f51 332 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
bogdanm 13:0645d8841f51 333 struct{
bogdanm 13:0645d8841f51 334 __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
bogdanm 13:0645d8841f51 335 __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
bogdanm 13:0645d8841f51 336 __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
bogdanm 13:0645d8841f51 337 __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
bogdanm 13:0645d8841f51 338 };
bogdanm 13:0645d8841f51 339 };
bogdanm 13:0645d8841f51 340 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
bogdanm 13:0645d8841f51 341 __I uint32_t RESERVED0[12];
bogdanm 13:0645d8841f51 342 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
bogdanm 13:0645d8841f51 343 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
bogdanm 13:0645d8841f51 344 } LPC_CT32B0_Type;
bogdanm 13:0645d8841f51 345
bogdanm 13:0645d8841f51 346
bogdanm 13:0645d8841f51 347 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 348 // ----- CT32B1 -----
bogdanm 13:0645d8841f51 349 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 350 typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
bogdanm 13:0645d8841f51 351 __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
bogdanm 13:0645d8841f51 352 __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
bogdanm 13:0645d8841f51 353 __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
bogdanm 13:0645d8841f51 354 __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
bogdanm 13:0645d8841f51 355 __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
bogdanm 13:0645d8841f51 356 __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
bogdanm 13:0645d8841f51 357 union {
bogdanm 13:0645d8841f51 358 __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
bogdanm 13:0645d8841f51 359 struct{
bogdanm 13:0645d8841f51 360 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
bogdanm 13:0645d8841f51 361 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
bogdanm 13:0645d8841f51 362 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
bogdanm 13:0645d8841f51 363 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
bogdanm 13:0645d8841f51 364 };
bogdanm 13:0645d8841f51 365 };
bogdanm 13:0645d8841f51 366 __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
bogdanm 13:0645d8841f51 367 union{
bogdanm 13:0645d8841f51 368 __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
bogdanm 13:0645d8841f51 369 struct{
bogdanm 13:0645d8841f51 370 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
bogdanm 13:0645d8841f51 371 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
bogdanm 13:0645d8841f51 372 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
bogdanm 13:0645d8841f51 373 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
bogdanm 13:0645d8841f51 374 };
bogdanm 13:0645d8841f51 375 };
bogdanm 13:0645d8841f51 376 __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
bogdanm 13:0645d8841f51 377 __I uint32_t RESERVED0[12];
bogdanm 13:0645d8841f51 378 __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
bogdanm 13:0645d8841f51 379 __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
bogdanm 13:0645d8841f51 380 } LPC_CT32B1_Type;
bogdanm 13:0645d8841f51 381
bogdanm 13:0645d8841f51 382
bogdanm 13:0645d8841f51 383 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 384 // ----- ADC -----
bogdanm 13:0645d8841f51 385 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 386 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
bogdanm 13:0645d8841f51 387 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
bogdanm 13:0645d8841f51 388 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
bogdanm 13:0645d8841f51 389 __I uint32_t RESERVED0[1];
bogdanm 13:0645d8841f51 390 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
bogdanm 13:0645d8841f51 391 union{
bogdanm 13:0645d8841f51 392 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
bogdanm 13:0645d8841f51 393 struct{
bogdanm 13:0645d8841f51 394 __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
bogdanm 13:0645d8841f51 395 __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
bogdanm 13:0645d8841f51 396 __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
bogdanm 13:0645d8841f51 397 __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
bogdanm 13:0645d8841f51 398 __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
bogdanm 13:0645d8841f51 399 __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
bogdanm 13:0645d8841f51 400 __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
bogdanm 13:0645d8841f51 401 __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
bogdanm 13:0645d8841f51 402 };
bogdanm 13:0645d8841f51 403 };
bogdanm 13:0645d8841f51 404 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
bogdanm 13:0645d8841f51 405 } LPC_ADC_Type;
bogdanm 13:0645d8841f51 406
bogdanm 13:0645d8841f51 407
bogdanm 13:0645d8841f51 408 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 409 // ----- PMU -----
bogdanm 13:0645d8841f51 410 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 411
bogdanm 13:0645d8841f51 412 typedef struct { /*!< (@ 0x40038000) PMU Structure */
bogdanm 13:0645d8841f51 413 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
bogdanm 13:0645d8841f51 414 union{
bogdanm 13:0645d8841f51 415 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
bogdanm 13:0645d8841f51 416 struct{
bogdanm 13:0645d8841f51 417 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
bogdanm 13:0645d8841f51 418 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
bogdanm 13:0645d8841f51 419 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
bogdanm 13:0645d8841f51 420 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
bogdanm 13:0645d8841f51 421 };
bogdanm 13:0645d8841f51 422 };
bogdanm 13:0645d8841f51 423 __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
bogdanm 13:0645d8841f51 424 } LPC_PMU_Type;
bogdanm 13:0645d8841f51 425
bogdanm 13:0645d8841f51 426
bogdanm 13:0645d8841f51 427 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 428 // ----- FLASHCTRL -----
bogdanm 13:0645d8841f51 429 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 430
bogdanm 13:0645d8841f51 431 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
bogdanm 13:0645d8841f51 432 __I uint32_t RESERVED0[4];
bogdanm 13:0645d8841f51 433 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
bogdanm 13:0645d8841f51 434 __I uint32_t RESERVED1[3];
bogdanm 13:0645d8841f51 435 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
bogdanm 13:0645d8841f51 436 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
bogdanm 13:0645d8841f51 437 __I uint32_t RESERVED2[1];
bogdanm 13:0645d8841f51 438 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
bogdanm 13:0645d8841f51 439 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
bogdanm 13:0645d8841f51 440 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
bogdanm 13:0645d8841f51 441 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
bogdanm 13:0645d8841f51 442 __I uint32_t RESERVED3[1001];
bogdanm 13:0645d8841f51 443 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
bogdanm 13:0645d8841f51 444 __I uint32_t RESERVED4[1];
bogdanm 13:0645d8841f51 445 __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
bogdanm 13:0645d8841f51 446 } LPC_FLASHCTRL_Type;
bogdanm 13:0645d8841f51 447
bogdanm 13:0645d8841f51 448
bogdanm 13:0645d8841f51 449 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 450 // ----- SSP -----
bogdanm 13:0645d8841f51 451 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 452 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
bogdanm 13:0645d8841f51 453 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
bogdanm 13:0645d8841f51 454 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
bogdanm 13:0645d8841f51 455 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
bogdanm 13:0645d8841f51 456 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
bogdanm 13:0645d8841f51 457 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
bogdanm 13:0645d8841f51 458 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
bogdanm 13:0645d8841f51 459 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
bogdanm 13:0645d8841f51 460 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
bogdanm 13:0645d8841f51 461 __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
bogdanm 13:0645d8841f51 462 } LPC_SSPx_Type;
bogdanm 13:0645d8841f51 463
bogdanm 13:0645d8841f51 464
bogdanm 13:0645d8841f51 465 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 466 // ----- IOCON -----
bogdanm 13:0645d8841f51 467 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 468 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
bogdanm 13:0645d8841f51 469 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
bogdanm 13:0645d8841f51 470 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
bogdanm 13:0645d8841f51 471 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
bogdanm 13:0645d8841f51 472 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
bogdanm 13:0645d8841f51 473 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
bogdanm 13:0645d8841f51 474 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
bogdanm 13:0645d8841f51 475 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
bogdanm 13:0645d8841f51 476 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
bogdanm 13:0645d8841f51 477 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
bogdanm 13:0645d8841f51 478 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
bogdanm 13:0645d8841f51 479 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
bogdanm 13:0645d8841f51 480 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
bogdanm 13:0645d8841f51 481 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
bogdanm 13:0645d8841f51 482 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
bogdanm 13:0645d8841f51 483 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
bogdanm 13:0645d8841f51 484 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
bogdanm 13:0645d8841f51 485 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
bogdanm 13:0645d8841f51 486 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
bogdanm 13:0645d8841f51 487 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
bogdanm 13:0645d8841f51 488 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
bogdanm 13:0645d8841f51 489 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
bogdanm 13:0645d8841f51 490 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
bogdanm 13:0645d8841f51 491 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
bogdanm 13:0645d8841f51 492 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
bogdanm 13:0645d8841f51 493 __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
bogdanm 13:0645d8841f51 494 __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
bogdanm 13:0645d8841f51 495 __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
bogdanm 13:0645d8841f51 496 __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
bogdanm 13:0645d8841f51 497 __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
bogdanm 13:0645d8841f51 498 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
bogdanm 13:0645d8841f51 499 __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
bogdanm 13:0645d8841f51 500 __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
bogdanm 13:0645d8841f51 501 __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
bogdanm 13:0645d8841f51 502 __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
bogdanm 13:0645d8841f51 503 __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
bogdanm 13:0645d8841f51 504 __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
bogdanm 13:0645d8841f51 505 __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
bogdanm 13:0645d8841f51 506 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
bogdanm 13:0645d8841f51 507 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
bogdanm 13:0645d8841f51 508 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
bogdanm 13:0645d8841f51 509 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
bogdanm 13:0645d8841f51 510 __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
bogdanm 13:0645d8841f51 511 __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
bogdanm 13:0645d8841f51 512 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
bogdanm 13:0645d8841f51 513 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
bogdanm 13:0645d8841f51 514 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
bogdanm 13:0645d8841f51 515 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
bogdanm 13:0645d8841f51 516 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
bogdanm 13:0645d8841f51 517 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
bogdanm 13:0645d8841f51 518 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
bogdanm 13:0645d8841f51 519 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
bogdanm 13:0645d8841f51 520 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
bogdanm 13:0645d8841f51 521 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
bogdanm 13:0645d8841f51 522 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
bogdanm 13:0645d8841f51 523 __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
bogdanm 13:0645d8841f51 524 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
bogdanm 13:0645d8841f51 525 } LPC_IOCON_Type;
bogdanm 13:0645d8841f51 526
bogdanm 13:0645d8841f51 527
bogdanm 13:0645d8841f51 528 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 529 // ----- SYSCON -----
bogdanm 13:0645d8841f51 530 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 531
bogdanm 13:0645d8841f51 532 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
bogdanm 13:0645d8841f51 533 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
bogdanm 13:0645d8841f51 534 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
bogdanm 13:0645d8841f51 535 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
bogdanm 13:0645d8841f51 536 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
bogdanm 13:0645d8841f51 537 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
bogdanm 13:0645d8841f51 538 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
bogdanm 13:0645d8841f51 539 __I uint32_t RESERVED0[2];
bogdanm 13:0645d8841f51 540 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
bogdanm 13:0645d8841f51 541 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
bogdanm 13:0645d8841f51 542 __I uint32_t RESERVED1[2];
bogdanm 13:0645d8841f51 543 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
bogdanm 13:0645d8841f51 544 __I uint32_t RESERVED2[3];
bogdanm 13:0645d8841f51 545 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
bogdanm 13:0645d8841f51 546 __I uint32_t RESERVED3;
bogdanm 13:0645d8841f51 547 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
bogdanm 13:0645d8841f51 548 __I uint32_t RESERVED4[9];
bogdanm 13:0645d8841f51 549 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
bogdanm 13:0645d8841f51 550 __I uint32_t RESERVED5;
bogdanm 13:0645d8841f51 551 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
bogdanm 13:0645d8841f51 552 __I uint32_t RESERVED6;
bogdanm 13:0645d8841f51 553 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
bogdanm 13:0645d8841f51 554 __I uint32_t RESERVED7[4];
bogdanm 13:0645d8841f51 555 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
bogdanm 13:0645d8841f51 556 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
bogdanm 13:0645d8841f51 557 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
bogdanm 13:0645d8841f51 558 __I uint32_t RESERVED8[3];
bogdanm 13:0645d8841f51 559 __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
bogdanm 13:0645d8841f51 560 __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
bogdanm 13:0645d8841f51 561 __I uint32_t RESERVED9[3];
bogdanm 13:0645d8841f51 562 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
bogdanm 13:0645d8841f51 563 __I uint32_t RESERVED10;
bogdanm 13:0645d8841f51 564 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
bogdanm 13:0645d8841f51 565 __I uint32_t RESERVED11[5];
bogdanm 13:0645d8841f51 566 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
bogdanm 13:0645d8841f51 567 __I uint32_t RESERVED12;
bogdanm 13:0645d8841f51 568 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
bogdanm 13:0645d8841f51 569 __I uint32_t RESERVED13[5];
bogdanm 13:0645d8841f51 570 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
bogdanm 13:0645d8841f51 571 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
bogdanm 13:0645d8841f51 572 __I uint32_t RESERVED14[18];
bogdanm 13:0645d8841f51 573 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
bogdanm 13:0645d8841f51 574 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
bogdanm 13:0645d8841f51 575 __I uint32_t RESERVED15[6];
bogdanm 13:0645d8841f51 576 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
bogdanm 13:0645d8841f51 577 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
bogdanm 13:0645d8841f51 578 __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
bogdanm 13:0645d8841f51 579 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
bogdanm 13:0645d8841f51 580 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
bogdanm 13:0645d8841f51 581 __I uint32_t RESERVED16[25];
bogdanm 13:0645d8841f51 582 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
bogdanm 13:0645d8841f51 583 __I uint32_t RESERVED17[3];
bogdanm 13:0645d8841f51 584 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
bogdanm 13:0645d8841f51 585 __I uint32_t RESERVED18[6];
bogdanm 13:0645d8841f51 586 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
bogdanm 13:0645d8841f51 587 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
bogdanm 13:0645d8841f51 588 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
bogdanm 13:0645d8841f51 589 __I uint32_t RESERVED19[111];
bogdanm 13:0645d8841f51 590 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
bogdanm 13:0645d8841f51 591 } LPC_SYSCON_Type;
bogdanm 13:0645d8841f51 592
bogdanm 13:0645d8841f51 593
bogdanm 13:0645d8841f51 594 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 595 // ----- GPIO_PIN_INT -----
bogdanm 13:0645d8841f51 596 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 597 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
bogdanm 13:0645d8841f51 598 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
bogdanm 13:0645d8841f51 599 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
bogdanm 13:0645d8841f51 600 __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
bogdanm 13:0645d8841f51 601 __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
bogdanm 13:0645d8841f51 602 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 13:0645d8841f51 603 __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 13:0645d8841f51 604 __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
bogdanm 13:0645d8841f51 605 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
bogdanm 13:0645d8841f51 606 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
bogdanm 13:0645d8841f51 607 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
bogdanm 13:0645d8841f51 608 } LPC_GPIO_PIN_INT_Type;
bogdanm 13:0645d8841f51 609
bogdanm 13:0645d8841f51 610
bogdanm 13:0645d8841f51 611 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 612 // ----- GPIO_GROUP_INT0 -----
bogdanm 13:0645d8841f51 613 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 614 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
bogdanm 13:0645d8841f51 615 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
bogdanm 13:0645d8841f51 616 __I uint32_t RESERVED0[7];
bogdanm 13:0645d8841f51 617 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
bogdanm 13:0645d8841f51 618 __I uint32_t RESERVED1[6];
bogdanm 13:0645d8841f51 619 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
bogdanm 13:0645d8841f51 620 } LPC_GPIO_GROUP_INT0_Type;
bogdanm 13:0645d8841f51 621
bogdanm 13:0645d8841f51 622
bogdanm 13:0645d8841f51 623 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 624 // ----- GPIO_GROUP_INT1 -----
bogdanm 13:0645d8841f51 625 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 626
bogdanm 13:0645d8841f51 627 typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
bogdanm 13:0645d8841f51 628 __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
bogdanm 13:0645d8841f51 629 __I uint32_t RESERVED0[7];
bogdanm 13:0645d8841f51 630 __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
bogdanm 13:0645d8841f51 631 __I uint32_t RESERVED1[6];
bogdanm 13:0645d8841f51 632 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
bogdanm 13:0645d8841f51 633 } LPC_GPIO_GROUP_INT1_Type;
bogdanm 13:0645d8841f51 634
bogdanm 13:0645d8841f51 635
bogdanm 13:0645d8841f51 636 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 637 // ----- Repetitive Interrupt Timer (RIT) -----
bogdanm 13:0645d8841f51 638 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 639
bogdanm 13:0645d8841f51 640 typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
bogdanm 13:0645d8841f51 641 __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
bogdanm 13:0645d8841f51 642 __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
bogdanm 13:0645d8841f51 643 __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
bogdanm 13:0645d8841f51 644 __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
bogdanm 13:0645d8841f51 645 __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
bogdanm 13:0645d8841f51 646 __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
bogdanm 13:0645d8841f51 647 __I uint32_t RESERVED0[1];
bogdanm 13:0645d8841f51 648 __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
bogdanm 13:0645d8841f51 649 } LPC_RITIMER_Type;
bogdanm 13:0645d8841f51 650
bogdanm 13:0645d8841f51 651
bogdanm 13:0645d8841f51 652 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 653 // ----- USB -----
bogdanm 13:0645d8841f51 654 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 655 typedef struct { /*!< (@ 0x40020000) USB Structure */
bogdanm 13:0645d8841f51 656 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
bogdanm 13:0645d8841f51 657 __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
bogdanm 13:0645d8841f51 658 __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
bogdanm 13:0645d8841f51 659 __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
bogdanm 13:0645d8841f51 660 __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
bogdanm 13:0645d8841f51 661 __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
bogdanm 13:0645d8841f51 662 __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
bogdanm 13:0645d8841f51 663 __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
bogdanm 13:0645d8841f51 664 __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
bogdanm 13:0645d8841f51 665 __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
bogdanm 13:0645d8841f51 666 __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
bogdanm 13:0645d8841f51 667 __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
bogdanm 13:0645d8841f51 668 __I uint32_t RESERVED0[1];
bogdanm 13:0645d8841f51 669 __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
bogdanm 13:0645d8841f51 670 } LPC_USB_Type;
bogdanm 13:0645d8841f51 671
bogdanm 13:0645d8841f51 672
bogdanm 13:0645d8841f51 673 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 674 // ----- GPIO_PORT -----
bogdanm 13:0645d8841f51 675 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 676
bogdanm 13:0645d8841f51 677 typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
bogdanm 13:0645d8841f51 678 union {
bogdanm 13:0645d8841f51 679 struct {
bogdanm 13:0645d8841f51 680 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
bogdanm 13:0645d8841f51 681 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
bogdanm 13:0645d8841f51 682 };
bogdanm 13:0645d8841f51 683 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
bogdanm 13:0645d8841f51 684 };
bogdanm 13:0645d8841f51 685 __I uint32_t RESERVED0[1008];
bogdanm 13:0645d8841f51 686 union {
bogdanm 13:0645d8841f51 687 struct {
bogdanm 13:0645d8841f51 688 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
bogdanm 13:0645d8841f51 689 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
bogdanm 13:0645d8841f51 690 };
bogdanm 13:0645d8841f51 691 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
bogdanm 13:0645d8841f51 692 };
bogdanm 13:0645d8841f51 693 __I uint32_t RESERVED1[960];
bogdanm 13:0645d8841f51 694 __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
bogdanm 13:0645d8841f51 695 __I uint32_t RESERVED2[30];
bogdanm 13:0645d8841f51 696 __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
bogdanm 13:0645d8841f51 697 __I uint32_t RESERVED3[30];
bogdanm 13:0645d8841f51 698 __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
bogdanm 13:0645d8841f51 699 __I uint32_t RESERVED4[30];
bogdanm 13:0645d8841f51 700 __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
bogdanm 13:0645d8841f51 701 __I uint32_t RESERVED5[30];
bogdanm 13:0645d8841f51 702 __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
bogdanm 13:0645d8841f51 703 __I uint32_t RESERVED6[30];
bogdanm 13:0645d8841f51 704 __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
bogdanm 13:0645d8841f51 705 __I uint32_t RESERVED7[30];
bogdanm 13:0645d8841f51 706 __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
bogdanm 13:0645d8841f51 707 } LPC_GPIO_Type;
bogdanm 13:0645d8841f51 708
bogdanm 13:0645d8841f51 709
bogdanm 13:0645d8841f51 710 #if defined ( __CC_ARM )
bogdanm 13:0645d8841f51 711 #pragma no_anon_unions
bogdanm 13:0645d8841f51 712 #endif
bogdanm 13:0645d8841f51 713
bogdanm 13:0645d8841f51 714
bogdanm 13:0645d8841f51 715 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 716 // ----- Peripheral memory map -----
bogdanm 13:0645d8841f51 717 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 718
bogdanm 13:0645d8841f51 719 #define LPC_I2C_BASE (0x40000000)
bogdanm 13:0645d8841f51 720 #define LPC_WWDT_BASE (0x40004000)
bogdanm 13:0645d8841f51 721 #define LPC_USART_BASE (0x40008000)
bogdanm 13:0645d8841f51 722 #define LPC_CT16B0_BASE (0x4000C000)
bogdanm 13:0645d8841f51 723 #define LPC_CT16B1_BASE (0x40010000)
bogdanm 13:0645d8841f51 724 #define LPC_CT32B0_BASE (0x40014000)
bogdanm 13:0645d8841f51 725 #define LPC_CT32B1_BASE (0x40018000)
bogdanm 13:0645d8841f51 726 #define LPC_ADC_BASE (0x4001C000)
bogdanm 13:0645d8841f51 727 #define LPC_PMU_BASE (0x40038000)
bogdanm 13:0645d8841f51 728 #define LPC_FLASHCTRL_BASE (0x4003C000)
bogdanm 13:0645d8841f51 729 #define LPC_SSP0_BASE (0x40040000)
bogdanm 13:0645d8841f51 730 #define LPC_IOCON_BASE (0x40044000)
bogdanm 13:0645d8841f51 731 #define LPC_SYSCON_BASE (0x40048000)
bogdanm 13:0645d8841f51 732 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
bogdanm 13:0645d8841f51 733 #define LPC_SSP1_BASE (0x40058000)
bogdanm 13:0645d8841f51 734 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
bogdanm 13:0645d8841f51 735 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
bogdanm 13:0645d8841f51 736 #define LPC_RITIMER_BASE (0x40064000)
bogdanm 13:0645d8841f51 737 #define LPC_USB_BASE (0x40080000)
bogdanm 13:0645d8841f51 738 #define LPC_GPIO_BASE (0x50000000)
bogdanm 13:0645d8841f51 739
bogdanm 13:0645d8841f51 740
bogdanm 13:0645d8841f51 741 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 742 // ----- Peripheral declaration -----
bogdanm 13:0645d8841f51 743 // ------------------------------------------------------------------------------------------------
bogdanm 13:0645d8841f51 744
bogdanm 13:0645d8841f51 745 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
bogdanm 13:0645d8841f51 746 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
bogdanm 13:0645d8841f51 747 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
bogdanm 13:0645d8841f51 748 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
bogdanm 13:0645d8841f51 749 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
bogdanm 13:0645d8841f51 750 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
bogdanm 13:0645d8841f51 751 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
bogdanm 13:0645d8841f51 752 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
bogdanm 13:0645d8841f51 753 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
bogdanm 13:0645d8841f51 754 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
bogdanm 13:0645d8841f51 755 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
bogdanm 13:0645d8841f51 756 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
bogdanm 13:0645d8841f51 757 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
bogdanm 13:0645d8841f51 758 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
bogdanm 13:0645d8841f51 759 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
bogdanm 13:0645d8841f51 760 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
bogdanm 13:0645d8841f51 761 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
bogdanm 13:0645d8841f51 762 #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
bogdanm 13:0645d8841f51 763 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
bogdanm 13:0645d8841f51 764 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
bogdanm 13:0645d8841f51 765
bogdanm 13:0645d8841f51 766
bogdanm 13:0645d8841f51 767 /** @} */ /* End of group Device_Peripheral_Registers */
bogdanm 13:0645d8841f51 768 /** @} */ /* End of group (null) */
bogdanm 13:0645d8841f51 769 /** @} */ /* End of group h1usf */
bogdanm 13:0645d8841f51 770
bogdanm 13:0645d8841f51 771 #ifdef __cplusplus
bogdanm 13:0645d8841f51 772 }
bogdanm 13:0645d8841f51 773 #endif
bogdanm 13:0645d8841f51 774
bogdanm 13:0645d8841f51 775
bogdanm 13:0645d8841f51 776 #endif // __LPC13UXX_H__