Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

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TARGET_ARCH_MAX/stm32f4xx_hal_i2c.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Parent:
89:552587b429a1 
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_i2c.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 89:552587b429a1 7 * @brief Header file of I2C HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_I2C_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_I2C_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup I2C
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 58
bogdanm 89:552587b429a1 59 /**
bogdanm 89:552587b429a1 60 * @brief I2C Configuration Structure definition
bogdanm 89:552587b429a1 61 */
bogdanm 89:552587b429a1 62 typedef struct
bogdanm 89:552587b429a1 63 {
bogdanm 89:552587b429a1 64 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
bogdanm 89:552587b429a1 65 This parameter must be set to a value lower than 400kHz */
bogdanm 89:552587b429a1 66
bogdanm 89:552587b429a1 67 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
bogdanm 89:552587b429a1 68 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
bogdanm 89:552587b429a1 69
bogdanm 89:552587b429a1 70 uint32_t OwnAddress1; /*!< Specifies the first device own address.
bogdanm 89:552587b429a1 71 This parameter can be a 7-bit or 10-bit address. */
bogdanm 89:552587b429a1 72
bogdanm 89:552587b429a1 73 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
bogdanm 89:552587b429a1 74 This parameter can be a value of @ref I2C_addressing_mode */
bogdanm 89:552587b429a1 75
bogdanm 89:552587b429a1 76 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
bogdanm 89:552587b429a1 77 This parameter can be a value of @ref I2C_dual_addressing_mode */
bogdanm 89:552587b429a1 78
bogdanm 89:552587b429a1 79 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
bogdanm 89:552587b429a1 80 This parameter can be a 7-bit address. */
bogdanm 89:552587b429a1 81
bogdanm 89:552587b429a1 82 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
bogdanm 89:552587b429a1 83 This parameter can be a value of @ref I2C_general_call_addressing_mode */
bogdanm 89:552587b429a1 84
bogdanm 89:552587b429a1 85 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
bogdanm 89:552587b429a1 86 This parameter can be a value of @ref I2C_nostretch_mode */
bogdanm 89:552587b429a1 87
bogdanm 89:552587b429a1 88 }I2C_InitTypeDef;
bogdanm 89:552587b429a1 89
bogdanm 89:552587b429a1 90 /**
bogdanm 89:552587b429a1 91 * @brief HAL State structures definition
bogdanm 89:552587b429a1 92 */
bogdanm 89:552587b429a1 93 typedef enum
bogdanm 89:552587b429a1 94 {
bogdanm 89:552587b429a1 95 HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
bogdanm 89:552587b429a1 96 HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
bogdanm 89:552587b429a1 97 HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
bogdanm 89:552587b429a1 98 HAL_I2C_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 89:552587b429a1 99 HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 89:552587b429a1 100 HAL_I2C_STATE_MEM_BUSY_TX = 0x32, /*!< Memory Data Transmission process is ongoing */
bogdanm 89:552587b429a1 101 HAL_I2C_STATE_MEM_BUSY_RX = 0x42, /*!< Memory Data Reception process is ongoing */
bogdanm 89:552587b429a1 102 HAL_I2C_STATE_TIMEOUT = 0x03, /*!< I2C timeout state */
bogdanm 89:552587b429a1 103 HAL_I2C_STATE_ERROR = 0x04 /*!< I2C error state */
bogdanm 89:552587b429a1 104
bogdanm 89:552587b429a1 105 }HAL_I2C_StateTypeDef;
bogdanm 89:552587b429a1 106
bogdanm 89:552587b429a1 107 /**
bogdanm 89:552587b429a1 108 * @brief HAL I2C Error Code structure definition
bogdanm 89:552587b429a1 109 */
bogdanm 89:552587b429a1 110 typedef enum
bogdanm 89:552587b429a1 111 {
bogdanm 89:552587b429a1 112 HAL_I2C_ERROR_NONE = 0x00, /*!< No error */
bogdanm 89:552587b429a1 113 HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */
bogdanm 89:552587b429a1 114 HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */
bogdanm 89:552587b429a1 115 HAL_I2C_ERROR_AF = 0x04, /*!< AF error */
bogdanm 89:552587b429a1 116 HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */
bogdanm 89:552587b429a1 117 HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */
bogdanm 89:552587b429a1 118 HAL_I2C_ERROR_TIMEOUT = 0x20 /*!< Timeout error */
bogdanm 89:552587b429a1 119
bogdanm 89:552587b429a1 120 }HAL_I2C_ErrorTypeDef;
bogdanm 89:552587b429a1 121
bogdanm 89:552587b429a1 122 /**
bogdanm 89:552587b429a1 123 * @brief I2C handle Structure definition
bogdanm 89:552587b429a1 124 */
bogdanm 89:552587b429a1 125 typedef struct
bogdanm 89:552587b429a1 126 {
bogdanm 89:552587b429a1 127 I2C_TypeDef *Instance; /*!< I2C registers base address */
bogdanm 89:552587b429a1 128
bogdanm 89:552587b429a1 129 I2C_InitTypeDef Init; /*!< I2C communication parameters */
bogdanm 89:552587b429a1 130
bogdanm 89:552587b429a1 131 uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
bogdanm 89:552587b429a1 132
bogdanm 89:552587b429a1 133 uint16_t XferSize; /*!< I2C transfer size */
bogdanm 89:552587b429a1 134
bogdanm 89:552587b429a1 135 __IO uint16_t XferCount; /*!< I2C transfer counter */
bogdanm 89:552587b429a1 136
bogdanm 89:552587b429a1 137 DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
bogdanm 89:552587b429a1 138
bogdanm 89:552587b429a1 139 DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
bogdanm 89:552587b429a1 140
bogdanm 89:552587b429a1 141 HAL_LockTypeDef Lock; /*!< I2C locking object */
bogdanm 89:552587b429a1 142
bogdanm 89:552587b429a1 143 __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
bogdanm 89:552587b429a1 144
bogdanm 89:552587b429a1 145 __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */
bogdanm 89:552587b429a1 146
bogdanm 89:552587b429a1 147 }I2C_HandleTypeDef;
bogdanm 89:552587b429a1 148
bogdanm 89:552587b429a1 149 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 150
bogdanm 89:552587b429a1 151 /** @defgroup I2C_Exported_Constants
bogdanm 89:552587b429a1 152 * @{
bogdanm 89:552587b429a1 153 */
bogdanm 89:552587b429a1 154
bogdanm 89:552587b429a1 155 /** @defgroup I2C_duty_cycle_in_fast_mode
bogdanm 89:552587b429a1 156 * @{
bogdanm 89:552587b429a1 157 */
bogdanm 89:552587b429a1 158 #define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 159 #define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
bogdanm 89:552587b429a1 160
bogdanm 89:552587b429a1 161 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
bogdanm 89:552587b429a1 162 ((CYCLE) == I2C_DUTYCYCLE_16_9))
bogdanm 89:552587b429a1 163 /**
bogdanm 89:552587b429a1 164 * @}
bogdanm 89:552587b429a1 165 */
bogdanm 89:552587b429a1 166
bogdanm 89:552587b429a1 167 /** @defgroup I2C_addressing_mode
bogdanm 89:552587b429a1 168 * @{
bogdanm 89:552587b429a1 169 */
bogdanm 89:552587b429a1 170 #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000)
bogdanm 89:552587b429a1 171 #define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
bogdanm 89:552587b429a1 172
bogdanm 89:552587b429a1 173 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
bogdanm 89:552587b429a1 174 ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
bogdanm 89:552587b429a1 175 /**
bogdanm 89:552587b429a1 176 * @}
bogdanm 89:552587b429a1 177 */
bogdanm 89:552587b429a1 178
bogdanm 89:552587b429a1 179 /** @defgroup I2C_dual_addressing_mode
bogdanm 89:552587b429a1 180 * @{
bogdanm 89:552587b429a1 181 */
bogdanm 89:552587b429a1 182 #define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 183 #define I2C_DUALADDRESS_ENABLED I2C_OAR2_ENDUAL
bogdanm 89:552587b429a1 184
bogdanm 89:552587b429a1 185 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
bogdanm 89:552587b429a1 186 ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
bogdanm 89:552587b429a1 187 /**
bogdanm 89:552587b429a1 188 * @}
bogdanm 89:552587b429a1 189 */
bogdanm 89:552587b429a1 190
bogdanm 89:552587b429a1 191 /** @defgroup I2C_general_call_addressing_mode
bogdanm 89:552587b429a1 192 * @{
bogdanm 89:552587b429a1 193 */
bogdanm 89:552587b429a1 194 #define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 195 #define I2C_GENERALCALL_ENABLED I2C_CR1_ENGC
bogdanm 89:552587b429a1 196
bogdanm 89:552587b429a1 197 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
bogdanm 89:552587b429a1 198 ((CALL) == I2C_GENERALCALL_ENABLED))
bogdanm 89:552587b429a1 199 /**
bogdanm 89:552587b429a1 200 * @}
bogdanm 89:552587b429a1 201 */
bogdanm 89:552587b429a1 202
bogdanm 89:552587b429a1 203 /** @defgroup I2C_nostretch_mode
bogdanm 89:552587b429a1 204 * @{
bogdanm 89:552587b429a1 205 */
bogdanm 89:552587b429a1 206 #define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 207 #define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH
bogdanm 89:552587b429a1 208
bogdanm 89:552587b429a1 209 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
bogdanm 89:552587b429a1 210 ((STRETCH) == I2C_NOSTRETCH_ENABLED))
bogdanm 89:552587b429a1 211 /**
bogdanm 89:552587b429a1 212 * @}
bogdanm 89:552587b429a1 213 */
bogdanm 89:552587b429a1 214
bogdanm 89:552587b429a1 215 /** @defgroup I2C_Memory_Address_Size
bogdanm 89:552587b429a1 216 * @{
bogdanm 89:552587b429a1 217 */
bogdanm 89:552587b429a1 218 #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 219 #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 220
bogdanm 89:552587b429a1 221 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
bogdanm 89:552587b429a1 222 ((SIZE) == I2C_MEMADD_SIZE_16BIT))
bogdanm 89:552587b429a1 223 /**
bogdanm 89:552587b429a1 224 * @}
bogdanm 89:552587b429a1 225 */
bogdanm 89:552587b429a1 226
bogdanm 89:552587b429a1 227 /** @defgroup I2C_Interrupt_configuration_definition
bogdanm 89:552587b429a1 228 * @{
bogdanm 89:552587b429a1 229 */
bogdanm 89:552587b429a1 230 #define I2C_IT_BUF I2C_CR2_ITBUFEN
bogdanm 89:552587b429a1 231 #define I2C_IT_EVT I2C_CR2_ITEVTEN
bogdanm 89:552587b429a1 232 #define I2C_IT_ERR I2C_CR2_ITERREN
bogdanm 89:552587b429a1 233 /**
bogdanm 89:552587b429a1 234 * @}
bogdanm 89:552587b429a1 235 */
bogdanm 89:552587b429a1 236
bogdanm 89:552587b429a1 237 /** @defgroup I2C_Flag_definition
bogdanm 89:552587b429a1 238 * @{
bogdanm 89:552587b429a1 239 */
bogdanm 89:552587b429a1 240 #define I2C_FLAG_SMBALERT ((uint32_t)0x00018000)
bogdanm 89:552587b429a1 241 #define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000)
bogdanm 89:552587b429a1 242 #define I2C_FLAG_PECERR ((uint32_t)0x00011000)
bogdanm 89:552587b429a1 243 #define I2C_FLAG_OVR ((uint32_t)0x00010800)
bogdanm 89:552587b429a1 244 #define I2C_FLAG_AF ((uint32_t)0x00010400)
bogdanm 89:552587b429a1 245 #define I2C_FLAG_ARLO ((uint32_t)0x00010200)
bogdanm 89:552587b429a1 246 #define I2C_FLAG_BERR ((uint32_t)0x00010100)
bogdanm 89:552587b429a1 247 #define I2C_FLAG_TXE ((uint32_t)0x00010080)
bogdanm 89:552587b429a1 248 #define I2C_FLAG_RXNE ((uint32_t)0x00010040)
bogdanm 89:552587b429a1 249 #define I2C_FLAG_STOPF ((uint32_t)0x00010010)
bogdanm 89:552587b429a1 250 #define I2C_FLAG_ADD10 ((uint32_t)0x00010008)
bogdanm 89:552587b429a1 251 #define I2C_FLAG_BTF ((uint32_t)0x00010004)
bogdanm 89:552587b429a1 252 #define I2C_FLAG_ADDR ((uint32_t)0x00010002)
bogdanm 89:552587b429a1 253 #define I2C_FLAG_SB ((uint32_t)0x00010001)
bogdanm 89:552587b429a1 254 #define I2C_FLAG_DUALF ((uint32_t)0x00100080)
bogdanm 89:552587b429a1 255 #define I2C_FLAG_SMBHOST ((uint32_t)0x00100040)
bogdanm 89:552587b429a1 256 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020)
bogdanm 89:552587b429a1 257 #define I2C_FLAG_GENCALL ((uint32_t)0x00100010)
bogdanm 89:552587b429a1 258 #define I2C_FLAG_TRA ((uint32_t)0x00100004)
bogdanm 89:552587b429a1 259 #define I2C_FLAG_BUSY ((uint32_t)0x00100002)
bogdanm 89:552587b429a1 260 #define I2C_FLAG_MSL ((uint32_t)0x00100001)
bogdanm 89:552587b429a1 261 /**
bogdanm 89:552587b429a1 262 * @}
bogdanm 89:552587b429a1 263 */
bogdanm 89:552587b429a1 264
bogdanm 89:552587b429a1 265 /**
bogdanm 89:552587b429a1 266 * @}
bogdanm 89:552587b429a1 267 */
bogdanm 89:552587b429a1 268
bogdanm 89:552587b429a1 269 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 270
bogdanm 89:552587b429a1 271 /** @brief Reset I2C handle state
bogdanm 89:552587b429a1 272 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 89:552587b429a1 273 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 89:552587b429a1 274 * @retval None
bogdanm 89:552587b429a1 275 */
bogdanm 89:552587b429a1 276 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
bogdanm 89:552587b429a1 277
bogdanm 89:552587b429a1 278 /** @brief Enable or disable the specified I2C interrupts.
bogdanm 89:552587b429a1 279 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 89:552587b429a1 280 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 89:552587b429a1 281 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 89:552587b429a1 282 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 283 * @arg I2C_IT_BUF: Buffer interrupt enable
bogdanm 89:552587b429a1 284 * @arg I2C_IT_EVT: Event interrupt enable
bogdanm 89:552587b429a1 285 * @arg I2C_IT_ERR: Error interrupt enable
bogdanm 89:552587b429a1 286 * @retval None
bogdanm 89:552587b429a1 287 */
bogdanm 89:552587b429a1 288
bogdanm 89:552587b429a1 289 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 89:552587b429a1 290 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
bogdanm 89:552587b429a1 291
bogdanm 89:552587b429a1 292 /** @brief Checks if the specified I2C interrupt source is enabled or disabled.
bogdanm 89:552587b429a1 293 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 89:552587b429a1 294 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 89:552587b429a1 295 * @param __INTERRUPT__: specifies the I2C interrupt source to check.
bogdanm 89:552587b429a1 296 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 297 * @arg I2C_IT_BUF: Buffer interrupt enable
bogdanm 89:552587b429a1 298 * @arg I2C_IT_EVT: Event interrupt enable
bogdanm 89:552587b429a1 299 * @arg I2C_IT_ERR: Error interrupt enable
bogdanm 89:552587b429a1 300 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 89:552587b429a1 301 */
bogdanm 89:552587b429a1 302 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 89:552587b429a1 303
bogdanm 89:552587b429a1 304 /** @brief Checks whether the specified I2C flag is set or not.
bogdanm 89:552587b429a1 305 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 89:552587b429a1 306 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 89:552587b429a1 307 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 308 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 309 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
bogdanm 89:552587b429a1 310 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
bogdanm 89:552587b429a1 311 * @arg I2C_FLAG_PECERR: PEC error in reception flag
bogdanm 89:552587b429a1 312 * @arg I2C_FLAG_OVR: Overrun/Underrun flag
bogdanm 89:552587b429a1 313 * @arg I2C_FLAG_AF: Acknowledge failure flag
bogdanm 89:552587b429a1 314 * @arg I2C_FLAG_ARLO: Arbitration lost flag
bogdanm 89:552587b429a1 315 * @arg I2C_FLAG_BERR: Bus error flag
bogdanm 89:552587b429a1 316 * @arg I2C_FLAG_TXE: Data register empty flag
bogdanm 89:552587b429a1 317 * @arg I2C_FLAG_RXNE: Data register not empty flag
bogdanm 89:552587b429a1 318 * @arg I2C_FLAG_STOPF: Stop detection flag
bogdanm 89:552587b429a1 319 * @arg I2C_FLAG_ADD10: 10-bit header sent flag
bogdanm 89:552587b429a1 320 * @arg I2C_FLAG_BTF: Byte transfer finished flag
bogdanm 89:552587b429a1 321 * @arg I2C_FLAG_ADDR: Address sent flag
bogdanm 89:552587b429a1 322 * Address matched flag
bogdanm 89:552587b429a1 323 * @arg I2C_FLAG_SB: Start bit flag
bogdanm 89:552587b429a1 324 * @arg I2C_FLAG_DUALF: Dual flag
bogdanm 89:552587b429a1 325 * @arg I2C_FLAG_SMBHOST: SMBus host header
bogdanm 89:552587b429a1 326 * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
bogdanm 89:552587b429a1 327 * @arg I2C_FLAG_GENCALL: General call header flag
bogdanm 89:552587b429a1 328 * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
bogdanm 89:552587b429a1 329 * @arg I2C_FLAG_BUSY: Bus busy flag
bogdanm 89:552587b429a1 330 * @arg I2C_FLAG_MSL: Master/Slave flag
bogdanm 89:552587b429a1 331 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 89:552587b429a1 332 */
bogdanm 89:552587b429a1 333 #define I2C_FLAG_MASK ((uint32_t)0x0000FFFF)
bogdanm 89:552587b429a1 334 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
bogdanm 89:552587b429a1 335 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
bogdanm 89:552587b429a1 336
bogdanm 89:552587b429a1 337 /** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
bogdanm 89:552587b429a1 338 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 89:552587b429a1 339 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 89:552587b429a1 340 * @param __FLAG__: specifies the flag to clear.
bogdanm 89:552587b429a1 341 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 342 * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
bogdanm 89:552587b429a1 343 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
bogdanm 89:552587b429a1 344 * @arg I2C_FLAG_PECERR: PEC error in reception flag
bogdanm 89:552587b429a1 345 * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
bogdanm 89:552587b429a1 346 * @arg I2C_FLAG_AF: Acknowledge failure flag
bogdanm 89:552587b429a1 347 * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
bogdanm 89:552587b429a1 348 * @arg I2C_FLAG_BERR: Bus error flag
bogdanm 89:552587b429a1 349 * @retval None
bogdanm 89:552587b429a1 350 */
bogdanm 92:4fc01daae5a5 351 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
bogdanm 89:552587b429a1 352
bogdanm 89:552587b429a1 353 /** @brief Clears the I2C ADDR pending flag.
bogdanm 89:552587b429a1 354 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 89:552587b429a1 355 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 89:552587b429a1 356 * @retval None
bogdanm 89:552587b429a1 357 */
bogdanm 89:552587b429a1 358
bogdanm 89:552587b429a1 359 #define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
bogdanm 89:552587b429a1 360 (__HANDLE__)->Instance->SR2;}while(0)
bogdanm 89:552587b429a1 361
bogdanm 89:552587b429a1 362 /** @brief Clears the I2C STOPF pending flag.
bogdanm 89:552587b429a1 363 * @param __HANDLE__: specifies the I2C Handle.
bogdanm 89:552587b429a1 364 * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
bogdanm 89:552587b429a1 365 * @retval None
bogdanm 89:552587b429a1 366 */
bogdanm 89:552587b429a1 367 #define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
bogdanm 89:552587b429a1 368 (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE;}while(0)
bogdanm 89:552587b429a1 369
bogdanm 89:552587b429a1 370 #define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
bogdanm 89:552587b429a1 371 #define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
bogdanm 89:552587b429a1 372
bogdanm 89:552587b429a1 373 #define __HAL_I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000)
bogdanm 89:552587b429a1 374 #define __HAL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
bogdanm 89:552587b429a1 375 #define __HAL_I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
bogdanm 89:552587b429a1 376 #define __HAL_I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
bogdanm 89:552587b429a1 377 #define __HAL_I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (__HAL_I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
bogdanm 89:552587b429a1 378 ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
bogdanm 89:552587b429a1 379 ((__HAL_I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
bogdanm 89:552587b429a1 380
bogdanm 89:552587b429a1 381 #define __HAL_I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
bogdanm 89:552587b429a1 382 #define __HAL_I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
bogdanm 89:552587b429a1 383
bogdanm 89:552587b429a1 384 #define __HAL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
bogdanm 89:552587b429a1 385 #define __HAL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
bogdanm 89:552587b429a1 386 #define __HAL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
bogdanm 89:552587b429a1 387
bogdanm 89:552587b429a1 388 #define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
bogdanm 89:552587b429a1 389 #define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
bogdanm 89:552587b429a1 390
bogdanm 89:552587b429a1 391 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
bogdanm 89:552587b429a1 392 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
bogdanm 89:552587b429a1 393 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
bogdanm 89:552587b429a1 394
bogdanm 89:552587b429a1 395 /* Include I2C HAL Extension module */
bogdanm 89:552587b429a1 396 #include "stm32f4xx_hal_i2c_ex.h"
bogdanm 89:552587b429a1 397
bogdanm 89:552587b429a1 398 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 399 /* Initialization/de-initialization functions **********************************/
bogdanm 89:552587b429a1 400 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 401 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 402 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 403 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 404
bogdanm 89:552587b429a1 405 /* I/O operation functions *****************************************************/
bogdanm 89:552587b429a1 406 /******* Blocking mode: Polling */
bogdanm 89:552587b429a1 407 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 408 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 409 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 410 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 411 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 412 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 413 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
bogdanm 89:552587b429a1 414
bogdanm 89:552587b429a1 415 /******* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 416 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 417 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 418 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 419 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 420 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 421 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 422
bogdanm 89:552587b429a1 423 /******* Non-Blocking mode: DMA */
bogdanm 89:552587b429a1 424 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 425 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 426 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 427 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 428 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 429 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 430
bogdanm 89:552587b429a1 431 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
bogdanm 89:552587b429a1 432 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 433 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 434 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 435 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 436 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 437 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 438 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 439 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 440 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 441
bogdanm 89:552587b429a1 442 /* Peripheral Control and State functions **************************************/
bogdanm 89:552587b429a1 443 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 444 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
bogdanm 89:552587b429a1 445
bogdanm 89:552587b429a1 446 /**
bogdanm 89:552587b429a1 447 * @}
bogdanm 89:552587b429a1 448 */
bogdanm 89:552587b429a1 449
bogdanm 89:552587b429a1 450 /**
bogdanm 89:552587b429a1 451 * @}
bogdanm 89:552587b429a1 452 */
bogdanm 89:552587b429a1 453
bogdanm 89:552587b429a1 454 #ifdef __cplusplus
bogdanm 89:552587b429a1 455 }
bogdanm 89:552587b429a1 456 #endif
bogdanm 89:552587b429a1 457
bogdanm 89:552587b429a1 458
bogdanm 89:552587b429a1 459 #endif /* __STM32F4xx_HAL_I2C_H */
bogdanm 89:552587b429a1 460
bogdanm 89:552587b429a1 461 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/