不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_sc000.h@6:b3885567877c, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:43:07 2017 +0000
Revision:
6:b3885567877c
Parent:
4:c1beacfc42c7 
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 * @file core_sc000.h
MikamiUitOpen 4:c1beacfc42c7 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
MikamiUitOpen 4:c1beacfc42c7 4 * @version V4.10
MikamiUitOpen 4:c1beacfc42c7 5 * @date 18. March 2015
MikamiUitOpen 4:c1beacfc42c7 6 *
MikamiUitOpen 4:c1beacfc42c7 7 * @note
MikamiUitOpen 4:c1beacfc42c7 8 *
MikamiUitOpen 4:c1beacfc42c7 9 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11
MikamiUitOpen 4:c1beacfc42c7 12 All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 *
MikamiUitOpen 4:c1beacfc42c7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37
MikamiUitOpen 4:c1beacfc42c7 38 #if defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 39 #pragma system_include /* treat file as system include file for MISRA check */
MikamiUitOpen 4:c1beacfc42c7 40 #endif
MikamiUitOpen 4:c1beacfc42c7 41
MikamiUitOpen 4:c1beacfc42c7 42 #ifndef __CORE_SC000_H_GENERIC
MikamiUitOpen 4:c1beacfc42c7 43 #define __CORE_SC000_H_GENERIC
MikamiUitOpen 4:c1beacfc42c7 44
MikamiUitOpen 4:c1beacfc42c7 45 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 46 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 47 #endif
MikamiUitOpen 4:c1beacfc42c7 48
MikamiUitOpen 4:c1beacfc42c7 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MikamiUitOpen 4:c1beacfc42c7 50 CMSIS violates the following MISRA-C:2004 rules:
MikamiUitOpen 4:c1beacfc42c7 51
MikamiUitOpen 4:c1beacfc42c7 52 \li Required Rule 8.5, object/function definition in header file.<br>
MikamiUitOpen 4:c1beacfc42c7 53 Function definitions in header files are used to allow 'inlining'.
MikamiUitOpen 4:c1beacfc42c7 54
MikamiUitOpen 4:c1beacfc42c7 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MikamiUitOpen 4:c1beacfc42c7 56 Unions are used for effective representation of core registers.
MikamiUitOpen 4:c1beacfc42c7 57
MikamiUitOpen 4:c1beacfc42c7 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
MikamiUitOpen 4:c1beacfc42c7 59 Function-like macros are used to allow more efficient code.
MikamiUitOpen 4:c1beacfc42c7 60 */
MikamiUitOpen 4:c1beacfc42c7 61
MikamiUitOpen 4:c1beacfc42c7 62
MikamiUitOpen 4:c1beacfc42c7 63 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 64 * CMSIS definitions
MikamiUitOpen 4:c1beacfc42c7 65 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 66 /** \ingroup SC000
MikamiUitOpen 4:c1beacfc42c7 67 @{
MikamiUitOpen 4:c1beacfc42c7 68 */
MikamiUitOpen 4:c1beacfc42c7 69
MikamiUitOpen 4:c1beacfc42c7 70 /* CMSIS SC000 definitions */
MikamiUitOpen 4:c1beacfc42c7 71 #define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
MikamiUitOpen 4:c1beacfc42c7 72 #define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
MikamiUitOpen 4:c1beacfc42c7 73 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
MikamiUitOpen 4:c1beacfc42c7 74 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
MikamiUitOpen 4:c1beacfc42c7 75
MikamiUitOpen 4:c1beacfc42c7 76 #define __CORTEX_SC (000) /*!< Cortex secure core */
MikamiUitOpen 4:c1beacfc42c7 77
MikamiUitOpen 4:c1beacfc42c7 78
MikamiUitOpen 4:c1beacfc42c7 79 #if defined ( __CC_ARM )
MikamiUitOpen 4:c1beacfc42c7 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
MikamiUitOpen 4:c1beacfc42c7 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
MikamiUitOpen 4:c1beacfc42c7 82 #define __STATIC_INLINE static __inline
MikamiUitOpen 4:c1beacfc42c7 83
MikamiUitOpen 4:c1beacfc42c7 84 #elif defined ( __GNUC__ )
MikamiUitOpen 4:c1beacfc42c7 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
MikamiUitOpen 4:c1beacfc42c7 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
MikamiUitOpen 4:c1beacfc42c7 87 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 88
MikamiUitOpen 4:c1beacfc42c7 89 #elif defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
MikamiUitOpen 4:c1beacfc42c7 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
MikamiUitOpen 4:c1beacfc42c7 92 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 93
MikamiUitOpen 4:c1beacfc42c7 94 #elif defined ( __TMS470__ )
MikamiUitOpen 4:c1beacfc42c7 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
MikamiUitOpen 4:c1beacfc42c7 96 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 97
MikamiUitOpen 4:c1beacfc42c7 98 #elif defined ( __TASKING__ )
MikamiUitOpen 4:c1beacfc42c7 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
MikamiUitOpen 4:c1beacfc42c7 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
MikamiUitOpen 4:c1beacfc42c7 101 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 102
MikamiUitOpen 4:c1beacfc42c7 103 #elif defined ( __CSMC__ )
MikamiUitOpen 4:c1beacfc42c7 104 #define __packed
MikamiUitOpen 4:c1beacfc42c7 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
MikamiUitOpen 4:c1beacfc42c7 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
MikamiUitOpen 4:c1beacfc42c7 107 #define __STATIC_INLINE static inline
MikamiUitOpen 4:c1beacfc42c7 108
MikamiUitOpen 4:c1beacfc42c7 109 #endif
MikamiUitOpen 4:c1beacfc42c7 110
MikamiUitOpen 4:c1beacfc42c7 111 /** __FPU_USED indicates whether an FPU is used or not.
MikamiUitOpen 4:c1beacfc42c7 112 This core does not support an FPU at all
MikamiUitOpen 4:c1beacfc42c7 113 */
MikamiUitOpen 4:c1beacfc42c7 114 #define __FPU_USED 0
MikamiUitOpen 4:c1beacfc42c7 115
MikamiUitOpen 4:c1beacfc42c7 116 #if defined ( __CC_ARM )
MikamiUitOpen 4:c1beacfc42c7 117 #if defined __TARGET_FPU_VFP
MikamiUitOpen 4:c1beacfc42c7 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 119 #endif
MikamiUitOpen 4:c1beacfc42c7 120
MikamiUitOpen 4:c1beacfc42c7 121 #elif defined ( __GNUC__ )
MikamiUitOpen 4:c1beacfc42c7 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
MikamiUitOpen 4:c1beacfc42c7 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 124 #endif
MikamiUitOpen 4:c1beacfc42c7 125
MikamiUitOpen 4:c1beacfc42c7 126 #elif defined ( __ICCARM__ )
MikamiUitOpen 4:c1beacfc42c7 127 #if defined __ARMVFP__
MikamiUitOpen 4:c1beacfc42c7 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 129 #endif
MikamiUitOpen 4:c1beacfc42c7 130
MikamiUitOpen 4:c1beacfc42c7 131 #elif defined ( __TMS470__ )
MikamiUitOpen 4:c1beacfc42c7 132 #if defined __TI__VFP_SUPPORT____
MikamiUitOpen 4:c1beacfc42c7 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 134 #endif
MikamiUitOpen 4:c1beacfc42c7 135
MikamiUitOpen 4:c1beacfc42c7 136 #elif defined ( __TASKING__ )
MikamiUitOpen 4:c1beacfc42c7 137 #if defined __FPU_VFP__
MikamiUitOpen 4:c1beacfc42c7 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 139 #endif
MikamiUitOpen 4:c1beacfc42c7 140
MikamiUitOpen 4:c1beacfc42c7 141 #elif defined ( __CSMC__ ) /* Cosmic */
MikamiUitOpen 4:c1beacfc42c7 142 #if ( __CSMC__ & 0x400) // FPU present for parser
MikamiUitOpen 4:c1beacfc42c7 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MikamiUitOpen 4:c1beacfc42c7 144 #endif
MikamiUitOpen 4:c1beacfc42c7 145 #endif
MikamiUitOpen 4:c1beacfc42c7 146
MikamiUitOpen 4:c1beacfc42c7 147 #include <stdint.h> /* standard types definitions */
MikamiUitOpen 4:c1beacfc42c7 148 #include <core_cmInstr.h> /* Core Instruction Access */
MikamiUitOpen 4:c1beacfc42c7 149 #include <core_cmFunc.h> /* Core Function Access */
MikamiUitOpen 4:c1beacfc42c7 150
MikamiUitOpen 4:c1beacfc42c7 151 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 152 }
MikamiUitOpen 4:c1beacfc42c7 153 #endif
MikamiUitOpen 4:c1beacfc42c7 154
MikamiUitOpen 4:c1beacfc42c7 155 #endif /* __CORE_SC000_H_GENERIC */
MikamiUitOpen 4:c1beacfc42c7 156
MikamiUitOpen 4:c1beacfc42c7 157 #ifndef __CMSIS_GENERIC
MikamiUitOpen 4:c1beacfc42c7 158
MikamiUitOpen 4:c1beacfc42c7 159 #ifndef __CORE_SC000_H_DEPENDANT
MikamiUitOpen 4:c1beacfc42c7 160 #define __CORE_SC000_H_DEPENDANT
MikamiUitOpen 4:c1beacfc42c7 161
MikamiUitOpen 4:c1beacfc42c7 162 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 163 extern "C" {
MikamiUitOpen 4:c1beacfc42c7 164 #endif
MikamiUitOpen 4:c1beacfc42c7 165
MikamiUitOpen 4:c1beacfc42c7 166 /* check device defines and use defaults */
MikamiUitOpen 4:c1beacfc42c7 167 #if defined __CHECK_DEVICE_DEFINES
MikamiUitOpen 4:c1beacfc42c7 168 #ifndef __SC000_REV
MikamiUitOpen 4:c1beacfc42c7 169 #define __SC000_REV 0x0000
MikamiUitOpen 4:c1beacfc42c7 170 #warning "__SC000_REV not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 171 #endif
MikamiUitOpen 4:c1beacfc42c7 172
MikamiUitOpen 4:c1beacfc42c7 173 #ifndef __MPU_PRESENT
MikamiUitOpen 4:c1beacfc42c7 174 #define __MPU_PRESENT 0
MikamiUitOpen 4:c1beacfc42c7 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 176 #endif
MikamiUitOpen 4:c1beacfc42c7 177
MikamiUitOpen 4:c1beacfc42c7 178 #ifndef __NVIC_PRIO_BITS
MikamiUitOpen 4:c1beacfc42c7 179 #define __NVIC_PRIO_BITS 2
MikamiUitOpen 4:c1beacfc42c7 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 181 #endif
MikamiUitOpen 4:c1beacfc42c7 182
MikamiUitOpen 4:c1beacfc42c7 183 #ifndef __Vendor_SysTickConfig
MikamiUitOpen 4:c1beacfc42c7 184 #define __Vendor_SysTickConfig 0
MikamiUitOpen 4:c1beacfc42c7 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MikamiUitOpen 4:c1beacfc42c7 186 #endif
MikamiUitOpen 4:c1beacfc42c7 187 #endif
MikamiUitOpen 4:c1beacfc42c7 188
MikamiUitOpen 4:c1beacfc42c7 189 /* IO definitions (access restrictions to peripheral registers) */
MikamiUitOpen 4:c1beacfc42c7 190 /**
MikamiUitOpen 4:c1beacfc42c7 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
MikamiUitOpen 4:c1beacfc42c7 192
MikamiUitOpen 4:c1beacfc42c7 193 <strong>IO Type Qualifiers</strong> are used
MikamiUitOpen 4:c1beacfc42c7 194 \li to specify the access to peripheral variables.
MikamiUitOpen 4:c1beacfc42c7 195 \li for automatic generation of peripheral register debug information.
MikamiUitOpen 4:c1beacfc42c7 196 */
MikamiUitOpen 4:c1beacfc42c7 197 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 198 #define __I volatile /*!< Defines 'read only' permissions */
MikamiUitOpen 4:c1beacfc42c7 199 #else
MikamiUitOpen 4:c1beacfc42c7 200 #define __I volatile const /*!< Defines 'read only' permissions */
MikamiUitOpen 4:c1beacfc42c7 201 #endif
MikamiUitOpen 4:c1beacfc42c7 202 #define __O volatile /*!< Defines 'write only' permissions */
MikamiUitOpen 4:c1beacfc42c7 203 #define __IO volatile /*!< Defines 'read / write' permissions */
MikamiUitOpen 4:c1beacfc42c7 204
MikamiUitOpen 4:c1beacfc42c7 205 /*@} end of group SC000 */
MikamiUitOpen 4:c1beacfc42c7 206
MikamiUitOpen 4:c1beacfc42c7 207
MikamiUitOpen 4:c1beacfc42c7 208
MikamiUitOpen 4:c1beacfc42c7 209 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 210 * Register Abstraction
MikamiUitOpen 4:c1beacfc42c7 211 Core Register contain:
MikamiUitOpen 4:c1beacfc42c7 212 - Core Register
MikamiUitOpen 4:c1beacfc42c7 213 - Core NVIC Register
MikamiUitOpen 4:c1beacfc42c7 214 - Core SCB Register
MikamiUitOpen 4:c1beacfc42c7 215 - Core SysTick Register
MikamiUitOpen 4:c1beacfc42c7 216 - Core MPU Register
MikamiUitOpen 4:c1beacfc42c7 217 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 218 /** \defgroup CMSIS_core_register Defines and Type Definitions
MikamiUitOpen 4:c1beacfc42c7 219 \brief Type definitions and defines for Cortex-M processor based devices.
MikamiUitOpen 4:c1beacfc42c7 220 */
MikamiUitOpen 4:c1beacfc42c7 221
MikamiUitOpen 4:c1beacfc42c7 222 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 223 \defgroup CMSIS_CORE Status and Control Registers
MikamiUitOpen 4:c1beacfc42c7 224 \brief Core Register type definitions.
MikamiUitOpen 4:c1beacfc42c7 225 @{
MikamiUitOpen 4:c1beacfc42c7 226 */
MikamiUitOpen 4:c1beacfc42c7 227
MikamiUitOpen 4:c1beacfc42c7 228 /** \brief Union type to access the Application Program Status Register (APSR).
MikamiUitOpen 4:c1beacfc42c7 229 */
MikamiUitOpen 4:c1beacfc42c7 230 typedef union
MikamiUitOpen 4:c1beacfc42c7 231 {
MikamiUitOpen 4:c1beacfc42c7 232 struct
MikamiUitOpen 4:c1beacfc42c7 233 {
MikamiUitOpen 4:c1beacfc42c7 234 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
MikamiUitOpen 4:c1beacfc42c7 235 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 4:c1beacfc42c7 236 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 4:c1beacfc42c7 237 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 4:c1beacfc42c7 238 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 4:c1beacfc42c7 239 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 240 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 241 } APSR_Type;
MikamiUitOpen 4:c1beacfc42c7 242
MikamiUitOpen 4:c1beacfc42c7 243 /* APSR Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 244 #define APSR_N_Pos 31 /*!< APSR: N Position */
MikamiUitOpen 4:c1beacfc42c7 245 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
MikamiUitOpen 4:c1beacfc42c7 246
MikamiUitOpen 4:c1beacfc42c7 247 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
MikamiUitOpen 4:c1beacfc42c7 248 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
MikamiUitOpen 4:c1beacfc42c7 249
MikamiUitOpen 4:c1beacfc42c7 250 #define APSR_C_Pos 29 /*!< APSR: C Position */
MikamiUitOpen 4:c1beacfc42c7 251 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
MikamiUitOpen 4:c1beacfc42c7 252
MikamiUitOpen 4:c1beacfc42c7 253 #define APSR_V_Pos 28 /*!< APSR: V Position */
MikamiUitOpen 4:c1beacfc42c7 254 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
MikamiUitOpen 4:c1beacfc42c7 255
MikamiUitOpen 4:c1beacfc42c7 256
MikamiUitOpen 4:c1beacfc42c7 257 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
MikamiUitOpen 4:c1beacfc42c7 258 */
MikamiUitOpen 4:c1beacfc42c7 259 typedef union
MikamiUitOpen 4:c1beacfc42c7 260 {
MikamiUitOpen 4:c1beacfc42c7 261 struct
MikamiUitOpen 4:c1beacfc42c7 262 {
MikamiUitOpen 4:c1beacfc42c7 263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 4:c1beacfc42c7 264 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
MikamiUitOpen 4:c1beacfc42c7 265 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 266 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 267 } IPSR_Type;
MikamiUitOpen 4:c1beacfc42c7 268
MikamiUitOpen 4:c1beacfc42c7 269 /* IPSR Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 270 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
MikamiUitOpen 4:c1beacfc42c7 271 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
MikamiUitOpen 4:c1beacfc42c7 272
MikamiUitOpen 4:c1beacfc42c7 273
MikamiUitOpen 4:c1beacfc42c7 274 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MikamiUitOpen 4:c1beacfc42c7 275 */
MikamiUitOpen 4:c1beacfc42c7 276 typedef union
MikamiUitOpen 4:c1beacfc42c7 277 {
MikamiUitOpen 4:c1beacfc42c7 278 struct
MikamiUitOpen 4:c1beacfc42c7 279 {
MikamiUitOpen 4:c1beacfc42c7 280 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
MikamiUitOpen 4:c1beacfc42c7 281 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
MikamiUitOpen 4:c1beacfc42c7 282 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
MikamiUitOpen 4:c1beacfc42c7 283 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
MikamiUitOpen 4:c1beacfc42c7 284 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
MikamiUitOpen 4:c1beacfc42c7 285 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
MikamiUitOpen 4:c1beacfc42c7 286 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
MikamiUitOpen 4:c1beacfc42c7 287 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
MikamiUitOpen 4:c1beacfc42c7 288 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 289 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 290 } xPSR_Type;
MikamiUitOpen 4:c1beacfc42c7 291
MikamiUitOpen 4:c1beacfc42c7 292 /* xPSR Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 293 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
MikamiUitOpen 4:c1beacfc42c7 294 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
MikamiUitOpen 4:c1beacfc42c7 295
MikamiUitOpen 4:c1beacfc42c7 296 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
MikamiUitOpen 4:c1beacfc42c7 297 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
MikamiUitOpen 4:c1beacfc42c7 298
MikamiUitOpen 4:c1beacfc42c7 299 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
MikamiUitOpen 4:c1beacfc42c7 300 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
MikamiUitOpen 4:c1beacfc42c7 301
MikamiUitOpen 4:c1beacfc42c7 302 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
MikamiUitOpen 4:c1beacfc42c7 303 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
MikamiUitOpen 4:c1beacfc42c7 304
MikamiUitOpen 4:c1beacfc42c7 305 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
MikamiUitOpen 4:c1beacfc42c7 306 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
MikamiUitOpen 4:c1beacfc42c7 307
MikamiUitOpen 4:c1beacfc42c7 308 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
MikamiUitOpen 4:c1beacfc42c7 309 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
MikamiUitOpen 4:c1beacfc42c7 310
MikamiUitOpen 4:c1beacfc42c7 311
MikamiUitOpen 4:c1beacfc42c7 312 /** \brief Union type to access the Control Registers (CONTROL).
MikamiUitOpen 4:c1beacfc42c7 313 */
MikamiUitOpen 4:c1beacfc42c7 314 typedef union
MikamiUitOpen 4:c1beacfc42c7 315 {
MikamiUitOpen 4:c1beacfc42c7 316 struct
MikamiUitOpen 4:c1beacfc42c7 317 {
MikamiUitOpen 4:c1beacfc42c7 318 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
MikamiUitOpen 4:c1beacfc42c7 319 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
MikamiUitOpen 4:c1beacfc42c7 320 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
MikamiUitOpen 4:c1beacfc42c7 321 } b; /*!< Structure used for bit access */
MikamiUitOpen 4:c1beacfc42c7 322 uint32_t w; /*!< Type used for word access */
MikamiUitOpen 4:c1beacfc42c7 323 } CONTROL_Type;
MikamiUitOpen 4:c1beacfc42c7 324
MikamiUitOpen 4:c1beacfc42c7 325 /* CONTROL Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 326 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
MikamiUitOpen 4:c1beacfc42c7 327 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
MikamiUitOpen 4:c1beacfc42c7 328
MikamiUitOpen 4:c1beacfc42c7 329 /*@} end of group CMSIS_CORE */
MikamiUitOpen 4:c1beacfc42c7 330
MikamiUitOpen 4:c1beacfc42c7 331
MikamiUitOpen 4:c1beacfc42c7 332 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 333 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MikamiUitOpen 4:c1beacfc42c7 334 \brief Type definitions for the NVIC Registers
MikamiUitOpen 4:c1beacfc42c7 335 @{
MikamiUitOpen 4:c1beacfc42c7 336 */
MikamiUitOpen 4:c1beacfc42c7 337
MikamiUitOpen 4:c1beacfc42c7 338 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MikamiUitOpen 4:c1beacfc42c7 339 */
MikamiUitOpen 4:c1beacfc42c7 340 typedef struct
MikamiUitOpen 4:c1beacfc42c7 341 {
MikamiUitOpen 4:c1beacfc42c7 342 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
MikamiUitOpen 4:c1beacfc42c7 343 uint32_t RESERVED0[31];
MikamiUitOpen 4:c1beacfc42c7 344 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
MikamiUitOpen 4:c1beacfc42c7 345 uint32_t RSERVED1[31];
MikamiUitOpen 4:c1beacfc42c7 346 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
MikamiUitOpen 4:c1beacfc42c7 347 uint32_t RESERVED2[31];
MikamiUitOpen 4:c1beacfc42c7 348 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
MikamiUitOpen 4:c1beacfc42c7 349 uint32_t RESERVED3[31];
MikamiUitOpen 4:c1beacfc42c7 350 uint32_t RESERVED4[64];
MikamiUitOpen 4:c1beacfc42c7 351 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
MikamiUitOpen 4:c1beacfc42c7 352 } NVIC_Type;
MikamiUitOpen 4:c1beacfc42c7 353
MikamiUitOpen 4:c1beacfc42c7 354 /*@} end of group CMSIS_NVIC */
MikamiUitOpen 4:c1beacfc42c7 355
MikamiUitOpen 4:c1beacfc42c7 356
MikamiUitOpen 4:c1beacfc42c7 357 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 358 \defgroup CMSIS_SCB System Control Block (SCB)
MikamiUitOpen 4:c1beacfc42c7 359 \brief Type definitions for the System Control Block Registers
MikamiUitOpen 4:c1beacfc42c7 360 @{
MikamiUitOpen 4:c1beacfc42c7 361 */
MikamiUitOpen 4:c1beacfc42c7 362
MikamiUitOpen 4:c1beacfc42c7 363 /** \brief Structure type to access the System Control Block (SCB).
MikamiUitOpen 4:c1beacfc42c7 364 */
MikamiUitOpen 4:c1beacfc42c7 365 typedef struct
MikamiUitOpen 4:c1beacfc42c7 366 {
MikamiUitOpen 4:c1beacfc42c7 367 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
MikamiUitOpen 4:c1beacfc42c7 368 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
MikamiUitOpen 4:c1beacfc42c7 369 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
MikamiUitOpen 4:c1beacfc42c7 370 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
MikamiUitOpen 4:c1beacfc42c7 371 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
MikamiUitOpen 4:c1beacfc42c7 372 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
MikamiUitOpen 4:c1beacfc42c7 373 uint32_t RESERVED0[1];
MikamiUitOpen 4:c1beacfc42c7 374 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
MikamiUitOpen 4:c1beacfc42c7 375 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
MikamiUitOpen 4:c1beacfc42c7 376 uint32_t RESERVED1[154];
MikamiUitOpen 4:c1beacfc42c7 377 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
MikamiUitOpen 4:c1beacfc42c7 378 } SCB_Type;
MikamiUitOpen 4:c1beacfc42c7 379
MikamiUitOpen 4:c1beacfc42c7 380 /* SCB CPUID Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 381 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
MikamiUitOpen 4:c1beacfc42c7 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
MikamiUitOpen 4:c1beacfc42c7 383
MikamiUitOpen 4:c1beacfc42c7 384 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
MikamiUitOpen 4:c1beacfc42c7 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
MikamiUitOpen 4:c1beacfc42c7 386
MikamiUitOpen 4:c1beacfc42c7 387 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
MikamiUitOpen 4:c1beacfc42c7 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
MikamiUitOpen 4:c1beacfc42c7 389
MikamiUitOpen 4:c1beacfc42c7 390 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
MikamiUitOpen 4:c1beacfc42c7 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
MikamiUitOpen 4:c1beacfc42c7 392
MikamiUitOpen 4:c1beacfc42c7 393 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
MikamiUitOpen 4:c1beacfc42c7 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
MikamiUitOpen 4:c1beacfc42c7 395
MikamiUitOpen 4:c1beacfc42c7 396 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 397 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
MikamiUitOpen 4:c1beacfc42c7 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
MikamiUitOpen 4:c1beacfc42c7 399
MikamiUitOpen 4:c1beacfc42c7 400 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
MikamiUitOpen 4:c1beacfc42c7 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
MikamiUitOpen 4:c1beacfc42c7 402
MikamiUitOpen 4:c1beacfc42c7 403 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
MikamiUitOpen 4:c1beacfc42c7 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
MikamiUitOpen 4:c1beacfc42c7 405
MikamiUitOpen 4:c1beacfc42c7 406 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
MikamiUitOpen 4:c1beacfc42c7 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
MikamiUitOpen 4:c1beacfc42c7 408
MikamiUitOpen 4:c1beacfc42c7 409 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
MikamiUitOpen 4:c1beacfc42c7 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
MikamiUitOpen 4:c1beacfc42c7 411
MikamiUitOpen 4:c1beacfc42c7 412 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
MikamiUitOpen 4:c1beacfc42c7 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
MikamiUitOpen 4:c1beacfc42c7 414
MikamiUitOpen 4:c1beacfc42c7 415 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
MikamiUitOpen 4:c1beacfc42c7 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
MikamiUitOpen 4:c1beacfc42c7 417
MikamiUitOpen 4:c1beacfc42c7 418 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
MikamiUitOpen 4:c1beacfc42c7 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
MikamiUitOpen 4:c1beacfc42c7 420
MikamiUitOpen 4:c1beacfc42c7 421 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
MikamiUitOpen 4:c1beacfc42c7 422 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
MikamiUitOpen 4:c1beacfc42c7 423
MikamiUitOpen 4:c1beacfc42c7 424 /* SCB Interrupt Control State Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 425 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
MikamiUitOpen 4:c1beacfc42c7 426 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
MikamiUitOpen 4:c1beacfc42c7 427
MikamiUitOpen 4:c1beacfc42c7 428 /* SCB Application Interrupt and Reset Control Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 429 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
MikamiUitOpen 4:c1beacfc42c7 430 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
MikamiUitOpen 4:c1beacfc42c7 431
MikamiUitOpen 4:c1beacfc42c7 432 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
MikamiUitOpen 4:c1beacfc42c7 433 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
MikamiUitOpen 4:c1beacfc42c7 434
MikamiUitOpen 4:c1beacfc42c7 435 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
MikamiUitOpen 4:c1beacfc42c7 436 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
MikamiUitOpen 4:c1beacfc42c7 437
MikamiUitOpen 4:c1beacfc42c7 438 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
MikamiUitOpen 4:c1beacfc42c7 439 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
MikamiUitOpen 4:c1beacfc42c7 440
MikamiUitOpen 4:c1beacfc42c7 441 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
MikamiUitOpen 4:c1beacfc42c7 442 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
MikamiUitOpen 4:c1beacfc42c7 443
MikamiUitOpen 4:c1beacfc42c7 444 /* SCB System Control Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 445 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
MikamiUitOpen 4:c1beacfc42c7 446 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
MikamiUitOpen 4:c1beacfc42c7 447
MikamiUitOpen 4:c1beacfc42c7 448 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
MikamiUitOpen 4:c1beacfc42c7 449 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
MikamiUitOpen 4:c1beacfc42c7 450
MikamiUitOpen 4:c1beacfc42c7 451 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
MikamiUitOpen 4:c1beacfc42c7 452 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
MikamiUitOpen 4:c1beacfc42c7 453
MikamiUitOpen 4:c1beacfc42c7 454 /* SCB Configuration Control Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 455 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
MikamiUitOpen 4:c1beacfc42c7 456 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
MikamiUitOpen 4:c1beacfc42c7 457
MikamiUitOpen 4:c1beacfc42c7 458 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
MikamiUitOpen 4:c1beacfc42c7 459 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
MikamiUitOpen 4:c1beacfc42c7 460
MikamiUitOpen 4:c1beacfc42c7 461 /* SCB System Handler Control and State Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 462 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
MikamiUitOpen 4:c1beacfc42c7 463 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
MikamiUitOpen 4:c1beacfc42c7 464
MikamiUitOpen 4:c1beacfc42c7 465 /*@} end of group CMSIS_SCB */
MikamiUitOpen 4:c1beacfc42c7 466
MikamiUitOpen 4:c1beacfc42c7 467
MikamiUitOpen 4:c1beacfc42c7 468 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 469 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
MikamiUitOpen 4:c1beacfc42c7 470 \brief Type definitions for the System Control and ID Register not in the SCB
MikamiUitOpen 4:c1beacfc42c7 471 @{
MikamiUitOpen 4:c1beacfc42c7 472 */
MikamiUitOpen 4:c1beacfc42c7 473
MikamiUitOpen 4:c1beacfc42c7 474 /** \brief Structure type to access the System Control and ID Register not in the SCB.
MikamiUitOpen 4:c1beacfc42c7 475 */
MikamiUitOpen 4:c1beacfc42c7 476 typedef struct
MikamiUitOpen 4:c1beacfc42c7 477 {
MikamiUitOpen 4:c1beacfc42c7 478 uint32_t RESERVED0[2];
MikamiUitOpen 4:c1beacfc42c7 479 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
MikamiUitOpen 4:c1beacfc42c7 480 } SCnSCB_Type;
MikamiUitOpen 4:c1beacfc42c7 481
MikamiUitOpen 4:c1beacfc42c7 482 /* Auxiliary Control Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 483 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
MikamiUitOpen 4:c1beacfc42c7 484 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
MikamiUitOpen 4:c1beacfc42c7 485
MikamiUitOpen 4:c1beacfc42c7 486 /*@} end of group CMSIS_SCnotSCB */
MikamiUitOpen 4:c1beacfc42c7 487
MikamiUitOpen 4:c1beacfc42c7 488
MikamiUitOpen 4:c1beacfc42c7 489 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 490 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
MikamiUitOpen 4:c1beacfc42c7 491 \brief Type definitions for the System Timer Registers.
MikamiUitOpen 4:c1beacfc42c7 492 @{
MikamiUitOpen 4:c1beacfc42c7 493 */
MikamiUitOpen 4:c1beacfc42c7 494
MikamiUitOpen 4:c1beacfc42c7 495 /** \brief Structure type to access the System Timer (SysTick).
MikamiUitOpen 4:c1beacfc42c7 496 */
MikamiUitOpen 4:c1beacfc42c7 497 typedef struct
MikamiUitOpen 4:c1beacfc42c7 498 {
MikamiUitOpen 4:c1beacfc42c7 499 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
MikamiUitOpen 4:c1beacfc42c7 500 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
MikamiUitOpen 4:c1beacfc42c7 501 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
MikamiUitOpen 4:c1beacfc42c7 502 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
MikamiUitOpen 4:c1beacfc42c7 503 } SysTick_Type;
MikamiUitOpen 4:c1beacfc42c7 504
MikamiUitOpen 4:c1beacfc42c7 505 /* SysTick Control / Status Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 506 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
MikamiUitOpen 4:c1beacfc42c7 507 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
MikamiUitOpen 4:c1beacfc42c7 508
MikamiUitOpen 4:c1beacfc42c7 509 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
MikamiUitOpen 4:c1beacfc42c7 510 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
MikamiUitOpen 4:c1beacfc42c7 511
MikamiUitOpen 4:c1beacfc42c7 512 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
MikamiUitOpen 4:c1beacfc42c7 513 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
MikamiUitOpen 4:c1beacfc42c7 514
MikamiUitOpen 4:c1beacfc42c7 515 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
MikamiUitOpen 4:c1beacfc42c7 516 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
MikamiUitOpen 4:c1beacfc42c7 517
MikamiUitOpen 4:c1beacfc42c7 518 /* SysTick Reload Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 519 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
MikamiUitOpen 4:c1beacfc42c7 520 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
MikamiUitOpen 4:c1beacfc42c7 521
MikamiUitOpen 4:c1beacfc42c7 522 /* SysTick Current Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 523 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
MikamiUitOpen 4:c1beacfc42c7 524 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
MikamiUitOpen 4:c1beacfc42c7 525
MikamiUitOpen 4:c1beacfc42c7 526 /* SysTick Calibration Register Definitions */
MikamiUitOpen 4:c1beacfc42c7 527 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
MikamiUitOpen 4:c1beacfc42c7 528 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
MikamiUitOpen 4:c1beacfc42c7 529
MikamiUitOpen 4:c1beacfc42c7 530 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
MikamiUitOpen 4:c1beacfc42c7 531 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
MikamiUitOpen 4:c1beacfc42c7 532
MikamiUitOpen 4:c1beacfc42c7 533 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
MikamiUitOpen 4:c1beacfc42c7 534 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
MikamiUitOpen 4:c1beacfc42c7 535
MikamiUitOpen 4:c1beacfc42c7 536 /*@} end of group CMSIS_SysTick */
MikamiUitOpen 4:c1beacfc42c7 537
MikamiUitOpen 4:c1beacfc42c7 538 #if (__MPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 539 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 540 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
MikamiUitOpen 4:c1beacfc42c7 541 \brief Type definitions for the Memory Protection Unit (MPU)
MikamiUitOpen 4:c1beacfc42c7 542 @{
MikamiUitOpen 4:c1beacfc42c7 543 */
MikamiUitOpen 4:c1beacfc42c7 544
MikamiUitOpen 4:c1beacfc42c7 545 /** \brief Structure type to access the Memory Protection Unit (MPU).
MikamiUitOpen 4:c1beacfc42c7 546 */
MikamiUitOpen 4:c1beacfc42c7 547 typedef struct
MikamiUitOpen 4:c1beacfc42c7 548 {
MikamiUitOpen 4:c1beacfc42c7 549 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
MikamiUitOpen 4:c1beacfc42c7 550 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
MikamiUitOpen 4:c1beacfc42c7 551 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
MikamiUitOpen 4:c1beacfc42c7 552 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
MikamiUitOpen 4:c1beacfc42c7 553 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
MikamiUitOpen 4:c1beacfc42c7 554 } MPU_Type;
MikamiUitOpen 4:c1beacfc42c7 555
MikamiUitOpen 4:c1beacfc42c7 556 /* MPU Type Register */
MikamiUitOpen 4:c1beacfc42c7 557 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
MikamiUitOpen 4:c1beacfc42c7 558 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
MikamiUitOpen 4:c1beacfc42c7 559
MikamiUitOpen 4:c1beacfc42c7 560 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
MikamiUitOpen 4:c1beacfc42c7 561 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
MikamiUitOpen 4:c1beacfc42c7 562
MikamiUitOpen 4:c1beacfc42c7 563 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
MikamiUitOpen 4:c1beacfc42c7 564 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
MikamiUitOpen 4:c1beacfc42c7 565
MikamiUitOpen 4:c1beacfc42c7 566 /* MPU Control Register */
MikamiUitOpen 4:c1beacfc42c7 567 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
MikamiUitOpen 4:c1beacfc42c7 568 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
MikamiUitOpen 4:c1beacfc42c7 569
MikamiUitOpen 4:c1beacfc42c7 570 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
MikamiUitOpen 4:c1beacfc42c7 571 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
MikamiUitOpen 4:c1beacfc42c7 572
MikamiUitOpen 4:c1beacfc42c7 573 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
MikamiUitOpen 4:c1beacfc42c7 574 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
MikamiUitOpen 4:c1beacfc42c7 575
MikamiUitOpen 4:c1beacfc42c7 576 /* MPU Region Number Register */
MikamiUitOpen 4:c1beacfc42c7 577 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
MikamiUitOpen 4:c1beacfc42c7 578 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
MikamiUitOpen 4:c1beacfc42c7 579
MikamiUitOpen 4:c1beacfc42c7 580 /* MPU Region Base Address Register */
MikamiUitOpen 4:c1beacfc42c7 581 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
MikamiUitOpen 4:c1beacfc42c7 582 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
MikamiUitOpen 4:c1beacfc42c7 583
MikamiUitOpen 4:c1beacfc42c7 584 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
MikamiUitOpen 4:c1beacfc42c7 585 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
MikamiUitOpen 4:c1beacfc42c7 586
MikamiUitOpen 4:c1beacfc42c7 587 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
MikamiUitOpen 4:c1beacfc42c7 588 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
MikamiUitOpen 4:c1beacfc42c7 589
MikamiUitOpen 4:c1beacfc42c7 590 /* MPU Region Attribute and Size Register */
MikamiUitOpen 4:c1beacfc42c7 591 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
MikamiUitOpen 4:c1beacfc42c7 592 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
MikamiUitOpen 4:c1beacfc42c7 593
MikamiUitOpen 4:c1beacfc42c7 594 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
MikamiUitOpen 4:c1beacfc42c7 595 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
MikamiUitOpen 4:c1beacfc42c7 596
MikamiUitOpen 4:c1beacfc42c7 597 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
MikamiUitOpen 4:c1beacfc42c7 598 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
MikamiUitOpen 4:c1beacfc42c7 599
MikamiUitOpen 4:c1beacfc42c7 600 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
MikamiUitOpen 4:c1beacfc42c7 601 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
MikamiUitOpen 4:c1beacfc42c7 602
MikamiUitOpen 4:c1beacfc42c7 603 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
MikamiUitOpen 4:c1beacfc42c7 604 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
MikamiUitOpen 4:c1beacfc42c7 605
MikamiUitOpen 4:c1beacfc42c7 606 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
MikamiUitOpen 4:c1beacfc42c7 607 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
MikamiUitOpen 4:c1beacfc42c7 608
MikamiUitOpen 4:c1beacfc42c7 609 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
MikamiUitOpen 4:c1beacfc42c7 610 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
MikamiUitOpen 4:c1beacfc42c7 611
MikamiUitOpen 4:c1beacfc42c7 612 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
MikamiUitOpen 4:c1beacfc42c7 613 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
MikamiUitOpen 4:c1beacfc42c7 614
MikamiUitOpen 4:c1beacfc42c7 615 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
MikamiUitOpen 4:c1beacfc42c7 616 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
MikamiUitOpen 4:c1beacfc42c7 617
MikamiUitOpen 4:c1beacfc42c7 618 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
MikamiUitOpen 4:c1beacfc42c7 619 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
MikamiUitOpen 4:c1beacfc42c7 620
MikamiUitOpen 4:c1beacfc42c7 621 /*@} end of group CMSIS_MPU */
MikamiUitOpen 4:c1beacfc42c7 622 #endif
MikamiUitOpen 4:c1beacfc42c7 623
MikamiUitOpen 4:c1beacfc42c7 624
MikamiUitOpen 4:c1beacfc42c7 625 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 626 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MikamiUitOpen 4:c1beacfc42c7 627 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
MikamiUitOpen 4:c1beacfc42c7 628 are only accessible over DAP and not via processor. Therefore
MikamiUitOpen 4:c1beacfc42c7 629 they are not covered by the Cortex-M0 header file.
MikamiUitOpen 4:c1beacfc42c7 630 @{
MikamiUitOpen 4:c1beacfc42c7 631 */
MikamiUitOpen 4:c1beacfc42c7 632 /*@} end of group CMSIS_CoreDebug */
MikamiUitOpen 4:c1beacfc42c7 633
MikamiUitOpen 4:c1beacfc42c7 634
MikamiUitOpen 4:c1beacfc42c7 635 /** \ingroup CMSIS_core_register
MikamiUitOpen 4:c1beacfc42c7 636 \defgroup CMSIS_core_base Core Definitions
MikamiUitOpen 4:c1beacfc42c7 637 \brief Definitions for base addresses, unions, and structures.
MikamiUitOpen 4:c1beacfc42c7 638 @{
MikamiUitOpen 4:c1beacfc42c7 639 */
MikamiUitOpen 4:c1beacfc42c7 640
MikamiUitOpen 4:c1beacfc42c7 641 /* Memory mapping of SC000 Hardware */
MikamiUitOpen 4:c1beacfc42c7 642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
MikamiUitOpen 4:c1beacfc42c7 643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
MikamiUitOpen 4:c1beacfc42c7 644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
MikamiUitOpen 4:c1beacfc42c7 645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
MikamiUitOpen 4:c1beacfc42c7 646
MikamiUitOpen 4:c1beacfc42c7 647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
MikamiUitOpen 4:c1beacfc42c7 648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
MikamiUitOpen 4:c1beacfc42c7 649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
MikamiUitOpen 4:c1beacfc42c7 650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
MikamiUitOpen 4:c1beacfc42c7 651
MikamiUitOpen 4:c1beacfc42c7 652 #if (__MPU_PRESENT == 1)
MikamiUitOpen 4:c1beacfc42c7 653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
MikamiUitOpen 4:c1beacfc42c7 654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
MikamiUitOpen 4:c1beacfc42c7 655 #endif
MikamiUitOpen 4:c1beacfc42c7 656
MikamiUitOpen 4:c1beacfc42c7 657 /*@} */
MikamiUitOpen 4:c1beacfc42c7 658
MikamiUitOpen 4:c1beacfc42c7 659
MikamiUitOpen 4:c1beacfc42c7 660
MikamiUitOpen 4:c1beacfc42c7 661 /*******************************************************************************
MikamiUitOpen 4:c1beacfc42c7 662 * Hardware Abstraction Layer
MikamiUitOpen 4:c1beacfc42c7 663 Core Function Interface contains:
MikamiUitOpen 4:c1beacfc42c7 664 - Core NVIC Functions
MikamiUitOpen 4:c1beacfc42c7 665 - Core SysTick Functions
MikamiUitOpen 4:c1beacfc42c7 666 - Core Register Access Functions
MikamiUitOpen 4:c1beacfc42c7 667 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 668 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MikamiUitOpen 4:c1beacfc42c7 669 */
MikamiUitOpen 4:c1beacfc42c7 670
MikamiUitOpen 4:c1beacfc42c7 671
MikamiUitOpen 4:c1beacfc42c7 672
MikamiUitOpen 4:c1beacfc42c7 673 /* ########################## NVIC functions #################################### */
MikamiUitOpen 4:c1beacfc42c7 674 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 4:c1beacfc42c7 675 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
MikamiUitOpen 4:c1beacfc42c7 676 \brief Functions that manage interrupts and exceptions via the NVIC.
MikamiUitOpen 4:c1beacfc42c7 677 @{
MikamiUitOpen 4:c1beacfc42c7 678 */
MikamiUitOpen 4:c1beacfc42c7 679
MikamiUitOpen 4:c1beacfc42c7 680 /* Interrupt Priorities are WORD accessible only under ARMv6M */
MikamiUitOpen 4:c1beacfc42c7 681 /* The following MACROS handle generation of the register offset and byte masks */
MikamiUitOpen 4:c1beacfc42c7 682 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
MikamiUitOpen 4:c1beacfc42c7 683 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
MikamiUitOpen 4:c1beacfc42c7 684 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
MikamiUitOpen 4:c1beacfc42c7 685
MikamiUitOpen 4:c1beacfc42c7 686
MikamiUitOpen 4:c1beacfc42c7 687 /** \brief Enable External Interrupt
MikamiUitOpen 4:c1beacfc42c7 688
MikamiUitOpen 4:c1beacfc42c7 689 The function enables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 4:c1beacfc42c7 690
MikamiUitOpen 4:c1beacfc42c7 691 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 4:c1beacfc42c7 692 */
MikamiUitOpen 4:c1beacfc42c7 693 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 694 {
MikamiUitOpen 4:c1beacfc42c7 695 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 4:c1beacfc42c7 696 }
MikamiUitOpen 4:c1beacfc42c7 697
MikamiUitOpen 4:c1beacfc42c7 698
MikamiUitOpen 4:c1beacfc42c7 699 /** \brief Disable External Interrupt
MikamiUitOpen 4:c1beacfc42c7 700
MikamiUitOpen 4:c1beacfc42c7 701 The function disables a device-specific interrupt in the NVIC interrupt controller.
MikamiUitOpen 4:c1beacfc42c7 702
MikamiUitOpen 4:c1beacfc42c7 703 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 4:c1beacfc42c7 704 */
MikamiUitOpen 4:c1beacfc42c7 705 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 706 {
MikamiUitOpen 4:c1beacfc42c7 707 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 4:c1beacfc42c7 708 }
MikamiUitOpen 4:c1beacfc42c7 709
MikamiUitOpen 4:c1beacfc42c7 710
MikamiUitOpen 4:c1beacfc42c7 711 /** \brief Get Pending Interrupt
MikamiUitOpen 4:c1beacfc42c7 712
MikamiUitOpen 4:c1beacfc42c7 713 The function reads the pending register in the NVIC and returns the pending bit
MikamiUitOpen 4:c1beacfc42c7 714 for the specified interrupt.
MikamiUitOpen 4:c1beacfc42c7 715
MikamiUitOpen 4:c1beacfc42c7 716 \param [in] IRQn Interrupt number.
MikamiUitOpen 4:c1beacfc42c7 717
MikamiUitOpen 4:c1beacfc42c7 718 \return 0 Interrupt status is not pending.
MikamiUitOpen 4:c1beacfc42c7 719 \return 1 Interrupt status is pending.
MikamiUitOpen 4:c1beacfc42c7 720 */
MikamiUitOpen 4:c1beacfc42c7 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 722 {
MikamiUitOpen 4:c1beacfc42c7 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MikamiUitOpen 4:c1beacfc42c7 724 }
MikamiUitOpen 4:c1beacfc42c7 725
MikamiUitOpen 4:c1beacfc42c7 726
MikamiUitOpen 4:c1beacfc42c7 727 /** \brief Set Pending Interrupt
MikamiUitOpen 4:c1beacfc42c7 728
MikamiUitOpen 4:c1beacfc42c7 729 The function sets the pending bit of an external interrupt.
MikamiUitOpen 4:c1beacfc42c7 730
MikamiUitOpen 4:c1beacfc42c7 731 \param [in] IRQn Interrupt number. Value cannot be negative.
MikamiUitOpen 4:c1beacfc42c7 732 */
MikamiUitOpen 4:c1beacfc42c7 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 734 {
MikamiUitOpen 4:c1beacfc42c7 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 4:c1beacfc42c7 736 }
MikamiUitOpen 4:c1beacfc42c7 737
MikamiUitOpen 4:c1beacfc42c7 738
MikamiUitOpen 4:c1beacfc42c7 739 /** \brief Clear Pending Interrupt
MikamiUitOpen 4:c1beacfc42c7 740
MikamiUitOpen 4:c1beacfc42c7 741 The function clears the pending bit of an external interrupt.
MikamiUitOpen 4:c1beacfc42c7 742
MikamiUitOpen 4:c1beacfc42c7 743 \param [in] IRQn External interrupt number. Value cannot be negative.
MikamiUitOpen 4:c1beacfc42c7 744 */
MikamiUitOpen 4:c1beacfc42c7 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 746 {
MikamiUitOpen 4:c1beacfc42c7 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MikamiUitOpen 4:c1beacfc42c7 748 }
MikamiUitOpen 4:c1beacfc42c7 749
MikamiUitOpen 4:c1beacfc42c7 750
MikamiUitOpen 4:c1beacfc42c7 751 /** \brief Set Interrupt Priority
MikamiUitOpen 4:c1beacfc42c7 752
MikamiUitOpen 4:c1beacfc42c7 753 The function sets the priority of an interrupt.
MikamiUitOpen 4:c1beacfc42c7 754
MikamiUitOpen 4:c1beacfc42c7 755 \note The priority cannot be set for every core interrupt.
MikamiUitOpen 4:c1beacfc42c7 756
MikamiUitOpen 4:c1beacfc42c7 757 \param [in] IRQn Interrupt number.
MikamiUitOpen 4:c1beacfc42c7 758 \param [in] priority Priority to set.
MikamiUitOpen 4:c1beacfc42c7 759 */
MikamiUitOpen 4:c1beacfc42c7 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MikamiUitOpen 4:c1beacfc42c7 761 {
MikamiUitOpen 4:c1beacfc42c7 762 if((int32_t)(IRQn) < 0) {
MikamiUitOpen 4:c1beacfc42c7 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
MikamiUitOpen 4:c1beacfc42c7 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
MikamiUitOpen 4:c1beacfc42c7 765 }
MikamiUitOpen 4:c1beacfc42c7 766 else {
MikamiUitOpen 4:c1beacfc42c7 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
MikamiUitOpen 4:c1beacfc42c7 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
MikamiUitOpen 4:c1beacfc42c7 769 }
MikamiUitOpen 4:c1beacfc42c7 770 }
MikamiUitOpen 4:c1beacfc42c7 771
MikamiUitOpen 4:c1beacfc42c7 772
MikamiUitOpen 4:c1beacfc42c7 773 /** \brief Get Interrupt Priority
MikamiUitOpen 4:c1beacfc42c7 774
MikamiUitOpen 4:c1beacfc42c7 775 The function reads the priority of an interrupt. The interrupt
MikamiUitOpen 4:c1beacfc42c7 776 number can be positive to specify an external (device specific)
MikamiUitOpen 4:c1beacfc42c7 777 interrupt, or negative to specify an internal (core) interrupt.
MikamiUitOpen 4:c1beacfc42c7 778
MikamiUitOpen 4:c1beacfc42c7 779
MikamiUitOpen 4:c1beacfc42c7 780 \param [in] IRQn Interrupt number.
MikamiUitOpen 4:c1beacfc42c7 781 \return Interrupt Priority. Value is aligned automatically to the implemented
MikamiUitOpen 4:c1beacfc42c7 782 priority bits of the microcontroller.
MikamiUitOpen 4:c1beacfc42c7 783 */
MikamiUitOpen 4:c1beacfc42c7 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
MikamiUitOpen 4:c1beacfc42c7 785 {
MikamiUitOpen 4:c1beacfc42c7 786
MikamiUitOpen 4:c1beacfc42c7 787 if((int32_t)(IRQn) < 0) {
MikamiUitOpen 4:c1beacfc42c7 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 4:c1beacfc42c7 789 }
MikamiUitOpen 4:c1beacfc42c7 790 else {
MikamiUitOpen 4:c1beacfc42c7 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
MikamiUitOpen 4:c1beacfc42c7 792 }
MikamiUitOpen 4:c1beacfc42c7 793 }
MikamiUitOpen 4:c1beacfc42c7 794
MikamiUitOpen 4:c1beacfc42c7 795
MikamiUitOpen 4:c1beacfc42c7 796 /** \brief System Reset
MikamiUitOpen 4:c1beacfc42c7 797
MikamiUitOpen 4:c1beacfc42c7 798 The function initiates a system reset request to reset the MCU.
MikamiUitOpen 4:c1beacfc42c7 799 */
MikamiUitOpen 4:c1beacfc42c7 800 __STATIC_INLINE void NVIC_SystemReset(void)
MikamiUitOpen 4:c1beacfc42c7 801 {
MikamiUitOpen 4:c1beacfc42c7 802 __DSB(); /* Ensure all outstanding memory accesses included
MikamiUitOpen 4:c1beacfc42c7 803 buffered write are completed before reset */
MikamiUitOpen 4:c1beacfc42c7 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
MikamiUitOpen 4:c1beacfc42c7 805 SCB_AIRCR_SYSRESETREQ_Msk);
MikamiUitOpen 4:c1beacfc42c7 806 __DSB(); /* Ensure completion of memory access */
MikamiUitOpen 4:c1beacfc42c7 807 while(1) { __NOP(); } /* wait until reset */
MikamiUitOpen 4:c1beacfc42c7 808 }
MikamiUitOpen 4:c1beacfc42c7 809
MikamiUitOpen 4:c1beacfc42c7 810 /*@} end of CMSIS_Core_NVICFunctions */
MikamiUitOpen 4:c1beacfc42c7 811
MikamiUitOpen 4:c1beacfc42c7 812
MikamiUitOpen 4:c1beacfc42c7 813
MikamiUitOpen 4:c1beacfc42c7 814 /* ################################## SysTick function ############################################ */
MikamiUitOpen 4:c1beacfc42c7 815 /** \ingroup CMSIS_Core_FunctionInterface
MikamiUitOpen 4:c1beacfc42c7 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MikamiUitOpen 4:c1beacfc42c7 817 \brief Functions that configure the System.
MikamiUitOpen 4:c1beacfc42c7 818 @{
MikamiUitOpen 4:c1beacfc42c7 819 */
MikamiUitOpen 4:c1beacfc42c7 820
MikamiUitOpen 4:c1beacfc42c7 821 #if (__Vendor_SysTickConfig == 0)
MikamiUitOpen 4:c1beacfc42c7 822
MikamiUitOpen 4:c1beacfc42c7 823 /** \brief System Tick Configuration
MikamiUitOpen 4:c1beacfc42c7 824
MikamiUitOpen 4:c1beacfc42c7 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
MikamiUitOpen 4:c1beacfc42c7 826 Counter is in free running mode to generate periodic interrupts.
MikamiUitOpen 4:c1beacfc42c7 827
MikamiUitOpen 4:c1beacfc42c7 828 \param [in] ticks Number of ticks between two interrupts.
MikamiUitOpen 4:c1beacfc42c7 829
MikamiUitOpen 4:c1beacfc42c7 830 \return 0 Function succeeded.
MikamiUitOpen 4:c1beacfc42c7 831 \return 1 Function failed.
MikamiUitOpen 4:c1beacfc42c7 832
MikamiUitOpen 4:c1beacfc42c7 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MikamiUitOpen 4:c1beacfc42c7 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MikamiUitOpen 4:c1beacfc42c7 835 must contain a vendor-specific implementation of this function.
MikamiUitOpen 4:c1beacfc42c7 836
MikamiUitOpen 4:c1beacfc42c7 837 */
MikamiUitOpen 4:c1beacfc42c7 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MikamiUitOpen 4:c1beacfc42c7 839 {
MikamiUitOpen 4:c1beacfc42c7 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
MikamiUitOpen 4:c1beacfc42c7 841
MikamiUitOpen 4:c1beacfc42c7 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MikamiUitOpen 4:c1beacfc42c7 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MikamiUitOpen 4:c1beacfc42c7 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MikamiUitOpen 4:c1beacfc42c7 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
MikamiUitOpen 4:c1beacfc42c7 846 SysTick_CTRL_TICKINT_Msk |
MikamiUitOpen 4:c1beacfc42c7 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MikamiUitOpen 4:c1beacfc42c7 848 return (0UL); /* Function successful */
MikamiUitOpen 4:c1beacfc42c7 849 }
MikamiUitOpen 4:c1beacfc42c7 850
MikamiUitOpen 4:c1beacfc42c7 851 #endif
MikamiUitOpen 4:c1beacfc42c7 852
MikamiUitOpen 4:c1beacfc42c7 853 /*@} end of CMSIS_Core_SysTickFunctions */
MikamiUitOpen 4:c1beacfc42c7 854
MikamiUitOpen 4:c1beacfc42c7 855
MikamiUitOpen 4:c1beacfc42c7 856
MikamiUitOpen 4:c1beacfc42c7 857
MikamiUitOpen 4:c1beacfc42c7 858 #ifdef __cplusplus
MikamiUitOpen 4:c1beacfc42c7 859 }
MikamiUitOpen 4:c1beacfc42c7 860 #endif
MikamiUitOpen 4:c1beacfc42c7 861
MikamiUitOpen 4:c1beacfc42c7 862 #endif /* __CORE_SC000_H_DEPENDANT */
MikamiUitOpen 4:c1beacfc42c7 863
MikamiUitOpen 4:c1beacfc42c7 864 #endif /* __CMSIS_GENERIC */