不韋 呂 / F746_Spectrogram

Realtime spectrogram for DISCO-F746NG. On-board MEMS microphone is used for input sound signal. リアルタイムスペクトログラム．入力：MEMSマイク

Dependencies:   F746_GUI F746_SAI_IO UIT_FFT_Real

mbed_src_STM32F7/targets/cmsis/core_cmInstr.h@6:b3885567877c, 2017-04-10 (annotated)

Committer:
MikamiUitOpen
Date:
Mon Apr 10 13:43:07 2017 +0000
Revision:
6:b3885567877c
Parent:
4:c1beacfc42c7 
7

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MikamiUitOpen 4:c1beacfc42c7 1 /**************************************************************************//**
MikamiUitOpen 4:c1beacfc42c7 2 * @file core_cmInstr.h
MikamiUitOpen 4:c1beacfc42c7 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
MikamiUitOpen 4:c1beacfc42c7 4 * @version V4.10
MikamiUitOpen 4:c1beacfc42c7 5 * @date 18. March 2015
MikamiUitOpen 4:c1beacfc42c7 6 *
MikamiUitOpen 4:c1beacfc42c7 7 * @note
MikamiUitOpen 4:c1beacfc42c7 8 *
MikamiUitOpen 4:c1beacfc42c7 9 ******************************************************************************/
MikamiUitOpen 4:c1beacfc42c7 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
MikamiUitOpen 4:c1beacfc42c7 11
MikamiUitOpen 4:c1beacfc42c7 12 All rights reserved.
MikamiUitOpen 4:c1beacfc42c7 13 Redistribution and use in source and binary forms, with or without
MikamiUitOpen 4:c1beacfc42c7 14 modification, are permitted provided that the following conditions are met:
MikamiUitOpen 4:c1beacfc42c7 15 - Redistributions of source code must retain the above copyright
MikamiUitOpen 4:c1beacfc42c7 16 notice, this list of conditions and the following disclaimer.
MikamiUitOpen 4:c1beacfc42c7 17 - Redistributions in binary form must reproduce the above copyright
MikamiUitOpen 4:c1beacfc42c7 18 notice, this list of conditions and the following disclaimer in the
MikamiUitOpen 4:c1beacfc42c7 19 documentation and/or other materials provided with the distribution.
MikamiUitOpen 4:c1beacfc42c7 20 - Neither the name of ARM nor the names of its contributors may be used
MikamiUitOpen 4:c1beacfc42c7 21 to endorse or promote products derived from this software without
MikamiUitOpen 4:c1beacfc42c7 22 specific prior written permission.
MikamiUitOpen 4:c1beacfc42c7 23 *
MikamiUitOpen 4:c1beacfc42c7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MikamiUitOpen 4:c1beacfc42c7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MikamiUitOpen 4:c1beacfc42c7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
MikamiUitOpen 4:c1beacfc42c7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
MikamiUitOpen 4:c1beacfc42c7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
MikamiUitOpen 4:c1beacfc42c7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
MikamiUitOpen 4:c1beacfc42c7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
MikamiUitOpen 4:c1beacfc42c7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
MikamiUitOpen 4:c1beacfc42c7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
MikamiUitOpen 4:c1beacfc42c7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
MikamiUitOpen 4:c1beacfc42c7 34 POSSIBILITY OF SUCH DAMAGE.
MikamiUitOpen 4:c1beacfc42c7 35 ---------------------------------------------------------------------------*/
MikamiUitOpen 4:c1beacfc42c7 36
MikamiUitOpen 4:c1beacfc42c7 37
MikamiUitOpen 4:c1beacfc42c7 38 #ifndef __CORE_CMINSTR_H
MikamiUitOpen 4:c1beacfc42c7 39 #define __CORE_CMINSTR_H
MikamiUitOpen 4:c1beacfc42c7 40
MikamiUitOpen 4:c1beacfc42c7 41
MikamiUitOpen 4:c1beacfc42c7 42 /* ########################## Core Instruction Access ######################### */
MikamiUitOpen 4:c1beacfc42c7 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
MikamiUitOpen 4:c1beacfc42c7 44 Access to dedicated instructions
MikamiUitOpen 4:c1beacfc42c7 45 @{
MikamiUitOpen 4:c1beacfc42c7 46 */
MikamiUitOpen 4:c1beacfc42c7 47
MikamiUitOpen 4:c1beacfc42c7 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
MikamiUitOpen 4:c1beacfc42c7 49 /* ARM armcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 50
MikamiUitOpen 4:c1beacfc42c7 51 #if (__ARMCC_VERSION < 400677)
MikamiUitOpen 4:c1beacfc42c7 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
MikamiUitOpen 4:c1beacfc42c7 53 #endif
MikamiUitOpen 4:c1beacfc42c7 54
MikamiUitOpen 4:c1beacfc42c7 55
MikamiUitOpen 4:c1beacfc42c7 56 /** \brief No Operation
MikamiUitOpen 4:c1beacfc42c7 57
MikamiUitOpen 4:c1beacfc42c7 58 No Operation does nothing. This instruction can be used for code alignment purposes.
MikamiUitOpen 4:c1beacfc42c7 59 */
MikamiUitOpen 4:c1beacfc42c7 60 #define __NOP __nop
MikamiUitOpen 4:c1beacfc42c7 61
MikamiUitOpen 4:c1beacfc42c7 62
MikamiUitOpen 4:c1beacfc42c7 63 /** \brief Wait For Interrupt
MikamiUitOpen 4:c1beacfc42c7 64
MikamiUitOpen 4:c1beacfc42c7 65 Wait For Interrupt is a hint instruction that suspends execution
MikamiUitOpen 4:c1beacfc42c7 66 until one of a number of events occurs.
MikamiUitOpen 4:c1beacfc42c7 67 */
MikamiUitOpen 4:c1beacfc42c7 68 #define __WFI __wfi
MikamiUitOpen 4:c1beacfc42c7 69
MikamiUitOpen 4:c1beacfc42c7 70
MikamiUitOpen 4:c1beacfc42c7 71 /** \brief Wait For Event
MikamiUitOpen 4:c1beacfc42c7 72
MikamiUitOpen 4:c1beacfc42c7 73 Wait For Event is a hint instruction that permits the processor to enter
MikamiUitOpen 4:c1beacfc42c7 74 a low-power state until one of a number of events occurs.
MikamiUitOpen 4:c1beacfc42c7 75 */
MikamiUitOpen 4:c1beacfc42c7 76 #define __WFE __wfe
MikamiUitOpen 4:c1beacfc42c7 77
MikamiUitOpen 4:c1beacfc42c7 78
MikamiUitOpen 4:c1beacfc42c7 79 /** \brief Send Event
MikamiUitOpen 4:c1beacfc42c7 80
MikamiUitOpen 4:c1beacfc42c7 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
MikamiUitOpen 4:c1beacfc42c7 82 */
MikamiUitOpen 4:c1beacfc42c7 83 #define __SEV __sev
MikamiUitOpen 4:c1beacfc42c7 84
MikamiUitOpen 4:c1beacfc42c7 85
MikamiUitOpen 4:c1beacfc42c7 86 /** \brief Instruction Synchronization Barrier
MikamiUitOpen 4:c1beacfc42c7 87
MikamiUitOpen 4:c1beacfc42c7 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
MikamiUitOpen 4:c1beacfc42c7 89 so that all instructions following the ISB are fetched from cache or
MikamiUitOpen 4:c1beacfc42c7 90 memory, after the instruction has been completed.
MikamiUitOpen 4:c1beacfc42c7 91 */
MikamiUitOpen 4:c1beacfc42c7 92 #define __ISB() do {\
MikamiUitOpen 4:c1beacfc42c7 93 __schedule_barrier();\
MikamiUitOpen 4:c1beacfc42c7 94 __isb(0xF);\
MikamiUitOpen 4:c1beacfc42c7 95 __schedule_barrier();\
MikamiUitOpen 4:c1beacfc42c7 96 } while (0)
MikamiUitOpen 4:c1beacfc42c7 97
MikamiUitOpen 4:c1beacfc42c7 98 /** \brief Data Synchronization Barrier
MikamiUitOpen 4:c1beacfc42c7 99
MikamiUitOpen 4:c1beacfc42c7 100 This function acts as a special kind of Data Memory Barrier.
MikamiUitOpen 4:c1beacfc42c7 101 It completes when all explicit memory accesses before this instruction complete.
MikamiUitOpen 4:c1beacfc42c7 102 */
MikamiUitOpen 4:c1beacfc42c7 103 #define __DSB() do {\
MikamiUitOpen 4:c1beacfc42c7 104 __schedule_barrier();\
MikamiUitOpen 4:c1beacfc42c7 105 __dsb(0xF);\
MikamiUitOpen 4:c1beacfc42c7 106 __schedule_barrier();\
MikamiUitOpen 4:c1beacfc42c7 107 } while (0)
MikamiUitOpen 4:c1beacfc42c7 108
MikamiUitOpen 4:c1beacfc42c7 109 /** \brief Data Memory Barrier
MikamiUitOpen 4:c1beacfc42c7 110
MikamiUitOpen 4:c1beacfc42c7 111 This function ensures the apparent order of the explicit memory operations before
MikamiUitOpen 4:c1beacfc42c7 112 and after the instruction, without ensuring their completion.
MikamiUitOpen 4:c1beacfc42c7 113 */
MikamiUitOpen 4:c1beacfc42c7 114 #define __DMB() do {\
MikamiUitOpen 4:c1beacfc42c7 115 __schedule_barrier();\
MikamiUitOpen 4:c1beacfc42c7 116 __dmb(0xF);\
MikamiUitOpen 4:c1beacfc42c7 117 __schedule_barrier();\
MikamiUitOpen 4:c1beacfc42c7 118 } while (0)
MikamiUitOpen 4:c1beacfc42c7 119
MikamiUitOpen 4:c1beacfc42c7 120 /** \brief Reverse byte order (32 bit)
MikamiUitOpen 4:c1beacfc42c7 121
MikamiUitOpen 4:c1beacfc42c7 122 This function reverses the byte order in integer value.
MikamiUitOpen 4:c1beacfc42c7 123
MikamiUitOpen 4:c1beacfc42c7 124 \param [in] value Value to reverse
MikamiUitOpen 4:c1beacfc42c7 125 \return Reversed value
MikamiUitOpen 4:c1beacfc42c7 126 */
MikamiUitOpen 4:c1beacfc42c7 127 #define __REV __rev
MikamiUitOpen 4:c1beacfc42c7 128
MikamiUitOpen 4:c1beacfc42c7 129
MikamiUitOpen 4:c1beacfc42c7 130 /** \brief Reverse byte order (16 bit)
MikamiUitOpen 4:c1beacfc42c7 131
MikamiUitOpen 4:c1beacfc42c7 132 This function reverses the byte order in two unsigned short values.
MikamiUitOpen 4:c1beacfc42c7 133
MikamiUitOpen 4:c1beacfc42c7 134 \param [in] value Value to reverse
MikamiUitOpen 4:c1beacfc42c7 135 \return Reversed value
MikamiUitOpen 4:c1beacfc42c7 136 */
MikamiUitOpen 4:c1beacfc42c7 137 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 4:c1beacfc42c7 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 139 {
MikamiUitOpen 4:c1beacfc42c7 140 rev16 r0, r0
MikamiUitOpen 4:c1beacfc42c7 141 bx lr
MikamiUitOpen 4:c1beacfc42c7 142 }
MikamiUitOpen 4:c1beacfc42c7 143 #endif
MikamiUitOpen 4:c1beacfc42c7 144
MikamiUitOpen 4:c1beacfc42c7 145 /** \brief Reverse byte order in signed short value
MikamiUitOpen 4:c1beacfc42c7 146
MikamiUitOpen 4:c1beacfc42c7 147 This function reverses the byte order in a signed short value with sign extension to integer.
MikamiUitOpen 4:c1beacfc42c7 148
MikamiUitOpen 4:c1beacfc42c7 149 \param [in] value Value to reverse
MikamiUitOpen 4:c1beacfc42c7 150 \return Reversed value
MikamiUitOpen 4:c1beacfc42c7 151 */
MikamiUitOpen 4:c1beacfc42c7 152 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 4:c1beacfc42c7 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
MikamiUitOpen 4:c1beacfc42c7 154 {
MikamiUitOpen 4:c1beacfc42c7 155 revsh r0, r0
MikamiUitOpen 4:c1beacfc42c7 156 bx lr
MikamiUitOpen 4:c1beacfc42c7 157 }
MikamiUitOpen 4:c1beacfc42c7 158 #endif
MikamiUitOpen 4:c1beacfc42c7 159
MikamiUitOpen 4:c1beacfc42c7 160
MikamiUitOpen 4:c1beacfc42c7 161 /** \brief Rotate Right in unsigned value (32 bit)
MikamiUitOpen 4:c1beacfc42c7 162
MikamiUitOpen 4:c1beacfc42c7 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
MikamiUitOpen 4:c1beacfc42c7 164
MikamiUitOpen 4:c1beacfc42c7 165 \param [in] value Value to rotate
MikamiUitOpen 4:c1beacfc42c7 166 \param [in] value Number of Bits to rotate
MikamiUitOpen 4:c1beacfc42c7 167 \return Rotated value
MikamiUitOpen 4:c1beacfc42c7 168 */
MikamiUitOpen 4:c1beacfc42c7 169 #define __ROR __ror
MikamiUitOpen 4:c1beacfc42c7 170
MikamiUitOpen 4:c1beacfc42c7 171
MikamiUitOpen 4:c1beacfc42c7 172 /** \brief Breakpoint
MikamiUitOpen 4:c1beacfc42c7 173
MikamiUitOpen 4:c1beacfc42c7 174 This function causes the processor to enter Debug state.
MikamiUitOpen 4:c1beacfc42c7 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
MikamiUitOpen 4:c1beacfc42c7 176
MikamiUitOpen 4:c1beacfc42c7 177 \param [in] value is ignored by the processor.
MikamiUitOpen 4:c1beacfc42c7 178 If required, a debugger can use it to store additional information about the breakpoint.
MikamiUitOpen 4:c1beacfc42c7 179 */
MikamiUitOpen 4:c1beacfc42c7 180 #define __BKPT(value) __breakpoint(value)
MikamiUitOpen 4:c1beacfc42c7 181
MikamiUitOpen 4:c1beacfc42c7 182
MikamiUitOpen 4:c1beacfc42c7 183 /** \brief Reverse bit order of value
MikamiUitOpen 4:c1beacfc42c7 184
MikamiUitOpen 4:c1beacfc42c7 185 This function reverses the bit order of the given value.
MikamiUitOpen 4:c1beacfc42c7 186
MikamiUitOpen 4:c1beacfc42c7 187 \param [in] value Value to reverse
MikamiUitOpen 4:c1beacfc42c7 188 \return Reversed value
MikamiUitOpen 4:c1beacfc42c7 189 */
MikamiUitOpen 4:c1beacfc42c7 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 4:c1beacfc42c7 191 #define __RBIT __rbit
MikamiUitOpen 4:c1beacfc42c7 192 #else
MikamiUitOpen 4:c1beacfc42c7 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 194 {
MikamiUitOpen 4:c1beacfc42c7 195 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
MikamiUitOpen 4:c1beacfc42c7 197
MikamiUitOpen 4:c1beacfc42c7 198 result = value; // r will be reversed bits of v; first get LSB of v
MikamiUitOpen 4:c1beacfc42c7 199 for (value >>= 1; value; value >>= 1)
MikamiUitOpen 4:c1beacfc42c7 200 {
MikamiUitOpen 4:c1beacfc42c7 201 result <<= 1;
MikamiUitOpen 4:c1beacfc42c7 202 result |= value & 1;
MikamiUitOpen 4:c1beacfc42c7 203 s--;
MikamiUitOpen 4:c1beacfc42c7 204 }
MikamiUitOpen 4:c1beacfc42c7 205 result <<= s; // shift when v's highest bits are zero
MikamiUitOpen 4:c1beacfc42c7 206 return(result);
MikamiUitOpen 4:c1beacfc42c7 207 }
MikamiUitOpen 4:c1beacfc42c7 208 #endif
MikamiUitOpen 4:c1beacfc42c7 209
MikamiUitOpen 4:c1beacfc42c7 210
MikamiUitOpen 4:c1beacfc42c7 211 /** \brief Count leading zeros
MikamiUitOpen 4:c1beacfc42c7 212
MikamiUitOpen 4:c1beacfc42c7 213 This function counts the number of leading zeros of a data value.
MikamiUitOpen 4:c1beacfc42c7 214
MikamiUitOpen 4:c1beacfc42c7 215 \param [in] value Value to count the leading zeros
MikamiUitOpen 4:c1beacfc42c7 216 \return number of leading zeros in value
MikamiUitOpen 4:c1beacfc42c7 217 */
MikamiUitOpen 4:c1beacfc42c7 218 #define __CLZ __clz
MikamiUitOpen 4:c1beacfc42c7 219
MikamiUitOpen 4:c1beacfc42c7 220
MikamiUitOpen 4:c1beacfc42c7 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 4:c1beacfc42c7 222
MikamiUitOpen 4:c1beacfc42c7 223 /** \brief LDR Exclusive (8 bit)
MikamiUitOpen 4:c1beacfc42c7 224
MikamiUitOpen 4:c1beacfc42c7 225 This function executes a exclusive LDR instruction for 8 bit value.
MikamiUitOpen 4:c1beacfc42c7 226
MikamiUitOpen 4:c1beacfc42c7 227 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 228 \return value of type uint8_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 229 */
MikamiUitOpen 4:c1beacfc42c7 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
MikamiUitOpen 4:c1beacfc42c7 231
MikamiUitOpen 4:c1beacfc42c7 232
MikamiUitOpen 4:c1beacfc42c7 233 /** \brief LDR Exclusive (16 bit)
MikamiUitOpen 4:c1beacfc42c7 234
MikamiUitOpen 4:c1beacfc42c7 235 This function executes a exclusive LDR instruction for 16 bit values.
MikamiUitOpen 4:c1beacfc42c7 236
MikamiUitOpen 4:c1beacfc42c7 237 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 238 \return value of type uint16_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 239 */
MikamiUitOpen 4:c1beacfc42c7 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
MikamiUitOpen 4:c1beacfc42c7 241
MikamiUitOpen 4:c1beacfc42c7 242
MikamiUitOpen 4:c1beacfc42c7 243 /** \brief LDR Exclusive (32 bit)
MikamiUitOpen 4:c1beacfc42c7 244
MikamiUitOpen 4:c1beacfc42c7 245 This function executes a exclusive LDR instruction for 32 bit values.
MikamiUitOpen 4:c1beacfc42c7 246
MikamiUitOpen 4:c1beacfc42c7 247 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 248 \return value of type uint32_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 249 */
MikamiUitOpen 4:c1beacfc42c7 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
MikamiUitOpen 4:c1beacfc42c7 251
MikamiUitOpen 4:c1beacfc42c7 252
MikamiUitOpen 4:c1beacfc42c7 253 /** \brief STR Exclusive (8 bit)
MikamiUitOpen 4:c1beacfc42c7 254
MikamiUitOpen 4:c1beacfc42c7 255 This function executes a exclusive STR instruction for 8 bit values.
MikamiUitOpen 4:c1beacfc42c7 256
MikamiUitOpen 4:c1beacfc42c7 257 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 258 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 259 \return 0 Function succeeded
MikamiUitOpen 4:c1beacfc42c7 260 \return 1 Function failed
MikamiUitOpen 4:c1beacfc42c7 261 */
MikamiUitOpen 4:c1beacfc42c7 262 #define __STREXB(value, ptr) __strex(value, ptr)
MikamiUitOpen 4:c1beacfc42c7 263
MikamiUitOpen 4:c1beacfc42c7 264
MikamiUitOpen 4:c1beacfc42c7 265 /** \brief STR Exclusive (16 bit)
MikamiUitOpen 4:c1beacfc42c7 266
MikamiUitOpen 4:c1beacfc42c7 267 This function executes a exclusive STR instruction for 16 bit values.
MikamiUitOpen 4:c1beacfc42c7 268
MikamiUitOpen 4:c1beacfc42c7 269 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 270 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 271 \return 0 Function succeeded
MikamiUitOpen 4:c1beacfc42c7 272 \return 1 Function failed
MikamiUitOpen 4:c1beacfc42c7 273 */
MikamiUitOpen 4:c1beacfc42c7 274 #define __STREXH(value, ptr) __strex(value, ptr)
MikamiUitOpen 4:c1beacfc42c7 275
MikamiUitOpen 4:c1beacfc42c7 276
MikamiUitOpen 4:c1beacfc42c7 277 /** \brief STR Exclusive (32 bit)
MikamiUitOpen 4:c1beacfc42c7 278
MikamiUitOpen 4:c1beacfc42c7 279 This function executes a exclusive STR instruction for 32 bit values.
MikamiUitOpen 4:c1beacfc42c7 280
MikamiUitOpen 4:c1beacfc42c7 281 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 282 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 283 \return 0 Function succeeded
MikamiUitOpen 4:c1beacfc42c7 284 \return 1 Function failed
MikamiUitOpen 4:c1beacfc42c7 285 */
MikamiUitOpen 4:c1beacfc42c7 286 #define __STREXW(value, ptr) __strex(value, ptr)
MikamiUitOpen 4:c1beacfc42c7 287
MikamiUitOpen 4:c1beacfc42c7 288
MikamiUitOpen 4:c1beacfc42c7 289 /** \brief Remove the exclusive lock
MikamiUitOpen 4:c1beacfc42c7 290
MikamiUitOpen 4:c1beacfc42c7 291 This function removes the exclusive lock which is created by LDREX.
MikamiUitOpen 4:c1beacfc42c7 292
MikamiUitOpen 4:c1beacfc42c7 293 */
MikamiUitOpen 4:c1beacfc42c7 294 #define __CLREX __clrex
MikamiUitOpen 4:c1beacfc42c7 295
MikamiUitOpen 4:c1beacfc42c7 296
MikamiUitOpen 4:c1beacfc42c7 297 /** \brief Signed Saturate
MikamiUitOpen 4:c1beacfc42c7 298
MikamiUitOpen 4:c1beacfc42c7 299 This function saturates a signed value.
MikamiUitOpen 4:c1beacfc42c7 300
MikamiUitOpen 4:c1beacfc42c7 301 \param [in] value Value to be saturated
MikamiUitOpen 4:c1beacfc42c7 302 \param [in] sat Bit position to saturate to (1..32)
MikamiUitOpen 4:c1beacfc42c7 303 \return Saturated value
MikamiUitOpen 4:c1beacfc42c7 304 */
MikamiUitOpen 4:c1beacfc42c7 305 #define __SSAT __ssat
MikamiUitOpen 4:c1beacfc42c7 306
MikamiUitOpen 4:c1beacfc42c7 307
MikamiUitOpen 4:c1beacfc42c7 308 /** \brief Unsigned Saturate
MikamiUitOpen 4:c1beacfc42c7 309
MikamiUitOpen 4:c1beacfc42c7 310 This function saturates an unsigned value.
MikamiUitOpen 4:c1beacfc42c7 311
MikamiUitOpen 4:c1beacfc42c7 312 \param [in] value Value to be saturated
MikamiUitOpen 4:c1beacfc42c7 313 \param [in] sat Bit position to saturate to (0..31)
MikamiUitOpen 4:c1beacfc42c7 314 \return Saturated value
MikamiUitOpen 4:c1beacfc42c7 315 */
MikamiUitOpen 4:c1beacfc42c7 316 #define __USAT __usat
MikamiUitOpen 4:c1beacfc42c7 317
MikamiUitOpen 4:c1beacfc42c7 318
MikamiUitOpen 4:c1beacfc42c7 319 /** \brief Rotate Right with Extend (32 bit)
MikamiUitOpen 4:c1beacfc42c7 320
MikamiUitOpen 4:c1beacfc42c7 321 This function moves each bit of a bitstring right by one bit.
MikamiUitOpen 4:c1beacfc42c7 322 The carry input is shifted in at the left end of the bitstring.
MikamiUitOpen 4:c1beacfc42c7 323
MikamiUitOpen 4:c1beacfc42c7 324 \param [in] value Value to rotate
MikamiUitOpen 4:c1beacfc42c7 325 \return Rotated value
MikamiUitOpen 4:c1beacfc42c7 326 */
MikamiUitOpen 4:c1beacfc42c7 327 #ifndef __NO_EMBEDDED_ASM
MikamiUitOpen 4:c1beacfc42c7 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 329 {
MikamiUitOpen 4:c1beacfc42c7 330 rrx r0, r0
MikamiUitOpen 4:c1beacfc42c7 331 bx lr
MikamiUitOpen 4:c1beacfc42c7 332 }
MikamiUitOpen 4:c1beacfc42c7 333 #endif
MikamiUitOpen 4:c1beacfc42c7 334
MikamiUitOpen 4:c1beacfc42c7 335
MikamiUitOpen 4:c1beacfc42c7 336 /** \brief LDRT Unprivileged (8 bit)
MikamiUitOpen 4:c1beacfc42c7 337
MikamiUitOpen 4:c1beacfc42c7 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
MikamiUitOpen 4:c1beacfc42c7 339
MikamiUitOpen 4:c1beacfc42c7 340 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 341 \return value of type uint8_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 342 */
MikamiUitOpen 4:c1beacfc42c7 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
MikamiUitOpen 4:c1beacfc42c7 344
MikamiUitOpen 4:c1beacfc42c7 345
MikamiUitOpen 4:c1beacfc42c7 346 /** \brief LDRT Unprivileged (16 bit)
MikamiUitOpen 4:c1beacfc42c7 347
MikamiUitOpen 4:c1beacfc42c7 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
MikamiUitOpen 4:c1beacfc42c7 349
MikamiUitOpen 4:c1beacfc42c7 350 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 351 \return value of type uint16_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 352 */
MikamiUitOpen 4:c1beacfc42c7 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
MikamiUitOpen 4:c1beacfc42c7 354
MikamiUitOpen 4:c1beacfc42c7 355
MikamiUitOpen 4:c1beacfc42c7 356 /** \brief LDRT Unprivileged (32 bit)
MikamiUitOpen 4:c1beacfc42c7 357
MikamiUitOpen 4:c1beacfc42c7 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
MikamiUitOpen 4:c1beacfc42c7 359
MikamiUitOpen 4:c1beacfc42c7 360 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 361 \return value of type uint32_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 362 */
MikamiUitOpen 4:c1beacfc42c7 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
MikamiUitOpen 4:c1beacfc42c7 364
MikamiUitOpen 4:c1beacfc42c7 365
MikamiUitOpen 4:c1beacfc42c7 366 /** \brief STRT Unprivileged (8 bit)
MikamiUitOpen 4:c1beacfc42c7 367
MikamiUitOpen 4:c1beacfc42c7 368 This function executes a Unprivileged STRT instruction for 8 bit values.
MikamiUitOpen 4:c1beacfc42c7 369
MikamiUitOpen 4:c1beacfc42c7 370 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 371 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 372 */
MikamiUitOpen 4:c1beacfc42c7 373 #define __STRBT(value, ptr) __strt(value, ptr)
MikamiUitOpen 4:c1beacfc42c7 374
MikamiUitOpen 4:c1beacfc42c7 375
MikamiUitOpen 4:c1beacfc42c7 376 /** \brief STRT Unprivileged (16 bit)
MikamiUitOpen 4:c1beacfc42c7 377
MikamiUitOpen 4:c1beacfc42c7 378 This function executes a Unprivileged STRT instruction for 16 bit values.
MikamiUitOpen 4:c1beacfc42c7 379
MikamiUitOpen 4:c1beacfc42c7 380 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 381 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 382 */
MikamiUitOpen 4:c1beacfc42c7 383 #define __STRHT(value, ptr) __strt(value, ptr)
MikamiUitOpen 4:c1beacfc42c7 384
MikamiUitOpen 4:c1beacfc42c7 385
MikamiUitOpen 4:c1beacfc42c7 386 /** \brief STRT Unprivileged (32 bit)
MikamiUitOpen 4:c1beacfc42c7 387
MikamiUitOpen 4:c1beacfc42c7 388 This function executes a Unprivileged STRT instruction for 32 bit values.
MikamiUitOpen 4:c1beacfc42c7 389
MikamiUitOpen 4:c1beacfc42c7 390 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 391 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 392 */
MikamiUitOpen 4:c1beacfc42c7 393 #define __STRT(value, ptr) __strt(value, ptr)
MikamiUitOpen 4:c1beacfc42c7 394
MikamiUitOpen 4:c1beacfc42c7 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 4:c1beacfc42c7 396
MikamiUitOpen 4:c1beacfc42c7 397
MikamiUitOpen 4:c1beacfc42c7 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
MikamiUitOpen 4:c1beacfc42c7 399 /* GNU gcc specific functions */
MikamiUitOpen 4:c1beacfc42c7 400
MikamiUitOpen 4:c1beacfc42c7 401 /* Define macros for porting to both thumb1 and thumb2.
MikamiUitOpen 4:c1beacfc42c7 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
MikamiUitOpen 4:c1beacfc42c7 403 * Otherwise, use general registers, specified by constrant "r" */
MikamiUitOpen 4:c1beacfc42c7 404 #if defined (__thumb__) && !defined (__thumb2__)
MikamiUitOpen 4:c1beacfc42c7 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
MikamiUitOpen 4:c1beacfc42c7 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
MikamiUitOpen 4:c1beacfc42c7 407 #else
MikamiUitOpen 4:c1beacfc42c7 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
MikamiUitOpen 4:c1beacfc42c7 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
MikamiUitOpen 4:c1beacfc42c7 410 #endif
MikamiUitOpen 4:c1beacfc42c7 411
MikamiUitOpen 4:c1beacfc42c7 412 /** \brief No Operation
MikamiUitOpen 4:c1beacfc42c7 413
MikamiUitOpen 4:c1beacfc42c7 414 No Operation does nothing. This instruction can be used for code alignment purposes.
MikamiUitOpen 4:c1beacfc42c7 415 */
MikamiUitOpen 4:c1beacfc42c7 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
MikamiUitOpen 4:c1beacfc42c7 417 {
MikamiUitOpen 4:c1beacfc42c7 418 __ASM volatile ("nop");
MikamiUitOpen 4:c1beacfc42c7 419 }
MikamiUitOpen 4:c1beacfc42c7 420
MikamiUitOpen 4:c1beacfc42c7 421
MikamiUitOpen 4:c1beacfc42c7 422 /** \brief Wait For Interrupt
MikamiUitOpen 4:c1beacfc42c7 423
MikamiUitOpen 4:c1beacfc42c7 424 Wait For Interrupt is a hint instruction that suspends execution
MikamiUitOpen 4:c1beacfc42c7 425 until one of a number of events occurs.
MikamiUitOpen 4:c1beacfc42c7 426 */
MikamiUitOpen 4:c1beacfc42c7 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
MikamiUitOpen 4:c1beacfc42c7 428 {
MikamiUitOpen 4:c1beacfc42c7 429 __ASM volatile ("wfi");
MikamiUitOpen 4:c1beacfc42c7 430 }
MikamiUitOpen 4:c1beacfc42c7 431
MikamiUitOpen 4:c1beacfc42c7 432
MikamiUitOpen 4:c1beacfc42c7 433 /** \brief Wait For Event
MikamiUitOpen 4:c1beacfc42c7 434
MikamiUitOpen 4:c1beacfc42c7 435 Wait For Event is a hint instruction that permits the processor to enter
MikamiUitOpen 4:c1beacfc42c7 436 a low-power state until one of a number of events occurs.
MikamiUitOpen 4:c1beacfc42c7 437 */
MikamiUitOpen 4:c1beacfc42c7 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
MikamiUitOpen 4:c1beacfc42c7 439 {
MikamiUitOpen 4:c1beacfc42c7 440 __ASM volatile ("wfe");
MikamiUitOpen 4:c1beacfc42c7 441 }
MikamiUitOpen 4:c1beacfc42c7 442
MikamiUitOpen 4:c1beacfc42c7 443
MikamiUitOpen 4:c1beacfc42c7 444 /** \brief Send Event
MikamiUitOpen 4:c1beacfc42c7 445
MikamiUitOpen 4:c1beacfc42c7 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
MikamiUitOpen 4:c1beacfc42c7 447 */
MikamiUitOpen 4:c1beacfc42c7 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
MikamiUitOpen 4:c1beacfc42c7 449 {
MikamiUitOpen 4:c1beacfc42c7 450 __ASM volatile ("sev");
MikamiUitOpen 4:c1beacfc42c7 451 }
MikamiUitOpen 4:c1beacfc42c7 452
MikamiUitOpen 4:c1beacfc42c7 453
MikamiUitOpen 4:c1beacfc42c7 454 /** \brief Instruction Synchronization Barrier
MikamiUitOpen 4:c1beacfc42c7 455
MikamiUitOpen 4:c1beacfc42c7 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
MikamiUitOpen 4:c1beacfc42c7 457 so that all instructions following the ISB are fetched from cache or
MikamiUitOpen 4:c1beacfc42c7 458 memory, after the instruction has been completed.
MikamiUitOpen 4:c1beacfc42c7 459 */
MikamiUitOpen 4:c1beacfc42c7 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
MikamiUitOpen 4:c1beacfc42c7 461 {
MikamiUitOpen 4:c1beacfc42c7 462 __ASM volatile ("isb 0xF":::"memory");
MikamiUitOpen 4:c1beacfc42c7 463 }
MikamiUitOpen 4:c1beacfc42c7 464
MikamiUitOpen 4:c1beacfc42c7 465
MikamiUitOpen 4:c1beacfc42c7 466 /** \brief Data Synchronization Barrier
MikamiUitOpen 4:c1beacfc42c7 467
MikamiUitOpen 4:c1beacfc42c7 468 This function acts as a special kind of Data Memory Barrier.
MikamiUitOpen 4:c1beacfc42c7 469 It completes when all explicit memory accesses before this instruction complete.
MikamiUitOpen 4:c1beacfc42c7 470 */
MikamiUitOpen 4:c1beacfc42c7 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
MikamiUitOpen 4:c1beacfc42c7 472 {
MikamiUitOpen 4:c1beacfc42c7 473 __ASM volatile ("dsb 0xF":::"memory");
MikamiUitOpen 4:c1beacfc42c7 474 }
MikamiUitOpen 4:c1beacfc42c7 475
MikamiUitOpen 4:c1beacfc42c7 476
MikamiUitOpen 4:c1beacfc42c7 477 /** \brief Data Memory Barrier
MikamiUitOpen 4:c1beacfc42c7 478
MikamiUitOpen 4:c1beacfc42c7 479 This function ensures the apparent order of the explicit memory operations before
MikamiUitOpen 4:c1beacfc42c7 480 and after the instruction, without ensuring their completion.
MikamiUitOpen 4:c1beacfc42c7 481 */
MikamiUitOpen 4:c1beacfc42c7 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
MikamiUitOpen 4:c1beacfc42c7 483 {
MikamiUitOpen 4:c1beacfc42c7 484 __ASM volatile ("dmb 0xF":::"memory");
MikamiUitOpen 4:c1beacfc42c7 485 }
MikamiUitOpen 4:c1beacfc42c7 486
MikamiUitOpen 4:c1beacfc42c7 487
MikamiUitOpen 4:c1beacfc42c7 488 /** \brief Reverse byte order (32 bit)
MikamiUitOpen 4:c1beacfc42c7 489
MikamiUitOpen 4:c1beacfc42c7 490 This function reverses the byte order in integer value.
MikamiUitOpen 4:c1beacfc42c7 491
MikamiUitOpen 4:c1beacfc42c7 492 \param [in] value Value to reverse
MikamiUitOpen 4:c1beacfc42c7 493 \return Reversed value
MikamiUitOpen 4:c1beacfc42c7 494 */
MikamiUitOpen 4:c1beacfc42c7 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 496 {
MikamiUitOpen 4:c1beacfc42c7 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
MikamiUitOpen 4:c1beacfc42c7 498 return __builtin_bswap32(value);
MikamiUitOpen 4:c1beacfc42c7 499 #else
MikamiUitOpen 4:c1beacfc42c7 500 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 501
MikamiUitOpen 4:c1beacfc42c7 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 4:c1beacfc42c7 503 return(result);
MikamiUitOpen 4:c1beacfc42c7 504 #endif
MikamiUitOpen 4:c1beacfc42c7 505 }
MikamiUitOpen 4:c1beacfc42c7 506
MikamiUitOpen 4:c1beacfc42c7 507
MikamiUitOpen 4:c1beacfc42c7 508 /** \brief Reverse byte order (16 bit)
MikamiUitOpen 4:c1beacfc42c7 509
MikamiUitOpen 4:c1beacfc42c7 510 This function reverses the byte order in two unsigned short values.
MikamiUitOpen 4:c1beacfc42c7 511
MikamiUitOpen 4:c1beacfc42c7 512 \param [in] value Value to reverse
MikamiUitOpen 4:c1beacfc42c7 513 \return Reversed value
MikamiUitOpen 4:c1beacfc42c7 514 */
MikamiUitOpen 4:c1beacfc42c7 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 516 {
MikamiUitOpen 4:c1beacfc42c7 517 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 518
MikamiUitOpen 4:c1beacfc42c7 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 4:c1beacfc42c7 520 return(result);
MikamiUitOpen 4:c1beacfc42c7 521 }
MikamiUitOpen 4:c1beacfc42c7 522
MikamiUitOpen 4:c1beacfc42c7 523
MikamiUitOpen 4:c1beacfc42c7 524 /** \brief Reverse byte order in signed short value
MikamiUitOpen 4:c1beacfc42c7 525
MikamiUitOpen 4:c1beacfc42c7 526 This function reverses the byte order in a signed short value with sign extension to integer.
MikamiUitOpen 4:c1beacfc42c7 527
MikamiUitOpen 4:c1beacfc42c7 528 \param [in] value Value to reverse
MikamiUitOpen 4:c1beacfc42c7 529 \return Reversed value
MikamiUitOpen 4:c1beacfc42c7 530 */
MikamiUitOpen 4:c1beacfc42c7 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
MikamiUitOpen 4:c1beacfc42c7 532 {
MikamiUitOpen 4:c1beacfc42c7 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 4:c1beacfc42c7 534 return (short)__builtin_bswap16(value);
MikamiUitOpen 4:c1beacfc42c7 535 #else
MikamiUitOpen 4:c1beacfc42c7 536 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 537
MikamiUitOpen 4:c1beacfc42c7 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 4:c1beacfc42c7 539 return(result);
MikamiUitOpen 4:c1beacfc42c7 540 #endif
MikamiUitOpen 4:c1beacfc42c7 541 }
MikamiUitOpen 4:c1beacfc42c7 542
MikamiUitOpen 4:c1beacfc42c7 543
MikamiUitOpen 4:c1beacfc42c7 544 /** \brief Rotate Right in unsigned value (32 bit)
MikamiUitOpen 4:c1beacfc42c7 545
MikamiUitOpen 4:c1beacfc42c7 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
MikamiUitOpen 4:c1beacfc42c7 547
MikamiUitOpen 4:c1beacfc42c7 548 \param [in] value Value to rotate
MikamiUitOpen 4:c1beacfc42c7 549 \param [in] value Number of Bits to rotate
MikamiUitOpen 4:c1beacfc42c7 550 \return Rotated value
MikamiUitOpen 4:c1beacfc42c7 551 */
MikamiUitOpen 4:c1beacfc42c7 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
MikamiUitOpen 4:c1beacfc42c7 553 {
MikamiUitOpen 4:c1beacfc42c7 554 return (op1 >> op2) | (op1 << (32 - op2));
MikamiUitOpen 4:c1beacfc42c7 555 }
MikamiUitOpen 4:c1beacfc42c7 556
MikamiUitOpen 4:c1beacfc42c7 557
MikamiUitOpen 4:c1beacfc42c7 558 /** \brief Breakpoint
MikamiUitOpen 4:c1beacfc42c7 559
MikamiUitOpen 4:c1beacfc42c7 560 This function causes the processor to enter Debug state.
MikamiUitOpen 4:c1beacfc42c7 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
MikamiUitOpen 4:c1beacfc42c7 562
MikamiUitOpen 4:c1beacfc42c7 563 \param [in] value is ignored by the processor.
MikamiUitOpen 4:c1beacfc42c7 564 If required, a debugger can use it to store additional information about the breakpoint.
MikamiUitOpen 4:c1beacfc42c7 565 */
MikamiUitOpen 4:c1beacfc42c7 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
MikamiUitOpen 4:c1beacfc42c7 567
MikamiUitOpen 4:c1beacfc42c7 568
MikamiUitOpen 4:c1beacfc42c7 569 /** \brief Reverse bit order of value
MikamiUitOpen 4:c1beacfc42c7 570
MikamiUitOpen 4:c1beacfc42c7 571 This function reverses the bit order of the given value.
MikamiUitOpen 4:c1beacfc42c7 572
MikamiUitOpen 4:c1beacfc42c7 573 \param [in] value Value to reverse
MikamiUitOpen 4:c1beacfc42c7 574 \return Reversed value
MikamiUitOpen 4:c1beacfc42c7 575 */
MikamiUitOpen 4:c1beacfc42c7 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 577 {
MikamiUitOpen 4:c1beacfc42c7 578 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 579
MikamiUitOpen 4:c1beacfc42c7 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 4:c1beacfc42c7 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
MikamiUitOpen 4:c1beacfc42c7 582 #else
MikamiUitOpen 4:c1beacfc42c7 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
MikamiUitOpen 4:c1beacfc42c7 584
MikamiUitOpen 4:c1beacfc42c7 585 result = value; // r will be reversed bits of v; first get LSB of v
MikamiUitOpen 4:c1beacfc42c7 586 for (value >>= 1; value; value >>= 1)
MikamiUitOpen 4:c1beacfc42c7 587 {
MikamiUitOpen 4:c1beacfc42c7 588 result <<= 1;
MikamiUitOpen 4:c1beacfc42c7 589 result |= value & 1;
MikamiUitOpen 4:c1beacfc42c7 590 s--;
MikamiUitOpen 4:c1beacfc42c7 591 }
MikamiUitOpen 4:c1beacfc42c7 592 result <<= s; // shift when v's highest bits are zero
MikamiUitOpen 4:c1beacfc42c7 593 #endif
MikamiUitOpen 4:c1beacfc42c7 594 return(result);
MikamiUitOpen 4:c1beacfc42c7 595 }
MikamiUitOpen 4:c1beacfc42c7 596
MikamiUitOpen 4:c1beacfc42c7 597
MikamiUitOpen 4:c1beacfc42c7 598 /** \brief Count leading zeros
MikamiUitOpen 4:c1beacfc42c7 599
MikamiUitOpen 4:c1beacfc42c7 600 This function counts the number of leading zeros of a data value.
MikamiUitOpen 4:c1beacfc42c7 601
MikamiUitOpen 4:c1beacfc42c7 602 \param [in] value Value to count the leading zeros
MikamiUitOpen 4:c1beacfc42c7 603 \return number of leading zeros in value
MikamiUitOpen 4:c1beacfc42c7 604 */
MikamiUitOpen 4:c1beacfc42c7 605 #define __CLZ __builtin_clz
MikamiUitOpen 4:c1beacfc42c7 606
MikamiUitOpen 4:c1beacfc42c7 607
MikamiUitOpen 4:c1beacfc42c7 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
MikamiUitOpen 4:c1beacfc42c7 609
MikamiUitOpen 4:c1beacfc42c7 610 /** \brief LDR Exclusive (8 bit)
MikamiUitOpen 4:c1beacfc42c7 611
MikamiUitOpen 4:c1beacfc42c7 612 This function executes a exclusive LDR instruction for 8 bit value.
MikamiUitOpen 4:c1beacfc42c7 613
MikamiUitOpen 4:c1beacfc42c7 614 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 615 \return value of type uint8_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 616 */
MikamiUitOpen 4:c1beacfc42c7 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
MikamiUitOpen 4:c1beacfc42c7 618 {
MikamiUitOpen 4:c1beacfc42c7 619 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 620
MikamiUitOpen 4:c1beacfc42c7 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 4:c1beacfc42c7 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 4:c1beacfc42c7 623 #else
MikamiUitOpen 4:c1beacfc42c7 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 4:c1beacfc42c7 625 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 4:c1beacfc42c7 626 */
MikamiUitOpen 4:c1beacfc42c7 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 4:c1beacfc42c7 628 #endif
MikamiUitOpen 4:c1beacfc42c7 629 return ((uint8_t) result); /* Add explicit type cast here */
MikamiUitOpen 4:c1beacfc42c7 630 }
MikamiUitOpen 4:c1beacfc42c7 631
MikamiUitOpen 4:c1beacfc42c7 632
MikamiUitOpen 4:c1beacfc42c7 633 /** \brief LDR Exclusive (16 bit)
MikamiUitOpen 4:c1beacfc42c7 634
MikamiUitOpen 4:c1beacfc42c7 635 This function executes a exclusive LDR instruction for 16 bit values.
MikamiUitOpen 4:c1beacfc42c7 636
MikamiUitOpen 4:c1beacfc42c7 637 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 638 \return value of type uint16_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 639 */
MikamiUitOpen 4:c1beacfc42c7 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
MikamiUitOpen 4:c1beacfc42c7 641 {
MikamiUitOpen 4:c1beacfc42c7 642 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 643
MikamiUitOpen 4:c1beacfc42c7 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 4:c1beacfc42c7 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 4:c1beacfc42c7 646 #else
MikamiUitOpen 4:c1beacfc42c7 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 4:c1beacfc42c7 648 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 4:c1beacfc42c7 649 */
MikamiUitOpen 4:c1beacfc42c7 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 4:c1beacfc42c7 651 #endif
MikamiUitOpen 4:c1beacfc42c7 652 return ((uint16_t) result); /* Add explicit type cast here */
MikamiUitOpen 4:c1beacfc42c7 653 }
MikamiUitOpen 4:c1beacfc42c7 654
MikamiUitOpen 4:c1beacfc42c7 655
MikamiUitOpen 4:c1beacfc42c7 656 /** \brief LDR Exclusive (32 bit)
MikamiUitOpen 4:c1beacfc42c7 657
MikamiUitOpen 4:c1beacfc42c7 658 This function executes a exclusive LDR instruction for 32 bit values.
MikamiUitOpen 4:c1beacfc42c7 659
MikamiUitOpen 4:c1beacfc42c7 660 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 661 \return value of type uint32_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 662 */
MikamiUitOpen 4:c1beacfc42c7 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
MikamiUitOpen 4:c1beacfc42c7 664 {
MikamiUitOpen 4:c1beacfc42c7 665 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 666
MikamiUitOpen 4:c1beacfc42c7 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 4:c1beacfc42c7 668 return(result);
MikamiUitOpen 4:c1beacfc42c7 669 }
MikamiUitOpen 4:c1beacfc42c7 670
MikamiUitOpen 4:c1beacfc42c7 671
MikamiUitOpen 4:c1beacfc42c7 672 /** \brief STR Exclusive (8 bit)
MikamiUitOpen 4:c1beacfc42c7 673
MikamiUitOpen 4:c1beacfc42c7 674 This function executes a exclusive STR instruction for 8 bit values.
MikamiUitOpen 4:c1beacfc42c7 675
MikamiUitOpen 4:c1beacfc42c7 676 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 677 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 678 \return 0 Function succeeded
MikamiUitOpen 4:c1beacfc42c7 679 \return 1 Function failed
MikamiUitOpen 4:c1beacfc42c7 680 */
MikamiUitOpen 4:c1beacfc42c7 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
MikamiUitOpen 4:c1beacfc42c7 682 {
MikamiUitOpen 4:c1beacfc42c7 683 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 684
MikamiUitOpen 4:c1beacfc42c7 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 4:c1beacfc42c7 686 return(result);
MikamiUitOpen 4:c1beacfc42c7 687 }
MikamiUitOpen 4:c1beacfc42c7 688
MikamiUitOpen 4:c1beacfc42c7 689
MikamiUitOpen 4:c1beacfc42c7 690 /** \brief STR Exclusive (16 bit)
MikamiUitOpen 4:c1beacfc42c7 691
MikamiUitOpen 4:c1beacfc42c7 692 This function executes a exclusive STR instruction for 16 bit values.
MikamiUitOpen 4:c1beacfc42c7 693
MikamiUitOpen 4:c1beacfc42c7 694 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 695 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 696 \return 0 Function succeeded
MikamiUitOpen 4:c1beacfc42c7 697 \return 1 Function failed
MikamiUitOpen 4:c1beacfc42c7 698 */
MikamiUitOpen 4:c1beacfc42c7 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
MikamiUitOpen 4:c1beacfc42c7 700 {
MikamiUitOpen 4:c1beacfc42c7 701 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 702
MikamiUitOpen 4:c1beacfc42c7 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 4:c1beacfc42c7 704 return(result);
MikamiUitOpen 4:c1beacfc42c7 705 }
MikamiUitOpen 4:c1beacfc42c7 706
MikamiUitOpen 4:c1beacfc42c7 707
MikamiUitOpen 4:c1beacfc42c7 708 /** \brief STR Exclusive (32 bit)
MikamiUitOpen 4:c1beacfc42c7 709
MikamiUitOpen 4:c1beacfc42c7 710 This function executes a exclusive STR instruction for 32 bit values.
MikamiUitOpen 4:c1beacfc42c7 711
MikamiUitOpen 4:c1beacfc42c7 712 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 713 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 714 \return 0 Function succeeded
MikamiUitOpen 4:c1beacfc42c7 715 \return 1 Function failed
MikamiUitOpen 4:c1beacfc42c7 716 */
MikamiUitOpen 4:c1beacfc42c7 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
MikamiUitOpen 4:c1beacfc42c7 718 {
MikamiUitOpen 4:c1beacfc42c7 719 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 720
MikamiUitOpen 4:c1beacfc42c7 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
MikamiUitOpen 4:c1beacfc42c7 722 return(result);
MikamiUitOpen 4:c1beacfc42c7 723 }
MikamiUitOpen 4:c1beacfc42c7 724
MikamiUitOpen 4:c1beacfc42c7 725
MikamiUitOpen 4:c1beacfc42c7 726 /** \brief Remove the exclusive lock
MikamiUitOpen 4:c1beacfc42c7 727
MikamiUitOpen 4:c1beacfc42c7 728 This function removes the exclusive lock which is created by LDREX.
MikamiUitOpen 4:c1beacfc42c7 729
MikamiUitOpen 4:c1beacfc42c7 730 */
MikamiUitOpen 4:c1beacfc42c7 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
MikamiUitOpen 4:c1beacfc42c7 732 {
MikamiUitOpen 4:c1beacfc42c7 733 __ASM volatile ("clrex" ::: "memory");
MikamiUitOpen 4:c1beacfc42c7 734 }
MikamiUitOpen 4:c1beacfc42c7 735
MikamiUitOpen 4:c1beacfc42c7 736
MikamiUitOpen 4:c1beacfc42c7 737 /** \brief Signed Saturate
MikamiUitOpen 4:c1beacfc42c7 738
MikamiUitOpen 4:c1beacfc42c7 739 This function saturates a signed value.
MikamiUitOpen 4:c1beacfc42c7 740
MikamiUitOpen 4:c1beacfc42c7 741 \param [in] value Value to be saturated
MikamiUitOpen 4:c1beacfc42c7 742 \param [in] sat Bit position to saturate to (1..32)
MikamiUitOpen 4:c1beacfc42c7 743 \return Saturated value
MikamiUitOpen 4:c1beacfc42c7 744 */
MikamiUitOpen 4:c1beacfc42c7 745 #define __SSAT(ARG1,ARG2) \
MikamiUitOpen 4:c1beacfc42c7 746 ({ \
MikamiUitOpen 4:c1beacfc42c7 747 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 4:c1beacfc42c7 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 4:c1beacfc42c7 749 __RES; \
MikamiUitOpen 4:c1beacfc42c7 750 })
MikamiUitOpen 4:c1beacfc42c7 751
MikamiUitOpen 4:c1beacfc42c7 752
MikamiUitOpen 4:c1beacfc42c7 753 /** \brief Unsigned Saturate
MikamiUitOpen 4:c1beacfc42c7 754
MikamiUitOpen 4:c1beacfc42c7 755 This function saturates an unsigned value.
MikamiUitOpen 4:c1beacfc42c7 756
MikamiUitOpen 4:c1beacfc42c7 757 \param [in] value Value to be saturated
MikamiUitOpen 4:c1beacfc42c7 758 \param [in] sat Bit position to saturate to (0..31)
MikamiUitOpen 4:c1beacfc42c7 759 \return Saturated value
MikamiUitOpen 4:c1beacfc42c7 760 */
MikamiUitOpen 4:c1beacfc42c7 761 #define __USAT(ARG1,ARG2) \
MikamiUitOpen 4:c1beacfc42c7 762 ({ \
MikamiUitOpen 4:c1beacfc42c7 763 uint32_t __RES, __ARG1 = (ARG1); \
MikamiUitOpen 4:c1beacfc42c7 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
MikamiUitOpen 4:c1beacfc42c7 765 __RES; \
MikamiUitOpen 4:c1beacfc42c7 766 })
MikamiUitOpen 4:c1beacfc42c7 767
MikamiUitOpen 4:c1beacfc42c7 768
MikamiUitOpen 4:c1beacfc42c7 769 /** \brief Rotate Right with Extend (32 bit)
MikamiUitOpen 4:c1beacfc42c7 770
MikamiUitOpen 4:c1beacfc42c7 771 This function moves each bit of a bitstring right by one bit.
MikamiUitOpen 4:c1beacfc42c7 772 The carry input is shifted in at the left end of the bitstring.
MikamiUitOpen 4:c1beacfc42c7 773
MikamiUitOpen 4:c1beacfc42c7 774 \param [in] value Value to rotate
MikamiUitOpen 4:c1beacfc42c7 775 \return Rotated value
MikamiUitOpen 4:c1beacfc42c7 776 */
MikamiUitOpen 4:c1beacfc42c7 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
MikamiUitOpen 4:c1beacfc42c7 778 {
MikamiUitOpen 4:c1beacfc42c7 779 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 780
MikamiUitOpen 4:c1beacfc42c7 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
MikamiUitOpen 4:c1beacfc42c7 782 return(result);
MikamiUitOpen 4:c1beacfc42c7 783 }
MikamiUitOpen 4:c1beacfc42c7 784
MikamiUitOpen 4:c1beacfc42c7 785
MikamiUitOpen 4:c1beacfc42c7 786 /** \brief LDRT Unprivileged (8 bit)
MikamiUitOpen 4:c1beacfc42c7 787
MikamiUitOpen 4:c1beacfc42c7 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
MikamiUitOpen 4:c1beacfc42c7 789
MikamiUitOpen 4:c1beacfc42c7 790 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 791 \return value of type uint8_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 792 */
MikamiUitOpen 4:c1beacfc42c7 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
MikamiUitOpen 4:c1beacfc42c7 794 {
MikamiUitOpen 4:c1beacfc42c7 795 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 796
MikamiUitOpen 4:c1beacfc42c7 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 4:c1beacfc42c7 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 4:c1beacfc42c7 799 #else
MikamiUitOpen 4:c1beacfc42c7 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 4:c1beacfc42c7 801 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 4:c1beacfc42c7 802 */
MikamiUitOpen 4:c1beacfc42c7 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 4:c1beacfc42c7 804 #endif
MikamiUitOpen 4:c1beacfc42c7 805 return ((uint8_t) result); /* Add explicit type cast here */
MikamiUitOpen 4:c1beacfc42c7 806 }
MikamiUitOpen 4:c1beacfc42c7 807
MikamiUitOpen 4:c1beacfc42c7 808
MikamiUitOpen 4:c1beacfc42c7 809 /** \brief LDRT Unprivileged (16 bit)
MikamiUitOpen 4:c1beacfc42c7 810
MikamiUitOpen 4:c1beacfc42c7 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
MikamiUitOpen 4:c1beacfc42c7 812
MikamiUitOpen 4:c1beacfc42c7 813 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 814 \return value of type uint16_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 815 */
MikamiUitOpen 4:c1beacfc42c7 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
MikamiUitOpen 4:c1beacfc42c7 817 {
MikamiUitOpen 4:c1beacfc42c7 818 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 819
MikamiUitOpen 4:c1beacfc42c7 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
MikamiUitOpen 4:c1beacfc42c7 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 4:c1beacfc42c7 822 #else
MikamiUitOpen 4:c1beacfc42c7 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
MikamiUitOpen 4:c1beacfc42c7 824 accepted by assembler. So has to use following less efficient pattern.
MikamiUitOpen 4:c1beacfc42c7 825 */
MikamiUitOpen 4:c1beacfc42c7 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
MikamiUitOpen 4:c1beacfc42c7 827 #endif
MikamiUitOpen 4:c1beacfc42c7 828 return ((uint16_t) result); /* Add explicit type cast here */
MikamiUitOpen 4:c1beacfc42c7 829 }
MikamiUitOpen 4:c1beacfc42c7 830
MikamiUitOpen 4:c1beacfc42c7 831
MikamiUitOpen 4:c1beacfc42c7 832 /** \brief LDRT Unprivileged (32 bit)
MikamiUitOpen 4:c1beacfc42c7 833
MikamiUitOpen 4:c1beacfc42c7 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
MikamiUitOpen 4:c1beacfc42c7 835
MikamiUitOpen 4:c1beacfc42c7 836 \param [in] ptr Pointer to data
MikamiUitOpen 4:c1beacfc42c7 837 \return value of type uint32_t at (*ptr)
MikamiUitOpen 4:c1beacfc42c7 838 */
MikamiUitOpen 4:c1beacfc42c7 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
MikamiUitOpen 4:c1beacfc42c7 840 {
MikamiUitOpen 4:c1beacfc42c7 841 uint32_t result;
MikamiUitOpen 4:c1beacfc42c7 842
MikamiUitOpen 4:c1beacfc42c7 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
MikamiUitOpen 4:c1beacfc42c7 844 return(result);
MikamiUitOpen 4:c1beacfc42c7 845 }
MikamiUitOpen 4:c1beacfc42c7 846
MikamiUitOpen 4:c1beacfc42c7 847
MikamiUitOpen 4:c1beacfc42c7 848 /** \brief STRT Unprivileged (8 bit)
MikamiUitOpen 4:c1beacfc42c7 849
MikamiUitOpen 4:c1beacfc42c7 850 This function executes a Unprivileged STRT instruction for 8 bit values.
MikamiUitOpen 4:c1beacfc42c7 851
MikamiUitOpen 4:c1beacfc42c7 852 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 853 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 854 */
MikamiUitOpen 4:c1beacfc42c7 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
MikamiUitOpen 4:c1beacfc42c7 856 {
MikamiUitOpen 4:c1beacfc42c7 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 4:c1beacfc42c7 858 }
MikamiUitOpen 4:c1beacfc42c7 859
MikamiUitOpen 4:c1beacfc42c7 860
MikamiUitOpen 4:c1beacfc42c7 861 /** \brief STRT Unprivileged (16 bit)
MikamiUitOpen 4:c1beacfc42c7 862
MikamiUitOpen 4:c1beacfc42c7 863 This function executes a Unprivileged STRT instruction for 16 bit values.
MikamiUitOpen 4:c1beacfc42c7 864
MikamiUitOpen 4:c1beacfc42c7 865 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 866 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 867 */
MikamiUitOpen 4:c1beacfc42c7 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
MikamiUitOpen 4:c1beacfc42c7 869 {
MikamiUitOpen 4:c1beacfc42c7 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
MikamiUitOpen 4:c1beacfc42c7 871 }
MikamiUitOpen 4:c1beacfc42c7 872
MikamiUitOpen 4:c1beacfc42c7 873
MikamiUitOpen 4:c1beacfc42c7 874 /** \brief STRT Unprivileged (32 bit)
MikamiUitOpen 4:c1beacfc42c7 875
MikamiUitOpen 4:c1beacfc42c7 876 This function executes a Unprivileged STRT instruction for 32 bit values.
MikamiUitOpen 4:c1beacfc42c7 877
MikamiUitOpen 4:c1beacfc42c7 878 \param [in] value Value to store
MikamiUitOpen 4:c1beacfc42c7 879 \param [in] ptr Pointer to location
MikamiUitOpen 4:c1beacfc42c7 880 */
MikamiUitOpen 4:c1beacfc42c7 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
MikamiUitOpen 4:c1beacfc42c7 882 {
MikamiUitOpen 4:c1beacfc42c7 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
MikamiUitOpen 4:c1beacfc42c7 884 }
MikamiUitOpen 4:c1beacfc42c7 885
MikamiUitOpen 4:c1beacfc42c7 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
MikamiUitOpen 4:c1beacfc42c7 887
MikamiUitOpen 4:c1beacfc42c7 888
MikamiUitOpen 4:c1beacfc42c7 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
MikamiUitOpen 4:c1beacfc42c7 890 /* IAR iccarm specific functions */
MikamiUitOpen 4:c1beacfc42c7 891 #include <cmsis_iar.h>
MikamiUitOpen 4:c1beacfc42c7 892
MikamiUitOpen 4:c1beacfc42c7 893
MikamiUitOpen 4:c1beacfc42c7 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
MikamiUitOpen 4:c1beacfc42c7 895 /* TI CCS specific functions */
MikamiUitOpen 4:c1beacfc42c7 896 #include <cmsis_ccs.h>
MikamiUitOpen 4:c1beacfc42c7 897
MikamiUitOpen 4:c1beacfc42c7 898
MikamiUitOpen 4:c1beacfc42c7 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
MikamiUitOpen 4:c1beacfc42c7 900 /* TASKING carm specific functions */
MikamiUitOpen 4:c1beacfc42c7 901 /*
MikamiUitOpen 4:c1beacfc42c7 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
MikamiUitOpen 4:c1beacfc42c7 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
MikamiUitOpen 4:c1beacfc42c7 904 * Including the CMSIS ones.
MikamiUitOpen 4:c1beacfc42c7 905 */
MikamiUitOpen 4:c1beacfc42c7 906
MikamiUitOpen 4:c1beacfc42c7 907
MikamiUitOpen 4:c1beacfc42c7 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
MikamiUitOpen 4:c1beacfc42c7 909 /* Cosmic specific functions */
MikamiUitOpen 4:c1beacfc42c7 910 #include <cmsis_csm.h>
MikamiUitOpen 4:c1beacfc42c7 911
MikamiUitOpen 4:c1beacfc42c7 912 #endif
MikamiUitOpen 4:c1beacfc42c7 913
MikamiUitOpen 4:c1beacfc42c7 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
MikamiUitOpen 4:c1beacfc42c7 915
MikamiUitOpen 4:c1beacfc42c7 916 #endif /* __CORE_CMINSTR_H */